HFA3861IV96

HFA3861 ADVANCE INFORMATION Data Sheet July 1999 File Number 4699.1 Direct Sequence Spread Spectrum Baseband Processor The Intersil HFA3861 Direct Sequence Spread Spectrum (DSSS) baseband processor is part of the PRISM® 2.4GHz radio chipset, and contains all the functions necessary for a full or half duplex packet baseband transceiver. ™ Features • Complete DSSS Baseband Processor • Processing Gain . . . . . . . . . . . . . . . . . . . . FCC Compliant • Programmable Data Rate. . . . . . . . 1, 2, 5.5, and 11Mbps • Ultra Small Package . . . . . . . . . . . . . . . . . . . . . 10 x 10mm • Single Supply Operation (44MHz Max) . . . . . 2.7V to 3.6V • Modulation Methods . . . . . . . . DBPSK, DQPSK, and CCK • Supports Full or Half Duplex Operations • On-Chip A/D and D/A Converters for I/Q Data (6-Bit, 22MSPS), AGC, and Adaptive Power Control (7-Bit) • Targeted for Multipath Delay Spreads ~100ns • Supports Short Preamble Acquisition The HFA3861 has on-board A/D’s for analog I and Q inputs and outputs, for which the HFA3783 IF QMODEM is recommended. Differential phase shift keying modulation schemes DBPSK and DQPSK, with data scrambling capability, are available along with Complementary Code Keying to provide a variety of data rates. Built-in flexibility allows the HFA3861 to be configured through a general purpose control bus, for a range of applications. Both Receive and Transmit AGC functions with 7-bit AGC control obtain maximum performance in the analog portions of the transceiver. The HFA3861 is housed in a thin plastic quad flat package (TQFP) suitable for PCMCIA board applications. Applications • Enterprise WLAN Systems • Systems Targeting IEEE 802.11 Standard • DSSS PCMCIA Wireless Transceiver • Spread Spectrum WLAN RF Modems Ordering Information PART NO. HFA3861IV HFA3861IV96 TEMP. RANGE (oC) -40 to 85 -40 to 85 PKG. TYPE 64 Ld TQFP Tape and Reel PKG. NO. Q64.10x10 • TDMA Packet Protocol Radios • Part 15 Compliant Radio Links • Portable PDA/Notebook Computer • Wireless Digital Audio, Video, Multimedia Pinout SDI RESET TX_PE RX_PE CCA TX_RDY TXD VDDD GNDd TXCLK MD_RDY RXD RXCLK TEST7 TEST6 TEST5 • PCN/Wireless PBX • Wireless Bridges 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 GNDd VDDD SD SCLK R/W CS GNDd VDDD GNDa RX_I+ RX_IVDDA RX_Q+ RX_QGNDa VREF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDDA TX_AGC_IN RX-IF_DET GNDa IREF VDDA TX_I+ TX_IGNDa COMPCAP2 COMPRES2 GNDa TX_Q+ TX_QVDDA COMPRES1 TEST4 TEST3 TEST2 TEST1 TEST0 GNDd MCLK NC ANT-SEL ANT-SEL RX-RF_AGC VDDD GNDd TX_IF_AGC RX_IF_AGC COMPCAP1 Simplified Block Diagram ANT_SEL RX_RF_AGC RX_IF_DET RX_IF_AGC RX_I± RX_Q± VREF I/O TX_I± TX_Q± I DAC Q DAC TX DAC TX ADC 6 6 MOD THRESH. DETECT IF DAC I ADC Q ADC 1 1 7 AGC CTL 6 6 DEMOD DATA I/O TX_IF_AGC TX_AGC_IN 44MHz MCLK 7 6 TX ALC HFA 3861 BBP 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 PRISM and PRISM logo are trademarks of Intersil Corporation. HFA3861 Table of Contents PAGE Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Port (4 Wire) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TX Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RX Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RX I/Q A/D Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGC Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RX_AGC_IN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TX I/Q DAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Header/Packet Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scrambler and Data Encoder Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spread Spectrum Modulator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TX Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clear Channel Assessment (CCA) and Energy Detect (ED) Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGC Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Demodulator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acquisition Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PN Correlators Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Demodulation and Tracking Description (DBPSK and DQPSK Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Decoder and Descrambler Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Demodulation in the CCK Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Demodulator Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overall Eb/N0 Versus BER Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Offset Tracking Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Carrier Offset Frequency Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A Default Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thin Plastic Quad Flatpack Packages (TQFP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 3 4 5 6 7 7 8 8 8 9 9 9 9 10 12 12 12 13 13 14 14 15 16 17 17 19 19 19 19 20 20 21 23 33 33 35 2 Typical Application Diagram RF DAC RF ADC IF DAC HFA3683 RF/IF CONV REFOUT PLL RF LO HFA3963 RFPA REF IN REF IN HFA3783 QUAD IF TX DAC TX ADC REF IN PLL I/O LO IF LO I DAC Q DAC I ADC Q ADC 1 1 7 AGC CTL RADIO DATA INTERFACE WEP ENGINE HFA3841 MAC I/O 6 6 MOD RADIO CONTROL PORTS 7 6 TX ALC HFA3861 BBP GP SERIAL PORTS MEMORY ACCESS ARBITER HOSTPC INTERFACE 3 44MHz MCLK DIFFERENTIAL SIGNALS 6 6 DEMOD CPU 16-BIT PIPELINED CONTROL PROCESSOR HOST INTERFACE LOGIC HFA3861 EXTERNAL MEMORY TYPICAL TRANSCEIVER APPLICATION CIRCUIT USING THE HFA3861 For additional information on the PRISM® chip set, call (407) 724-7800 to access Intersil’ AnswerFAX system. When prompted, key in the four-digit document number (File #) of the data sheets you wish to receive. The four-digit file numbers are shown in the Typical Application Diagram, and correspond to the appropriate circuit. HFA3861 Pin Descriptions NAME VDDA (Analog) VDDD (Digital) GNDa (Analog) PIN 12, 17, 22, 31 2, 8, 37, 57 9, 15, 20, 25, 28, TYPE I/O Power Power Ground Ground I I I I O DESCRIPTION DC power supply 2.7V - 3.6V (Not Hard wired Together On Chip). DC power supply 2.7 - 3.6V DC power supply 2.7 - 3.6V, ground (Not Hard wired Together On Chip). DC power supply 2.7 - 3.6V, ground. Voltage reference for A/D’s and D/A’s Current reference for internal ADC and DAC devices. Requires a 12kΩ resistor to ground. Analog input to the internal 6-bit A/D of the In-phase received data. Balanced differential 10+/11Analog input to the internal 6-bit A/D of the Quadrature received data. Balanced differential 13+/14The antenna select signal changes state as the receiver switches from antenna to antenna during the acquisition process in the antenna diversity mode. This is a complement for ANTSEL (pin 40) for differential drive of antenna switches. The antenna select signal changes state as the receiver switches from antenna to antenna during the acquisition process in the antenna diversity mode. This is a complement for ANTSEL (pin 39) for differential drive of antenna switches. Analog input to the receive power A/D converter for AGC control. Analog drive to the IF AGC control. Drive to the RF AGC stage attenuator. CMOS digital. Input to the transmit power A/D converter for transmit AGC control. Analog drive to the transmit IF power control. When active, the transmitter is configured to be operational, otherwise the transmitter is in standby mode. TX_PE is an input from the external Media Access Controller (MAC) or network processor to the HFA3861. The rising edge of TX_PE will start the internal transmit state machine and the falling edge will initiate shut down of the state machine. TX_PE envelopes the transmit data except for the last bit. The transmitter will continue to run for 4µs after TX_PE goes inactive to allow the PA to shut down gracefully. TXD is an input, used to transfer MAC Payload Data Unit (MPDU) data from the MAC or network processor to the HFA3861. The data is received serially with the LSB first. The data is clocked in the HFA3861 at the rising edge of TXCLK. TXCLK is a clock output used to receive the data on the TXD from the MAC or network processor to the HFA3861, synchronously. Transmit data on the TXD bus is clocked into the HFA3861 on the rising edge. The clocking edge is also programmable to be on either phase of the clock. The rate of the clock will be dependent upon the data rate that is programmed in the signalling field of the header. TX_RDY is an output to the external network processor indicating that Preamble and Header information has been generated and that the HFA3861 is ready to receive the data packet from the network processor over the TXD serial bus. Clear Channel Assessment (CCA) is an output used to signal that the channel is clear to transmit. The CCA may be configured to one of four possible algorithms. The CCA algorithm and its features are described elsewhere in the data sheet. Logic 0 = Channel is clear to transmit. Logic 1 = Channel is NOT clear to transmit (busy). This polarity is programmable and can be inverted. RXD is an output to the external network processor transferring demodulated Header information and data in a serial format. The data is sent serially with the LSB first. The data is frame aligned with MD_RDY. RXCLK is the bit clock output. This clock is used to transfer Header information and payload data through the RXD serial bus to the network processor. This clock reflects the bit rate in use. RXCLK is held to a logic “0” state during the CRC16 reception. RXCLK becomes active after the SFD has been detected. Data should be sampled on the rising edge. This polarity is programmable and can be inverted. GNDd (Digital) 1, 7, 36, 43, 56 VREF IREF RXI, +/RXQ, +/ANTSEL 16 21 10/11 13/14 39 ANTSEL 40 O RX_IF_DET RX_IF_AGC RX_RF_AGC TX_AGC_IN TX_IF_AGC TX_PE 19 34 38 18 35 62 I O O I O I TXD 58 I TXCLK 55 O TX_RDY 59 O CCA 60 O RXD 53 O RXCLK 52 O 4 HFA3861 Pin Descriptions NAME MD_RDY PIN 54 (Continued) TYPE I/O O DESCRIPTION MD_RDY is an output signal to the network processor, indicating header data and a data packet are ready to be transferred to the processor. MD_RDY is an active high signal that signals the start of data transfer over the RXD serial bus. MD_RDY goes active when the SFD (Note) is detected and returns to its inactive state when RX_PE goes inactive or an error is detected in the header. When active, the receiver is configured to be operational, otherwise the receiver is in standby mode. This is an active high input signal. In standby, RX_PE inactive, all RX A/D converters are disabled. SD is a serial bidirectional data bus which is used to transfer address and data to/from the internal registers. The bit ordering of an 8-bit word is MSB first. The first 8 bits during transfers indicate the register address immediately followed by 8 more bits representing the data that needs to be written or read at that register. In the 4 wire interface mode, this pin is tristated unless the R/W pin is high. SCLK is the clock for the SD serial bus. The data on SD is clocked at the rising edge. SCLK is an input clock and it is asynchronous to the internal master clock (MCLK). The maximum rate of this clock is 11MHz or one half the master clock frequency, whichever is lower. Serial Data Input in 3 wire mode described in Tech Brief TBD. This pin is not used in the 4 wire interface described in this data sheet. It should not be left floating. R/W is an input to the HFA3861 used to change the direction of the SD bus when reading or writing data on the SD bus. R/W must be set up prior to the rising edge of SCLK. A high level indicates read while a low level is a write. CS is a Chip select for the device to activate the serial control port. The CS doesn’t impact any of the other interface ports and signals, i.e., the TX or RX ports and interface signals. This is an active low signal. When inactive SD, SCLK, and R/W become “don’t care” signals. This is a data port that can be programmed to bring out internal signals or data for monitoring. These bits are primarily reserved by the manufacturer for testing. A further description of the test port is given in the appropriate section of this data sheet. Master reset for device. When active TX and RX functions are disabled. If RESET is kept low the HFA3861 goes into the power standby mode. RESET does not alter any of the configuration register values nor does it preset any of the registers into default values. Device requires programming upon power-up. Master Clock for device. The nominal frequency of this clock is 44MHz. This is used internally to generate all other internal necessary clocks and is divided by 2 or 4 for the transceiver clocks. TX Spread baseband I digital output data. Data is output at the chip rate. Balanced differential 23+/ 24TX Spread baseband Q digital output data. Data is output at the chip rate. Balanced differential 29+/30-. Compensation capacitor Compensation capacitor Compensation Resistor Compensation Resistor RX_PE SD 61 3 I I/O SCLK 4 I SDI R/W 64 5 I I CS 6 I TEST 7:0 51, 50, 49, 48, 47, 46, 45, 44 63 I/O RESET I MCLK TXI+/TXQ+/CompCap CompCap2 CompRes1 CompRes2 42 23/24 29/30 33 26 32 27 I O O I I I I NOTE: See CR10. External Interfaces There are three primary digital interface ports for the HFA3861 that are used for configuration and during normal operation of the device as shown in Figure 1. These ports are: • The Control Port, which is used to configure, write and/or read the status of the internal HFA3861 registers. • The TX Port, which is used to accept the data that needs to be transmitted from the network processor. • The RX Port, which is used to output the received demodulated data to the network processor. In addition to these primary digital interfaces the device includes a byte wide parallel Test Port which can be configured to output various internal signals and/or data. The device can also be set into various power consumption modes by external control. The HFA3861 contains four Analog to Digital (A/D) converters and four Digital to Analog converters. The analog interfaces to the HFA3861 include, the In phase (I) and quadrature (Q) data component inputs/ outputs, and the RF and IF receive automatic gain control and transmit output power control. 5 HFA3861 HFA3861 ANALOG INPUTS A/D REFERENCE POWER DOWN SIGNALS TEST PORT ANT_SEL 8 RXI RXQ AGC VREF IREF TX_PE RX_PE RESET TEST AGC TXI TXQ TXD TXCLK TX_RDY RXD RXC MD_RDY CS SD SCLK R/W SDI ANALOG OUTPUTS TX_PORT RX_PORT CONTROL_PORT FIGURE 1. EXTERNAL INTERFACES Control Port (4 Wire) The serial control port is used to serially write and read data to/from the device. This serial port can operate up to a 11MHz rate or 1/2 the maximum master clock rate of the device, MCLK (whichever is lower). MCLK must be running and RESET must be inactive during programming. This port is used to program and to read all internal registers. The first 8 bits always represent the address followed immediately by the 8 data bits for that register. The LSB of the address is a don’t care, but reserved for future expansion. The serial transfers are accomplished through the serial data pin (SD). SD is a bidirectional serial data bus. Chip Select (CS), and Read/Write (R/W) are also required as handshake signals for this port. The clock used in conjunction with the address and data on SD is SCLK. This clock is provided by the external source and it is an input to the HFA3861. The timing relationships of these signals are illustrated in Figures 2 and 3. R/W is high when data is to be read, and low when it is to be written. CS is an asynchronous reset to the state machine. CS must be active (low) during the entire data transfer cycle. CS selects the serial control port device only. The serial control port operates asynchronously from the TX and RX ports and it can accomplish data transfers independent of the activity at the other digital or analog ports. The HFA3861 has 96 internal registers that can be configured through the control port. These registers are listed in the Configuration and Control Internal Register table. Table 9 lists the configuration register number, a brief name describing the register, the HEX address to access each of the registers and typical values. The type indicates whether the corresponding register is Read only (R) or Read/Write (R/W). Some registers are two bytes wide as indicated on the table (high and low bytes). 7 SCLK FIRST ADDRESS BIT 6 5 4 3 2 1 0 FIRST DATABIT OUT 7 6 5 4 3 2 1 0 SD 7 MSB 6 5 4 3 2 1 7 MSB 6 5 4 3 2 1 0 LSB ADDRESS IN DATA OUT R/W CS NOTES: 1. The HFA3861 always uses the rising edge of SCLK to sample address and data and to generate read data. 2. These figures show the controller using the falling edge of SCLK to generate address and data and to sample read data. FIGURE 2. CONTROL PORT READ TIMING 7 SCLK SD 7 MSB 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 7 MSB 6 5 4 3 2 1 0 LSB ADDRESS IN DATA IN R/W CS FIGURE 3. CONTROL PORT WRITE TIMING 6 HFA3861 TX Port The transmit data port accepts the data that needs to be transmitted serially from an external data source. The data is modulated and transmitted as soon as it is received from the external data source. The serial data is input to the HFA3861 through TXD using the next rising edge of TXCLK to clock it in the HFA3861. TXCLK is an output from the HFA3861. A timing scenario of the transmit signal handshakes and sequence is shown on timing diagram Figure 4. The external processor initiates the transmit sequence by asserting TX_PE. TX_PE envelopes the transmit data packet on TXD. The HFA3861 responds by generating a Preamble and Header. Before the last bit of the Header is sent, the HFA3861 begins generating TXCLK to input the serial data on TXD. TXCLK will run until TX_PE goes back to its inactive state indicating the end of the data packet. The user needs to hold TX_PE high for as many clocks as there bits to transmit. For the higher data rates, this will be in multiples of the number of bits per symbol. The HFA3861 will continue to output modulated signal for 4µs after the last data bit is output, to supply bits to flush the modulation path. TX_PE must be held until the last data bit is output from the MAC/FIFO. The minimum TX_PE inactive pulse required to restart the preamble and header generation is 2.22µs and to reset the modulator is 4.22µs. The HFA3861 internally generates the preamble and header information from information supplied via the control registers. The external source needs to provide only the data portion of the packet and set the control registers. The timing diagram of this process is illustrated on Figure 4. Assertion of TX_PE will initialize the generation of the preamble and header. TX_RDY, which is an output from the HFA3861, is used (if needed) to indicate to the external processor that the preamble has been generated and the device is ready to receive the data packet (MPDU) to be transmitted from the external processor. Signals TX_RDY, TX_PE and TXCLK can be set individually, by programming Configuration Register (CR) 1, as either active high or active low signals. The transmit port is completely independent from the operation of the other interface ports including the RX port, therefore supporting a full duplex mode. RX Port The timing diagram Figure 5 illustrates the relationships between the various signals of the RX port. The receive data port serially outputs the demodulated data from RXD. The data is output as soon as it is demodulated by the HFA3861. RX_PE must be at its active state throughout the receive operation. When RX_PE is inactive the device's receive functions, including acquisition, will be in a stand by mode. TXCLK TX_PE FIRST DATA BIT SAMPLED LAST DATA BIT SAMPLED TXD LSB DATA PACKET MSB DEASSERTED WHEN LAST CHIP OF MPDU CLEARS MOD PATH OF 3861 EXCEPT FOR TX FILTER AND D/A TX_RDY NOTE: Preamble/Header and Data is transmitted LSB first. TXD shown generated from rising edge of TXCLK. FIGURE 4. TX PORT TIMING RXCLK RX_PE HEADER FIELDS PROCESSING PREAMBLE/HEADER DATA MD_RDY RXD LSB DATA PACKET MSB NOTE: MD_RDY active after CRC16. See detailed timing diagrams (Figures 18, 19, 20). FIGURE 5. RX PORT TIMING 7 HFA3861 RXCLK is an output from the HFA3861 and is the clock for the serial demodulated data on RXD. MD_RDY is an output from the HFA3861 and it may be set to go active after the SFD or CRC fields. Note that RXCLK becomes active after the Start Frame Delimiter (SFD) to clock out the Signal, Service, and Length fields, then goes inactive during the header CRC field. RXCLK becomes active again for the data. MD_RDY returns to its inactive state after RX_PE is deactivated by the external controller, or if a header error is detected. A header error is either a failure of the CRC check, or the failure of the received signal field to match one of the 4 programmed signal fields. For either type of header error, the HFA3861 will reset itself after reception of the CRC field. If MD_RDY had been set to go active after CRC, it will remain low. MD_RDY and RXCLK can be configured through CR 1, bits 1 and 0 to be active low, or active high. The receive port is completely independent from the operation of the other interface ports including the TX port, supporting therefore a full duplex mode. The voltages applied to pin 16, VREF and pin 21, IREF set the references for the internal I and Q A/D converters. In addition, For a nominal I/Q input of 250mVP-P, the suggested VREF voltage is 1.2V. AGC Circuit The AGC circuit is designed to optimize A/D performance for the I and Q inputs by maintaining the proper headroom on the 6-bit converters. There are two gain stages being controlled. At RF, the gain control is a 30dB step in gain from turning off the LNA. This RF gain control optimizes the receiver dynamic range when the signal level is high and maintains the noise figure of the receiver when it is needed most. At IF the gain control is linear and covers the bulk of the gain control range of the receiver. The AGC sensing mechanism uses a combination of the I and Q A/D converters and the detected signal level in the IF to determine the gain settings. The A/D outputs are monitored in the HFA3861 for the desired nominal level. When it is reached, by adjusting the receiver gain, the gain control is locked for the remainder of the packet. RX I/Q A/D Interface The PRISM baseband processor chip (HFA3861) includes two 6-bit Analog to Digital converters (A/Ds) that sample the balanced differential analog input from the IF down converter. The I/Q A/D clock, samples at twice the chip rate. The nominal sampling rate is 22MHz. The interface specifications for the I and Q A/Ds are listed in Table 1. The HFA3861 is designed to be DC coupled to the HFA3783. TABLE 1. I, Q, A/D SPECIFICATIONS PARAMETER Full Scale Input Voltage (VP-P) Input Bandwidth (-0.5dB) Input Capacitance (pF) Input Impedance (DC) fS (Sampling Frequency) MIN 0.90 5kΩ TYP 1.00 11MHz 2 22MHz MAX 1.10 - RX_AGC_IN Interface The signal level in the IF stage is monitored to determine when to impose the up to 30dB gain reduction in the RF stage. This maximizes the dynamic range of the receiver by keeping the RF stages out of saturation at high signal levels. When the IF circuits’ sensor output reaches 0.5V, the HFA3861 comparator switches in the 30dB pad and compensates the IF AGC and RSSI measures. RX_RF_AGC RX_IF_DET RX_IF_AGC RX_I± HFA3683 HFA3783 RX_Q± THRESH. DETECT IF DAC I ADC Q ADC 1 1 7 AGC CTL 6 6 DEMOD DATA I/O I/O HFA3861 FIGURE 6. AGC CIRCUIT 8 HFA3861 TX I/Q DAC Interface The transmit section outputs balanced differential analog signals from the transmit DACs to the HFA3783. These are DC coupled and digitally filtered. noise floor values. Optimum receiver operation may not be achieved until these values are reestablished (typically