HI-5043

HI-5042 thru HI-5051 TM Data Sheet April 2000 File Number 3127.4 CMOS Analog Switches This family of CMOS analog switches offers low resistance switching performance for analog voltages up to the supply rails and for signal currents up to 80mA. “ON” resistance is low and stays reasonably constant over the full range of operating signal voltage and current. rON remains exceptionally constant for input voltages between +5V and -5V and currents up to 50mA. Switch impedance also changes very little over temperature, particularly between 0oC and 75oC. rON is nominally 25Ω for HI-5049 and HI-5051 and 50Ω for HI-5042 through HI-5047. All devices provide break-before-make switching and are TTL and CMOS compatible for maximum application versatility. Performance is further enhanced by Dielectric Isolation processing which insures latch-free operation with very low input and output leakage currents (0.8nA at 25oC). This family of switches also features very low power operation (1.5mW at 25oC). There are 7 devices in this switch series which are differentiated by type of switch action and value of rON (see Functional Description Table). The HI-504X and HI-505X series switches can directly replace IH-5040 series devices, and are functionally compatible with the DG180 and DG190 family. Features • Wide Analog Signal Range . . . . . . . . . . . . . . . . . . . ±15V • Low “ON” Resistance . . . . . . . . . . . . . . . . . . . . . . . . . 25Ω • High Current Capability . . . . . . . . . . . . . . . . . . . . . . 80mA • Break-Before-Make Switching - Turn-On Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370ns - Turn-Off Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 280ns • No Latch-Up • Input MOS Gates are Protected from Electrostatic Discharge • DTL, TTL, CMOS, PMOS Compatible Applications • High Frequency Switching • Sample and Hold • Digital Filters • Operational Amplifier Gain Switching Functional Diagram S Ordering Information A N P PART NUMBER HI1-5042-2 HI1-5043-2 HI1-5043-5 HI3-5043-5 HI9P5043-5 HI1-5047-5 HI1-5049-5 HI1-5051-2 HI1-5051-5 HI3-5051-5 HI9P5051-9 TEMP. RANGE (oC) -55 to 125 -55 to 125 0 to 75 0 to 75 0 to 75 0 to 75 0 to 75 -55 to 125 0 to 75 0 to 75 -40 to 85 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld CERDIP 16 Ld CERDIP 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC PKG. NO. F16.3 F16.3 F16.3 E16.3 M16.15 F16.3 F16.3 F16.3 F16.3 E16.3 M16.15 D Functional Description PART NUMBER HI-5042 HI-5043 HI-5047 HI-5049 HI-5051 SPDT Dual SPDT 4PST Dual DPST Dual SPDT TYPE rON 50Ω 50Ω 50Ω 25Ω 25Ω 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 HI-5042 thru HI-5051 Pinouts (SWITCHES SHOWN FOR LOGIC “0” INPUT) Pinouts (SWITCHES SHOWN FOR LOGIC “0” INPUT) Single Control SPDT HI-5042 (50Ω) D1 1 2 D2 3 S2 4 5 6 7 8 16 S1 15 A 14 V13 VR 12 VL 11 V+ 10 9 D2 1 2 D1 3 S1 4 S4 5 D4 6 7 D3 8 Dual Control 4PST HI-5047 (50Ω) 16 S2 15 A 14 V13 VR 12 VL 11 V+ 10 9 S3 DUAL SPDT HI-5043 (50Ω), HI-5051 (25Ω) D1 1 2 D3 3 S3 4 S4 5 D4 6 7 D2 8 16 S1 15 A1 14 V13 VR 12 VL 11 V+ 10 A2 9 S2 D1 1 2 D3 3 S3 4 S4 5 D4 6 7 D2 8 DUAL DPST HI-5049 (25Ω) 16 S1 15 A1 14 V13 VR 12 VL 11 V+ 10 A2 9 S2 NOTE: Unused pins may be internally connected. Ground all unused pins. NOTE: Unused pins may be internally connected. Ground all unused pins. Switch Functions (SWITCHES SHOWN FOR LOGIC “1” INPUT) DUAL SPDT HI-5043 (50Ω) VL 12 1 3 D1 D2 S1 S3 A1 A2 S2 S4 16 4 15 10 9 5 13 VR 14 VV+ 11 1 3 D1 D3 SPDT HI-5042 (50Ω) VL 12 S1 S2 16 4 V+ 11 A 15 8 6 D2 D4 13 VR 14 V- 4PST HI-5047 (50Ω) VL 12 S1 S2 S3 S4 A 4 16 9 5 15 V+ 11 3 1 8 6 D1 D2 D3 D4 S1 S3 A1 A2 S2 S4 13 VR 14 V16 4 15 10 9 5 DUAL DPST HI-5049 (25Ω) VL 12 V+ 11 1 3 D1 D3 S1 S3 A1 8 6 13 VR 14 VA2 S2 S4 16 4 15 10 9 5 DUAL SPDT HI-5051 (25Ω) VL 12 V+ 11 1 3 D1 D3 D2 D4 8 6 13 VR 14 V- D2 D4 2 HI-5042 thru HI-5051 Schematic Diagrams V+ VL 35µA R6 QP4 R3 N13 100µA 25µA 25µA QP1 25µA P15 P14 QN1 P16 QP3 R4 QP5 QP8 R2 QP7 VR QP6 P13 25µA 16µA V+ R5 TO VR’ 25µA QP2 VN16 to VL’ N1 V+ IN P2 VP1 N3 N2 OUT R7 QN2 N14 N15 NOTE: Connect V+ to VL for minimizing power consumption when driving from CMOS circuits. TTL/CMOS REFERENCE CIRCUIT (NOTE) A1 (A2) A1 (A2) SWITCH CELL V+ P3 P5 P4 P6 VR' D2 VL' N6 VP2 N4 N2 N5 N3 VN7 N8 N9 N10 N11 N12 P7 P8 P9 P10 P11 P12 A1 A1 A2 A2 V+ P1 N1 D1 R4 A 200Ω NOTE: All N-Channel bodies to V-, all P-Channel bodies to V+ except as shown. DIGITAL INPUT BUFFER AND LEVEL SHIFTER 3 HI-5042 thru HI-5051 Absolute Maximum Ratings Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V VR to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+, VDigital and Analog Input Voltage . . . . . . . . . . . . (V+) +4V to (V-) -4V Analog Current (S to D) Continuous . . . . . . . . . . . . . . . . . . . . 30mA Analog Current (S to D) Peak . . . . . . . . . . . . . . . . . . . . . . . . . 80mA Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 75 22 SOIC Package . . . . . . . . . . . . . . . . . . . 110 N/A PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A Maximum Junction Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC Maximum Storage Temperature. . . . . . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range HI-50XX-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HI-50XX-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC HI-50XX-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Supplies = +15V, -15V; VR = 0V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.8V, VL = 5V, Unless Otherwise Specified. For Test Conditions, Consult Performance Characteristics, Unused Pins are Grounded TEST CONDITIONS TEMP (oC) -2 MIN TYP MAX MIN -5, -9 TYP MAX UNITS PARAMETER DYNAMIC CHARACTERISTICS Switch ON Time, tON Switch OFF Time, tOFF Charge Injection, Q OFF Isolation Crosstalk Input Switch Capacitance, CS(OFF) Output Switch Capacitance, CD(OFF) Output Switch Capacitance, CD(ON) Digital Input Capacitance, CA Drain To Source Capacitance, CDS(OFF) DIGITAL INPUT CHARACTERISTICS Input Low Threshold, VAL Input High Threshold, VAH Input Leakage Current (High or Low), IA ANALOG SWITCH CHARACTERISTICS Analog Signal Range ON Resistance, rON HI-5042 to HI-5047 (Note 5) (Note 5) (Note 3) (Note 4) (Note 4) 25 25 25 25 25 25 25 25 25 25 75 80 - 370 280 5 80 88 11 11 22 5 0.5 500 500 20 - - 370 280 5 80 88 11 11 22 5 0.5 500 500 - ns ns mV dB dB pF pF pF pF pF Full Full Full 2.4 - 0.01 0.8 1.0 2.4 - 0.01 0.8 1.0 V V µA Full -15 - +15 -15 - +15 V Ω Ω Ω Ω Ω Ω nA nA (Note 2) 25 Full - 50 25 - 75 150 45 50 - 50 25 - 75 150 45 50 HI-5049, HI-5051 (Note 2) 25 Full Channel-to-Channel Match, ∆rON HI-5042 to HI-5047 HI-5049, HI-5051 OFF Input or Output Leakage Current, IS(OFF) = ID(OFF) 25 25 25 Full 2 1 0.8 100 10 5 2 200 2 1 0.8 100 10 5 2 200 4 HI-5042 thru HI-5051 Electrical Specifications Supplies = +15V, -15V; VR = 0V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.8V, VL = 5V, Unless Otherwise Specified. For Test Conditions, Consult Performance Characteristics, Unused Pins are Grounded (Continued) TEST CONDITIONS TEMP (oC) 25 Full POWER REQUIREMENTS Quiescent Power Dissipation, PD I+, I-, IL , IR I+, +15V Quiescent Current I-, -15V Quiescent Current IL , +5V Quiescent Current IR , Ground Quiescent Current NOTES: 2. VOUT = ±10V, IOUT = 3. VIN = 0V, CL = 10nF. 4. RL = 100Ω , f = 100kHz, VIN = 2.0VP-P , CL = 5pF. 5. VAL = 0V, VAH = 5V. 1mA. (Note 5) (Note 5) (Note 5) (Note 5) 25 25 Full Full Full Full 1.5 0.2 0.3 0.3 0.3 0.3 1.5 0.3 0.5 0.5 0.5 0.5 mW mA mA mA mA mA -2 MIN TYP 0.01 2 MAX 2 200 MIN -5, -9 TYP 0.01 2 MAX 2 200 UNITS nA nA PARAMETER ON Leakage Current, ID(ON) Test Circuits and Waveforms TA = 25oC, V+ = +15V, V- = -15V, VL = +5V, VR = 0V, VAH = 3V and VAL = 0.8V Unless Otherwise Specified 1mA V2 1mA IN ±VIN V2 OUT rON = FIGURE 1A. TEST CIRCUIT 80 NORMALIZED ON RESISTANCE (REFERRED TO 25oC) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -10 0 5 -5 ANALOG SIGNAL LEVEL (V) 10 15 -50 -25 0 25 50 75 100 125 TEMPERATURE (oC) VIN = 0V ON RESISTANCE (Ω) 60 V+ = +12V V- = -12V 40 V+ = +10V V- = -10V 20 V+ = +15V V- = -15V 0 -15 FIGURE 1B. ON RESISTANCE vs ANALOG SIGNAL LEVEL FIGURE 1C. NORMALIZED ON RESISTANCE vs TEMPERATURE FIGURE 1. ON RESISTANCE 5 HI-5042 thru HI-5051 Test Circuits and Waveforms 100nA TA = 25oC, V+ = +15V, V- = -15V, VL = +5V, VR = 0V, VAH = 3V and VAL = 0.8V Unless Otherwise Specified (Continued) OFF LEAKAGE CURRENT IS(OFF) ID(OFF) IN OUT A ± 10V LEAKAGE CURRENT 10nA IS(OFF) = ID(OFF) A ±10V 1nA ON LEAKAGE CURRENT IN ID(ON) OUT 100pA A 10pA 25 ID(ON) ±10V 50 75 TEMPERATURE (oC) 100 125 FIGURE 2A. LEAKAGE CURRENTS vs TEMPERATURE FIGURE 2. LEAKAGE CURRENTS 1.4 NORMALIZED ON RESISTANCE (REFERRED TO 1mA) FIGURE 2B. TEST CIRCUITS 1.3 1.2 IN ±VIN OUT I 1.1 V IN r ON = --------I 1.0 0 20 40 ANALOG CURRENT (mA) 60 80 FIGURE 3A. NORMALIZED ON RESISTANCE vs ANALOG CURRENT FIGURE 3. NORMALIZED ON RESISTANCE FIGURE 3B. TEST CIRCUIT -200 OFF ISOLATION (dB) IN -160 RL = 100Ω VIN 2VP-P 50Ω OUT VOUT RL -120 -80 RL = 10kΩ -40  V OUT OFF ISOLATION = 20 Log  ---------------  V IN  1 10 100 1K 10K 100K 1M FREQUENCY (Hz) FIGURE 4A. OFF ISOLATION vs FREQUENCY FIGURE 4C. OFF ISOLATION FIGURE 4B. TEST CIRCUIT 6 HI-5042 thru HI-5051 Test Circuits and Waveforms TA = 25oC, V+ = +15V, V- = -15V, VL = +5V, VR = 0V, VAH = 3V and VAL = 0.8V Unless Otherwise Specified (Continued) 200 CROSSTALK (dB) SWITCHED CHANNEL VIN 2VP-P 50Ω 160 120 VOUT RL RL 80 40 0 1 10 100 1K 10K 100K 1M FREQUENCY (Hz)  V IN  CROSSTALK = 20 Log  ---------------  V OUT FIGURE 5A. CROSSTALK vs FREQUENCY FIGURE 5. CROSSTALK FIGURE 5B. TEST CIRCUIT 200 POWER CONSUMPTION (mW) 160 +10V -10V A VL VR V+ IL I+ VI- 120 TOGGLE AT 50% DUTY 80 40 +5V 0 1K 10K 100K 1M TOGGLE FREQUENCY (50% DUTY CYCLE) (Hz) +15V -15V FIGURE 6A. POWER CONSUMPTION vs FREQUENCY FIGURE 6. POWER CONSUMPTION FIGURE 6B. TEST CIRCUIT VAH VA IN1 +10V OUT 2 IN2 1K VA tOFF tON 1K tON 90% tOFF 90% 90% OUT 1 OUT 2 OUT 1 90% FIGURE 7A. TEST CIRCUIT FIGURE 7B. MEASUREMENT POINTS 7 HI-5042 thru HI-5051 Test Circuits and Waveforms TA = 25oC, V+ = +15V, V- = -15V, VL = +5V, VR = 0V, VAH = 3V and VAL = 0.8V Unless Otherwise Specified (Continued) VA VA OUTPUT OUTPUT VA = 0V to 5V Vertical: 2V/Div. Horizontal: 200ns/Div. FIGURE 7C. WAVEFORMS WITH TTL COMPATIBLE LOGIC INPUT VA = 0V to 10V Vertical: 5V/Div. Horizontal: 200ns/Div. FIGURE 7D. WAVEFORMS WITH CMOS COMPATIBLE LOGIC INPUT 720 660 600 720 660 600 INPUT) INPUT) (NEED tON tOFF 540 480 420 360 300 240 180 120 60 2.4 3.0 3.6 DIGITAL “HIGH” (V) 4.2 4.8 540 480 420 360 300 240 180 120 60 0 0.5 1.0 1.5 DIGITAL “LOW” (V) tOFF tON FIGURE 7E. SWITCHING TIMES vs POSITIVE DIGITAL VOLTAGE (NEED FIGURE 7F. SWITCHING TIMES vs NEGATIVE DIGITAL VOLTAGE FIGURE 7. SWITCH tON AND tOFF 8 HI-5042 thru HI-5051 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E16.3 (JEDEC MS-001-BB ISSUE D) 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280 A E A2 L A C L -AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A1 A2 -C- B B1 C D D1 E eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). E1 e eA eB L N 0.100 BSC 0.300 BSC 0.115 16 0.430 0.150 2.54 BSC 7.62 BSC 2.93 16 10.92 3.81 9 HI-5042 thru HI-5051 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 1.35 0.10 0.33 0.19 9.80 3.80 MAX 1.75 0.25 0.51 0.25 10.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0532 0.0040 0.013 0.0075 0.3859 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.3937 0.1574 A1 B C D α A1 0.10(0.004) C E e H h L N e B 0.25(0.010) M C AM BS 0.050 BSC 0.2284 0.0099 0.016 16 0o 8o 0.2440 0.0196 0.050 1.27 BSC 5.80 0.25 0.40 16 0o 6.20 0.50 1.27 NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 10 HI-5042 thru HI-5051 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A - B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.840 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 21.34 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94 α eA c1 D E e eA eA/2 L Q S1 e DS eA/2 c 0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 16 0.200 0.060 105o 0.015 0.030 0.010 0.0015 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 16 5.08 1.52 105o 0.38 0.76 0.25 0.038 aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. α aaa bbb ccc M N All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369 11