HI-506_07

® HI-506, HI-507, HI-508, HI-509 Data Sheet October 30, 2007 FN3142.8 Single 16 and 8/Differential 8-Channel and 4-Channel CMOS Analog Multiplexers The HI-506/HI-507 and HI-508/HI-509 monolithic CMOS multiplexers each include an array of sixteen and eight analog switches respectively, a digital decoder circuit for channel selection, voltage reference for logic thresholds, and an enable input for device selection when several multiplexers are present. The Dielectric Isolation (DI) process used in fabrication of these devices eliminates the problem of latchup. DI also offers much lower substrate leakage and parasitic capacitance than conventional junction isolated CMOS (see Application Note AN520). The switching threshold for each digital input is established by an internal +5V reference, providing a guaranteed minimum 2.4V for logic “1” and maximum 0.8V for logic “0”. This allows direct interface without pullup resistors to signals from most logic families: CMOS, TTL, DTL and some PMOS. For protection against transient overvoltage, the digital inputs include a series 200Ω resistor and diode clamp to each supply. The HI-506 is a single 16-channel, the HI-507 is an 8-channel differential, the HI-508 is a single 8-channel and the HI-509 is a 4-channel differential multiplexer. If input overvoltages are present, the HI-546/HI-547/HI-548/ HI-549 multiplexers are recommended. Features • Pb-Free Available (RoHS Compliant) (See Ordering Info) • Low ON Resistance . . . . . . . . . . . . . . . . . . . . . . . . 180Ω • Wide Analog Signal Range . . . . . . . . . . . . . . . . . . . . . ±15V • TTL/CMOS Compatible • Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns • Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . . 44V • Break-Before-Make Switching • No Latch-Up • Replaces DG506A/DG506AA and DG507A/DG507AA • Replaces DG508A/DG508AA and DG509A/DG509AA • Pb-Free Available (RoHS Compliant) Applications • Data Acquisition Systems • Precision Instrumentation • Demultiplexing • Selector Switch 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003, 2005, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HI-506, HI-507, HI-508, HI-509 Ordering Information PART NUMBER HI1-0506-2 HI1-0506-5 HI4P0506-5 HI4P0506-5Z (Note 1) HI9P0506-5 HI9P0506-9 HI9P0506-9Z (Note 1) HI1-0507-2 HI3-0507-5 HI3-0507-5Z HI1-0508-2 HI1-0508-5 HI3-0508-5 HI3-0508-5Z (Note 1) HI9P0508-5 HI9P0508-5Z (Notes 1, 2) HI9P0508-9 HI9P0508-9Z (Note 1) HI1-0509-2 HI1-0509-4 HI1-0509-5 HI3-0509-5 HI4P0509-5 HI4P0509-5Z (Notes 1, 2) HI9P0509-5 HI9P0509-5Z (Notes 1, 2) NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Add “96” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 3. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. PART MARKING HI1-506-2 HI1-506-5 HI4P 506-5 HI4P 506-5Z HI9P506-5 HI9P506-9 HI9P506-9Z HI1-507-2 HI3-507-5 HI3-507-5Z HI1-508-2 HI1-508 HI3-508-5 HI3-508-5Z HI9P508-5 HI9P508-5Z HI9P508-9 HI9P508-9Z HI1-509-2 HI1-509-4 HI1-509-5 HI3-509-5 HI4P 509-5 HI4P 509-5Z HI9P 509-5 HI9P 509-5Z TEMP. RANGE (°C) -55 to +125 0 to +75 0 to +75 0 to +75 0 to +75 -40 to +85 -40 to +85 -55 to +125 0 to +75 0 to +75 -55 to 125 0 to +75 0 to +75 0 to +75 0 to +75 0 to +75 -40 to +85 -40 to +85 -55 to +125 -25 to +85 0 to +75 0 to +75 0 to +75 0 to +75 0 to +75 0 to +75 PACKAGE 28 Ld CERDIP 28 Ld CERDIP 28 Ld PLCC 28 Ld PLCC (Pb-free) 28 Ld SOIC 28 Ld SOIC 28 Ld SOIC (Pb-free) 28 Ld CERDIP 28 Ld PDIP PKG. DWG. # F28.6 F28.6 N28.45 N28.45 M28.3 M28.3 M28.3 F28.6 E28.6 28 Ld PDIP (Note 3) (Pb-free) E28.6 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP F16.3 F16.3 E16.3 16 Ld PDIP (Note 3) (Pb-free) E16.3 16 Ld SOIC 16 Ld SOIC (Pb-free) 16 Ld SOIC 16 Ld SOIC (Pb-free) 16 Ld CERDIP 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 20 Ld PLCC 20 Ld PLCC (Pb-free) 16 Ld SOIC 16 Ld SOIC (Pb-free) M16.15 M16.15 M16.15 M16.15 F16.3 F16.3 F16.3 E16.3 N20.35 N20.35 M16.15 M16.15 2 FN3142.8 October 30, 2007 HI-506, HI-507, HI-508, HI-509 Pinouts HI-506 (CERDIP, SOIC) TOP VIEW HI-506 (PLCC) TOP VIEW +VSUPPLY -VSUPPLY 27 OUT NC 2 NC 3 IN 16 4 IN 15 5 IN 14 6 IN 13 7 IN 12 8 IN 11 9 IN 10 10 IN 9 11 GND 12 NC 13 ADDRESS A3 14 27 -VSUPPLY 26 IN 8 25 IN 7 24 IN 6 23 IN 5 22 IN 4 21 IN 3 20 IN 2 19 IN 1 18 ENABLE 17 ADDRESS A0 16 ADDRESS A1 15 ADDRESS A2 IN 9 11 IN 15 IN 14 IN 13 IN 12 IN 11 IN 10 5 6 7 8 9 10 4 3 2 1 28 IN 8 26 25 24 23 22 21 20 19 IN 7 IN 6 IN 5 IN 4 IN 3 IN 2 IN 1 18 ENABLE FN3142.8 October 30, 2007 NC 13 NC 12 GND 14 A3 NC +VSUPPLY 1 28 OUT IN 16 15 A2 16 A1 17 A0 16 A1 15 A2 HI-507 (PDIP, CERDIP) TOP VIEW +VSUPPLY 1 OUT B 2 NC 3 IN 8B 4 IN 7B 5 IN 6B 6 IN 5B 7 IN 4B 8 IN 3B 9 IN 2B 10 IN 1B 11 GND 12 NC 13 NC 14 28 OUT A 27 -VSUPPLY 26 IN 8A 25 IN 7A 24 IN 6A 23 IN 5A 22 IN 4A 21 IN 3A 20 IN 2A 19 IN 1A 18 ENABLE 17 ADDRESS A0 16 ADDRESS A1 15 ADDRESS A2 HI-508 (PDIP, CERDIP, SOIC) TOP VIEW A0 1 ENABLE 2 -VSUPPLY 3 IN 1 4 IN 2 5 IN 3 6 IN 4 7 OUT 8 14 GND 13 +VSUPPLY 12 IN 5 11 IN 6 10 IN 7 9 IN 8 3 HI-506, HI-507, HI-508, HI-509 Pinouts (Continued) HI-509 (PDIP, CERDIP, SOIC) TOP VIEW A0 1 ENABLE 2 -VSUPPLY 3 IN 1A 4 IN 2A 5 IN 3A 6 IN 4A 7 OUT A 8 16 A1 15 GND 14 +VSUPPLY 13 IN 1B 12 IN 2B 11 IN 3B 10 IN 4B 9 OUT B NC IN 2A IN 3A 6 7 8 9 IN 4A 10 OUT A 11 NC 12 OUT B 13 IN 4B -VSUPPLY IN 1A 4 5 ENABLE HI-509 (PLCC) TOP VIEW 3 2 1 20 19 18 +VSUPPLY 17 IN 1B 16 NC 15 IN 2B 14 IN 3B 4 GND NC A0 A1 FN3142.8 October 30, 2007 HI-506, HI-507, HI-508, HI-509 Truth Tables HI-506 A3 X L L L L L L L L H H H H H H H H A2 X L L L L H H H H L L L L H H H H A1 X L L H H L L H H L L H H L L H H A0 X L H L H L H L H L H L H L H L H EN L H H H H H H H H H H H H H H H H “ON” CHANNEL None 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A1 X L L H H A0 X L H L H EN L H H H H HI-509 “ON” CHANNEL PAIR None 1 2 3 4 A2 X L L L L H H H H A1 X L L H H L L H H A0 X L H L H L H L H HI-508 EN L H H H H H H H H “ON” CHANNEL None 1 2 3 4 5 6 7 8 HI-507 A2 X L L L L H H H H A1 X L L H H L L H H A0 X L H L H L H L H EN L H H H H H H H H “ON” CHANNEL None 1 2 3 4 5 6 7 8 5 FN3142.8 October 30, 2007 HI-506, HI-507, HI-508, HI-509 Functional Diagrams HI-506 HI-507 IN 1 IN 2 DECODER/ DRIVER IN 16 OUT IN 1A OUT A IN 8A IN 1B OUT B DECODER/ DRIVER IN 8B 5V REF LEVEL SHIFT 5V REF LEVEL SHIFT † DIGITAL INPUT PROTECTION †† †† A0 A1 A2 A3 † EN † DIGITAL INPUT PROTECTION † A0 † A1 † A2 † EN HI-508 HI-509 IN 1 IN 2 DECODER/ DRIVER IN 8 OUT IN 1A OUT A IN 4A IN 1B OUT B DECODER/ DRIVER IN 4B 5V REF LEVEL SHIFT 5V REF LEVEL SHIFT † DIGITAL INPUT PROTECTION † A0 † A1 † A2 † EN † DIGITAL INPUT PROTECTION † A0 † A1 † EN 6 FN3142.8 October 30, 2007 HI-506, HI-507, HI-508, HI-509 Schematic Diagrams ADDRESS DECODER V+ P P P P P P P N A0 OR A0 A1 OR A1 A2 O R A2 A3 O R A3 N N TO P-CHANNEL DEVICE OF THE SWITCH N N TO N-CHANNEL DEVICE OF THE SWITCH N N ENABLE DELETE A3 OR A3 INPUT FOR HI-507, HI-508, HI-509 DELETE A2 OR A2 INPUT FOR HI-509 V- ADDRESS INPUT BUFFER LEVEL SHIFTER P3 P1 V+ D1 N1 P4 V+ P5 A P6 P7 P8 P9 P10 D2 200Ω VAIN VL VR P2 N4 N2 N3 VN5 N6 N7 N8 N9 N10 A ALL N-CHANNEL BODIES TO VALL P-CHANNEL BODIES TO V+ UNLESS OTHERWISE INDICATED TTL REFERENCE CIRCUIT V+ P15 Q1P Q2P Q3P Q4P FROM DECODE MULTIPLEX SWITCH N18 Q5N V+ Q6N R2 16.8k Q11P Q10N Q9P N13 N14 N15 Q12N FROM DECODE VGND D3 R3 6.8k P16 VR P18 Q7P VQ8N IN P17 N19 N17 OUT VL N12 7 FN3142.8 October 30, 2007 HI-506, HI-507, HI-508, HI-509 Absolute Maximum Ratings V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44V V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+22V V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V Digital Input Voltage (VEN , VA) . . . . . (V-) -4V to (V+) +4V or 20mA, Whichever Occurs First Analog Signal (VIN, VOUT, Note 5) . . . . . . . . . . (V-) -2V to (V+) +2V Continuous Current, In or Out . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Peak Current, In or Out (Pulsed 1ms, 10% Duty Cycle Max) . 40mA Thermal Information Thermal Resistance (Typical, Note 4) θJA (°C/W) θJC (°C/W) 16 Ld CERDIP Package. . . . . . . . . . . . 85 32 16 Ld SOIC Package . . . . . . . . . . . . . . 115 N/A 16 Ld PDIP Package . . . . . . . . . . . . . . 100 N/A 20 Ld PLCC Package. . . . . . . . . . . . . . 80 N/A 28 Ld CERDIP Package. . . . . . . . . . . . 55 18 28 Ld PDIP Package . . . . . . . . . . . . . . 60 N/A 28 Ld SOIC Package . . . . . . . . . . . . . . 70 N/A 28 Ld PLCC Package. . . . . . . . . . . . . . 70 N/A Maximum Junction Temperature Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Ranges HI-50X-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C HI-50X-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-25°C to +85°C HI-50X-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +75°C HI-50X-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Typical Minimum Supply Voltage . . . . . . . . . . . . ± 10V or Single 20V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 4. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. Signals on IN or OUT exceeding V+ or V- are clamped by internal diodes. Limit resulting current to maximum current ratings. If an overvoltage condition is anticipated (analog input exceeds either power supply voltage), the Intersil HI-546/HI-547/HI-548/HI-549 multiplexers are recommended. Electrical Specifications Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V; VAL (Logic Level Low) = 0.8V, Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section -2 -4, -5, -9 MAX 500 1000 500 1000 500 1000 0.8 MIN (Note 11) 25 2.4 TYP 250 80 250 250 1.2 2.4 360 600 68 10 52 30 17 12 6 0.08 MAX 1000 1000 1000 0.8 UNITS ns ns ns ns ns ns ns μs μs ns ns dB pF pF pF pF pF pF pF V V PARAMETER DYNAMIC CHARACTERISTICS Access Time, tA Break-Before-Make Delay, tOPEN Enable Delay (ON), tON(EN) Enable Delay (OFF), tOFF(EN) Settling Time, tS (HI-506 and HI-507) Settling Time, tS (HI-508 and HI-509) Off Isolation Channel Input Capacitance, CS(OFF) Channel Output Capacitance, CD(OFF) HI-506 HI-507 HI-508 HI-509 Digital Input Capacitance, CA Input to Output Capacitance, CDS(OFF) DIGITAL INPUT CHARACTERISTICS Input Low Threshold, VAL Input High Threshold, VAH TEST CONDITIONS TEMP (°C) 25 Full 25 25 Full 25 Full MIN (Note 11) 25 2.4 TYP 250 80 250 250 1.2 2.4 360 600 68 10 52 30 17 12 6 0.08 - To 0.1% To 0.01% To 0.1% To 0.01% Note 9 25 25 25 25 25 25 25 25 25 25 25 25 Full Full 8 FN3142.8 October 30, 2007 HI-506, HI-507, HI-508, HI-509 Electrical Specifications Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V; VAL (Logic Level Low) = 0.8V, Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section (Continued) -2 PARAMETER Input Leakage Current (High or Low), IA ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, VIN On Resistance, rON ΔrON , (Any Two Channels) Off Input Leakage Current, IS(OFF) Off Output Leakage Current, ID(OFF) HI-506 HI-507 HI-508 HI-509 On Channel Leakage Current, ID(ON) HI-506 HI-507 HI-508 HI-509 Differential Off Output Leakage Current, IDIFF (HI-507, HI-509 Only) POWER SUPPLY CHARACTERISTICS Current, I+ HI-506/HI-507 HI-508/HI-509 Current, IHI-506/HI-507 HI-508/HI-509 Power Dissipation, PD HI-506/HI-507 HI-508/HI-509 NOTES: 6. VOUT = ±10V, IOUT = +1mA. 7. 10nA is the practical lower limit for high speed measurement in the production test environment. 8. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at +25°C. 9. VEN = 0.8V, RL = 1k, CL = 15pF, VS = 7VRMS , f = 100kHz. 10. VEN , VA = 0V or 2.4V. 11. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested. Note 10 Note 10 Note 10 Note 10 Full Full Full Full Full Full 1.5 1.5 0.4 0.4 3.0 2.4 1.0 1.0 60 51 1.5 1.5 0.4 0.4 3.0 2.4 1.0 1.0 60 51 mA mA mA mA mW mW Note 7 Note 7 Note 7 Note 6 Full 25 25 25 Full 25 Full Full Full Full 25 Full Full Full Full Full -15 180 5 0.03 0.3 0.3 +15 300 50 300 200 200 100 300 200 200 100 50 -15 180 5 0.03 0.3 0.3 +15 400 50 300 200 200 100 300 200 200 100 50 V Ω % nA nA nA nA nA nA nA nA nA nA nA nA nA TEST CONDITIONS Note 8 TEMP (°C) Full MIN (Note 11) TYP MAX 1.0 MIN (Note 11) -4, -5, -9 TYP MAX 1.0 UNITS μA 9 FN3142.8 October 30, 2007 HI-506, HI-507, HI-508, HI-509 Test Circuits and Waveforms TA = +25°C, VSUPPLY = ±15V, VAH = 2.4V, VAL = 0.8V, Unless Otherwise Specified 1mA V2 IN OUT V2 1mA VIN rON = FIGURE 1A. TEST CIRCUIT 400 NORMALIZED RESISTANCE (REFERRED TO VALUE AT ±15V) 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 10 -55°C TO +125°C VIN = 0V ON RESISTANCE (Ω) 300 +125°C 200 +25°C 100 -55°C 0 -15 -10 -5 0 5 ANALOG INPUT (V) 10 15 11 12 13 14 15 SUPPLY VOLTAGE (±V) FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE FIGURE 1C. NORMALIZED ON RESISTANCE vs SUPPLY VOLTAGE FIGURE 1. ON RESISTANCE 100nA 10nA LEAKAGE CURRENT OFF OUTPUT LEAKAGE CURRENT ID(OFF) ID(ON) EN OUT 0.8V 1nA A ID(OFF) ±10V 100pA OFF INPUT LEAKAGE CURRENT IS(OFF) +10V 10pA 25 50 75 100 125 TEMPERATURE (°C) FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE FIGURE 2B. ID(OFF) TEST CIRCUIT (NOTE 12) 10 FN3142.8 October 30, 2007 HI-506, HI-507, HI-508, HI-509 Test Circuits and Waveforms TA = +25°C, VSUPPLY = ±15V, VAH = 2.4V, VAL = 0.8V, Unless Otherwise Specified (Continued) OUT A IS(OFF) EN +10V 0.8V A0 A1 EN OUT A ID(ON) ±10V +10V ±10V 2.4V FIGURE 2C. IS(OFF) TEST CIRCUIT (NOTE 12) NOTE: FIGURE 2D. ID(ON) TEST CIRCUIT (NOTE 12) FIGURE 2. LEAKAGE CURRENTS 12. Two measurements per channel: ±10V and +10V. (Two measurements per device for ID(OFF) ±10V and +10V) 70 60 SWITCH CURRENT (mA) 50 +25°C 40 30 20 10 0 +125°C ±VIN A -55°C 0 2 4 6 8 10 12 VOLTAGE ACROSS SWITCH (±V) 14 16 FIGURE 3A. ON CHANNEL CURRENT vs VOLTAGE FIGURE 3. ON CHANNEL CURRENT FIGURE 3B. TEST CIRCUIT +15V/+10V 8 VSUPPLY = ±15V SUPPLY CURRENT (mA) 6 A3 A2 4 VA 50Ω A1 A0 2 VSUPPLY = ±10V 0 1k 10k 100k TOGGLE FREQUENCY (Hz) 1M 10M 3.5V VA EN GND V+ IN 1 HI-506 † IN 2 THRU IN 7/15 IN 8/16 OUT V±10V/±5V A +ISUPPLY +10V/+5V 10 MΩ 14 pF HIGH = 3.5V LOW = 0V 50% DUTY CYCLE † Similar connection for HI-507/ HI-508/HI-509 A -ISUPPLY -15V/-10V FIGURE 4A. SUPPLY CURRENT vs TOGGLE FREQUENCY FIGURE 4. DYNAMIC SUPPLY CURRENT FIGURE 4B. TEST CIRCUIT 11 FN3142.8 October 30, 2007 HI-506, HI-507, HI-508, HI-509 Test Circuits and Waveforms TA = +25°C, VSUPPLY = ±15V, VAH = 2.4V, VAL = 0.8V, Unless Otherwise Specified (Continued) +15V 600 A3 ACCESS TIME (ns) A2 400 VA 50Ω A1 A0 3.5V EN GND V+ IN 1 IN 2 THRU IN 7/15 HI-506 † IN 16 OUT V+10V ±10V 200 10 kΩ 50 pF 0 -15V 2 3 4 5 13 LOGIC LEVEL (HIGH) (V) 14 15 † Similar connection for HI-507/ HI-508/HI-509 FIGURE 5A. ACCESS TIME vs LOGIC LEVEL (HIGH) FIGURE 5B. TEST CIRCUIT 3.5V 50% ADDRESS DRIVE (VA) 0V VA INPUT 2V/DIV. S1 ON +10V OUTPUT 10% tA -10V OUTPUT 5V/DIV. S16 ON 200ns/DIV. FIGURE 5C. MEASUREMENT POINTS FIGURE 5. ACCESS TIME FIGURE 5D. WAVEFORMS +15V A3 A2 V+ HI-506 † +5V IN 1 VA 50Ω A1 A0 IN 2 THRU IN 7/IN 15 IN 8 /16 VOUT GND OUT V200Ω 50pF 3.5V EN -15V † Similar connection for HI-507/HI-508/HI-509 FIGURE 6A. TEST CIRCUIT 12 FN3142.8 October 30, 2007 HI-506, HI-507, HI-508, HI-509 Test Circuits and Waveforms TA = +25°C, VSUPPLY = ±15V, VAH = 2.4V, VAL = 0.8V, Unless Otherwise Specified (Continued) 3.5V VA INPUT 2V/DIV. ADDRESS DRIVE (VA) OUTPUT S1 ON S16 ON 0V OUTPUT 1V/DIV. 50% 50% tOPEN 100ns/DIV. FIGURE 6B. MEASUREMENT POINTS FIGURE 6. BREAK-BEFORE-MAKE DELAY +15V FIGURE 6C. WAVEFORMS A3 A2 V+ HI-506 † IN 1 +10V A1 A0 EN VA 50Ω IN 2 THRU IN 7/IN 15 IN 8 /16 VOUT GND OUT V200Ω 50pF -15V † Similar connection for HI-507/HI-508/HI-509 FIGURE 7A. TEST CIRCUIT 3.5V 50% 50% ENABLE DRIVE (VA) 0V 90% OUTPUT 10% tON(EN) tOFF(EN) ENABLE DRIVE 2V/DIV. DISABLED ENABLED (S1 ON) OUTPUT 2V/DIV. 100ns/DIV 0V FIGURE 7B. MEASUREMENT POINTS FIGURE 7. ENABLE DELAYS FIGURE 7C. WAVEFORMS 13 FN3142.8 October 30, 2007 HI-506, HI-507, HI-508, HI-509 Typical Performance Curves 4 TA = 25°C, VSUPPLY = ±15V, VAH = 2.4V, VAL = 0.8V, Unless Otherwise Specified 100 (VS), (VD) OFF ISOLATION (dB) INPUT LOGIC THRESHOLD (V) 3 80 RL = 1k 60 RL = 10M 40 2 1 20 VEN = 0V CLOAD = 28pF VS = 7VRMS 105 106 107 0 10 12 14 16 18 20 POWER SUPPLY VOLTAGE (±V) 0 104 FREQUENCY (Hz) FIGURE 8. LOGIC THRESHOLD vs POWER SUPPLY VOLTAGE FIGURE 9. OFF ISOLATION vs FREQUENCY 3 POWER SUPPLY CURRENT (mA) POWER SUPPLY CURRENT (mA) 3 2 VEN = 2.4V VEN = 0V 1 2 EN = 5V 1 EN = 0V 0 -55 0 -35 -15 -5 25 45 65 85 105 125 TEMPERATURE (°C) -55 -35 -15 -5 25 45 65 85 105 125 TEMPERATURE (°C) FIGURE 10A. HI-506/HI-507 FIGURE 10B. HI-508/HI-509 FIGURE 10. POWER SUPPLY CURRENT vs TEMPERATURE 14 FN3142.8 October 30, 2007 HI-506, HI-507, HI-508, HI-509 Die Characteristics METALLIZATION: Type: CuAl Thickness: 16kÅ ±2kÅ SUBSTRATE POTENTIAL (NOTE): -VSUPPLY PASSIVATION: Type: Nitride/Silox Nitride Thickness: 3.5kÅ ±1kÅ Silox Thickness: 12kÅ ±2kÅ NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential. WORST CASE CURRENT DENSITY: 1.4 x 105 A/cm2 TRANSISTOR COUNT: 421 PROCESS: CMOS-DI Metallization Mask Layout HI-506 EN A0 A1 A2 A3 GND EN A0 A1 A2 NC HI-507 GND IN 1 IN 9 IN 1A IN 1B IN 2 IN 10 IN 2A IN 2B IN 3 IN 11 IN 3A IN 3B IN 4 IN 12 IN 13 IN 4A IN 4B IN 5B IN 5 IN 5A IN 6 IN 14 IN 15 IN 6A IN 6B IN 7B IN 7 IN 7A IN 8 IN 16 IN 8A IN 8B -V OUT +V NC -V OUT A +V OUT B 15 FN3142.8 October 30, 2007 HI-506, HI-507, HI-508, HI-509 Die Characteristics METALLIZATION: Type: CuAl Thickness: 16kÅ ±2kÅ SUBSTRATE POTENTIAL (NOTE): -VSUPPLY PASSIVATION: Type: Nitride/Silox Nitride Thickness: 3.5kÅ ±1kÅ Silox Thickness: 12kÅ ±2kÅ NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential. WORST CASE CURRENT DENSITY: 1.4 x 105 A/cm2 TRANSISTOR COUNT: 234 PROCESS: CMOS-DI Metallization Mask Layout HI-508 EN A0 A1 A2 GND EN A0 A1 HI-509 GND -VSUP IN 1 IN 2 +VSUP IN 5 -VSUP IN 1A IN 2A +VSUP IN 1B IN 6 IN 2B IN 3 IN 7 IN 4 OUT IN 8 IN 3A IN 3B IN 4A OUT A OUT B IN 4B 16 FN3142.8 October 30, 2007 HI-506, HI-507, HI-508, HI-509 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E E16.3 (JEDEC MS-001-BB ISSUE D) 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280 MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93 -C- A2 B B1 C D D1 E E1 e eA eB L N eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 0.100 BSC 0.300 BSC 0.115 16 0.430 0.150 2.54 BSC 7.62 BSC 2.93 16 10.92 3.81 17 FN3142.8 October 30, 2007 HI-506, HI-507, HI-508, HI-509 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E28.6 (JEDEC MS-011-AB ISSUE B) 28 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 3.18 0.356 0.77 0.204 35.1 0.13 15.24 12.32 MAX 6.35 4.95 0.558 1.77 0.381 39.7 15.87 14.73 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 1 12/00 MIN 0.015 0.125 0.014 0.030 0.008 1.380 0.005 0.600 0.485 MAX 0.250 0.195 0.022 0.070 0.015 1.565 0.625 0.580 A E A2 L A C L -AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A1 A2 -C- B B1 C D D1 E E1 e eA eB L N eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 0.100 BSC 0.600 BSC 0.115 28 0.700 0.200 2.54 BSC 15.24 BSC 2.93 28 17.78 5.08 18 FN3142.8 October 30, 2007 HI-506, HI-507, HI-508, HI-509 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.840 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 21.34 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94 α eA c1 D E e eA eA/2 L Q S1 e DS eA/2 c 0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 16 0.200 0.060 105o 0.015 0.030 0.010 0.0015 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 16 5.08 1.52 105o 0.38 0.76 0.25 0.038 aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. α aaa bbb ccc M N 19 FN3142.8 October 30, 2007 HI-506, HI-507, HI-508, HI-509 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A) 28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.500 MAX 0.232 0.026 0.023 0.065 0.045 0.018 0.015 1.490 0.610 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 12.70 MAX 5.92 0.66 0.58 1.65 1.14 0.46 0.38 37.85 15.49 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94 α eA c1 D E e eA eA/2 L Q S1 e DS eA/2 c 0.100 BSC 0.600 BSC 0.300 BSC 0.125 0.015 0.005 90o 28 0.200 0.060 105o 0.015 0.030 0.010 0.0015 2.54 BSC 15.24 BSC 7.62 BSC 3.18 0.38 0.13 90o 28 5.08 1.52 105o 0.38 0.76 0.25 0.038 aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. α aaa bbb ccc M N 20 FN3142.8 October 30, 2007 HI-506, HI-507, HI-508, HI-509 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45° H 0.25(0.010) M BM M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 1.35 0.10 0.33 0.19 9.80 3.80 MAX 1.75 0.25 0.51 0.25 10.00 4.00 NOTES 9 3 4 5 6 7 8° Rev. 1 6/05 MIN 0.0532 0.0040 0.013 0.0075 0.3859 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.3937 0.1574 A1 B C D E α A1 0.10(0.004) C e H h L N 0.050 BSC 0.2284 0.0099 0.016 16 0° 8° 0.2440 0.0196 0.050 1.27 BSC 5.80 0.25 0.40 16 0° 6.20 0.50 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 21 FN3142.8 October 30, 2007 HI-506, HI-507, HI-508, HI-509 Small Outline Plastic Packages (SOIC) N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45o 0.25(0.010) M BM M28.3 (JEDEC MS-013-AE ISSUE C) 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 2.35 0.10 0.33 0.23 17.70 7.40 10.00 0.25 0.40 28 0o MAX 2.65 0.30 0.51 0.32 18.10 7.60 10.65 0.75 1.27 8o NOTES 9 3 4 5 6 7 Rev. 0 12/93 MIN 0.0926 0.0040 0.013 0.0091 0.6969 0.2914 0.394 0.01 0.016 28 0o MAX 0.1043 0.0118 0.0200 0.0125 0.7125 0.2992 0.419 0.029 0.050 8o A1 B C D E e H C α A1 0.10(0.004) 0.05 BSC 1.27 BSC e B 0.25(0.010) M C AM BS h L N NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 22 FN3142.8 October 30, 2007 HI-506, HI-507, HI-508, HI-509 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER C L 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP 0.004 (0.10) C N20.35 (JEDEC MS-018AA ISSUE A) 20 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL A MIN 0.165 0.090 0.385 0.350 0.141 0.385 0.350 0.141 20 MAX 0.180 0.120 0.395 0.356 0.169 0.395 0.356 0.169 MILLIMETERS MIN 4.20 2.29 9.78 8.89 3.59 9.78 8.89 3.59 20 MAX 4.57 3.04 10.03 9.04 4.29 10.03 9.04 4.29 NOTES 3 4, 5 3 4, 5 6 Rev. 2 11/97 0.025 (0.64) R 0.045 (1.14) D2/E2 E1 E C L A1 D D1 D2/E2 VIEW “A” D2 E E1 D1 D 0.020 (0.51) MAX 3 PLCS A1 A 0.020 (0.51) MIN E2 N SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53) 0.045 (1.14) MIN VIEW “A” TYP. 0.025 (0.64) MIN NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. 23 FN3142.8 October 30, 2007 HI-506, HI-507, HI-508, HI-509 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER C L 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP 0.004 (0.10) C N28.45 (JEDEC MS-018AB ISSUE A) 28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL A MIN 0.165 0.090 0.485 0.450 0.191 0.485 0.450 0.191 28 MAX 0.180 0.120 0.495 0.456 0.219 0.495 0.456 0.219 MILLIMETERS MIN 4.20 2.29 12.32 11.43 4.86 12.32 11.43 4.86 28 MAX 4.57 3.04 12.57 11.58 5.56 12.57 11.58 5.56 NOTES 3 4, 5 3 4, 5 6 Rev. 2 11/97 0.025 (0.64) R 0.045 (1.14) D2/E2 E1 E C L A1 D D1 D2/E2 VIEW “A” D2 E E1 D1 D 0.020 (0.51) MAX 3 PLCS A1 A 0.020 (0.51) MIN E2 N SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53) 0.045 (1.14) MIN VIEW “A” TYP. 0.025 (0.64) MIN NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 24 FN3142.8 October 30, 2007