HI-516

HI-516 Data Sheet October 1999 File Number 3146.3 16-Channel/Differential 8-Channel, CMOS High Speed Analog Multiplexer The Hl-516 is a monolithic, dielectrically isolated, highspeed, high-performance CMOS analog multiplexer. It offers unique built-in channel selection decoding plus an inhibit input for disabling all channels. The dual function of address input A3 enables the Hl-516 to be user programmed either as a single ended 16-Channel multiplexer by connecting ‘out A’ to ‘out B’ and using A3 as a digital address input, or as an 8-Channel differential multiplexer by connecting A3 to the V- supply. The substrate leakages and parasitic capacitances are reduced substantially by using the Intersil Dielectric Isolation process to achieve optimum performance in both high and low level signal applications. The low output leakage current (lD(OFF) < 100pA at 25oC) and fast settling (tSETTLE = 800ns to 0.01%) characteristics of the device make it an ideal choice for high speed data acquisition systems, precision instrumentation, and industrial process control. For MIL-STD-883 compliant parts, request the Hl-516/883 data sheet. Features • Access Time (Typical) . . . . . . . . . . . . . . . . . . . . . . . 130ns • Settling Time . . . . . . . . . . . . . . . . . . . . . . . . 250ns (0.1%) • Low Leakage (Typical) - IS(OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10pA - ID(OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30pA • Low Capacitance (Max) - CS(OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10pF - CD(OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25pF • Off Isolation at 500kHz . . . . . . . . . . . . . . . . . . 55dB (Min) • Low Charge Injection Error . . . . . . . . . . . . . . . . . . . 20mV • Single Ended to Differential Selectable (SDS) • Logic Level Selectable (LLS) Applications • Data Acquisition Systems • Precision Instrumentation • Industrial Control Ordering Information PART NUMBER HI3-0516-5 TEMP. RANGE (oC) 0 to 75 PACKAGE 28 Ld PDIP PKG. NO. E28.6 Pinout HI-516 (PDIP) TOP VIEW V+ 1 OUT B 2 NC 3 IN 16/8B 4 IN 15/7B 5 IN 14/6B 6 IN 13/5B 7 IN 12/4B 8 IN 11/3B 9 IN 10/2B 10 IN 9/1B 11 GND 12 VDD /LLS 13 A3 /SDS 14 28 OUT A 27 V26 IN 8/8A 25 IN 7/7A 24 IN 6/6A 23 IN 5/5A 22 IN 4/4A 21 IN 3/3A 20 IN 2/2A 19 IN 1/1A 18 ENABLE 17 A0 16 A1 15 A2 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 407-727-9207 | Copyright © Intersil Corporation 1999 HI-516 Truth Tables HI-516 USED AS A 16-CHANNEL MULTIPLEXER OR DUAL 8-CHANNEL MULTIPLEXER (NOTE 1) USE A3 AS DIGITAL ADDRESS INPUT ENABLE L H H H H H H H H H H H H H H H H NOTE: 1. For 16-channel single-ended function, tie ‘out A’ to ‘out B’; for dual 8-channel function use the A3 address pin to select between MUX A and MUX B, where MUX A is selected with A3 low. X L L L L L L L L H H H H H H H H A3 X L L L L H H H H L L L L H H H H A2 X L L H H L L H H L L H H L L H H A1 X L H L H L H L H L H L H L H L H A0 ON CHANNEL TO OUT A None 1A 2A 3A 4A 5A 6A 7A 8A None None None None None None None None OUT B None None None None None None None None None 1B 2B 3B 4B 5B 6B 7B 8B HI-516 USED AS A DIFFERENTIAL 8-CHANNEL MULTIPLEXER A3 CONNECTED TO V- SUPPLY ENABLE L H H H H H H H H A2 X L L L L H H H H A1 X L L H H L L H H A0 X L H L H L H L H ON CHANNEL TO OUT A None 1A 2A 3A 4A 5A 6A 7A 8A OUT B None 1B 2B 3B 4B 5B 6B 7B 8B 2 HI-516 Functional Block Diagram VDD /LLS IN 1A N EN A0 A1 A2 A3 Q A3 DECODER Q N P OUT B DECODER IN 8B N P N P DECODER IN 8A P OUT A IN 1B INPUT BUFFER AND DECODERS MULTIPLEXER SWITCHES A3 DECODE A3 H L VQ H L L Q L H L 3 HI-516 Absolute Maximum Ratings V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33V Analog Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VIN , VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V Digital Input Voltage: TTL Levels Selected (VDD /LLS Pin = GND or Open) VA0-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to +6V VA3/SDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V CMOS Levels Selected (VDD /LLS Pin = VDD) VA0-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to (V+) +2V Thermal Information Thermal Resistance (Typical, Note 2) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Maximum Junction Temperature Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC Operating Conditions Temperature Ranges HI-516-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.8V; VDD /LLS = GND. (Note 3) Unless Otherwise Specified -5 TEST CONDITIONS TEMP (oC) PARAMETER DYNAMIC CHARACTERISTICS Access Time, tA MIN TYP MAX UNITS 25 Full 10 55 - 130 20 120 140 250 800 - 175 225 175 175 20 10 25 ns ns ns ns ns ns ns mV dB pF pF Break-Before-Make Delay, tOPEN Enable Delay (ON), tON(EN) Enable Delay (OFF), tOFF(EN) Settling Time To 0.1% To 0.01% Charge Injection Error Off Isolation Channel Input Capacitance, CS(OFF) Channel Output Capacitance, CD(OFF) Digital Input Capacitance, CA Input to Output Capacitance, CDS(OFF) DIGITAL INPUT CHARACTERISTICS Input Low Threshold, VAL (TTL) Input High Threshold, VAH (TTL) Input Low Threshold, VAL (CMOS) Input High Threshold, VAH (CMOS) Input Leakage Current, IAH (High) Note 3 Note 3 Note 3 Note 3 Note 6 Note 7 25 25 25 25 25 25 25 25 25 25 25 - 0.02 10 - pF pF Full Full Full Full Full 2.4 0.7VDD - - 0.8 0.3VDD 1 V V V V µA 4 HI-516 Electrical Specifications Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.8V; VDD /LLS = GND. (Note 3) Unless Otherwise Specified (Continued) -5 PARAMETER Input Leakage Current, IAL (Low) ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, VIN On Resistance, rON Note 4 Note 5 Full 25 Full Off Input Leakage Current, lS(OFF) 25 Full Off Output Leakage Current, ID(OFF) On Channel Leakage Current, ID(ON) POWER SUPPLY CHARACTERISTICS Power Dissipation, PD I+, Current I-, Current NOTES: 3. VDD /LLS pin = open or grounded for TTL compatibility. VDD /LLS pin = VDD for CMOS compatibility. 4. At temperatures above 90oC, care must be taken to assure VIN remains at least 1V below the VSUPPLY for proper operation. 5. VIN = ±10V, IOUT = -100µA. 6. VIN = 0V, CL = 100pF, enable input pulse = 3V, f = 500kHz. 7. VEN = 0.8V, VIN = 3VRMS , f = 500kHz, CL = 40pF, RL = 1K, Pin 3 grounded. VEN = 2.4V Full Full Full 900 30 30 mW mA mA 25 Full 25 -15 620 0.01 0.03 0.04 +15 750 1,000 50 100 V Ω Ω nA nA nA nA nA TEST CONDITIONS TEMP (oC) Full MIN TYP MAX 25 UNITS µA 5 HI-516 Test Circuits and Waveforms IOUT 100µA EN V2 IN ±10V OUT rON = V2 100µA ±10V OUT A ID(OFF) 10V ± 0.8V VDD /LLS = GND, Unless Otherwise Specified. VIN FIGURE 1. ON RESISTANCE TEST CIRCUIT FIGURE 2. ID(OFF) TEST CIRCUIT (NOTE 8) OUT OUT IS(OFF) A EN ± ±10V 10V 2.4V 0.8V 10V ±10V ± EN A ID(ON) FIGURE 3. IS(OFF) TEST CIRCUIT (NOTE 8) FIGURE 4. ID(ON) TEST CIRCUIT (NOTE 8) +15V 3.5V 50% 0V A2 +10V OUTPUT 10% tA 2.4V VA 50Ω A1 A0 EN VDD/LLS IN 2-15 IN 16 OUT A OUT B V10 kΩ 50 pF 10V ± ADDRESS DRIVE (VA) A3/SDS V+ IN 1 ±10V -10V GND -15V FIGURE 5A. MEASUREMENT POINTS NOTE: 8. Two measurements per channel: ±10V and FIGURE 5B. TEST CIRCUIT 10V. (Two measurements per device for ID(OFF) ±10V and 10V). FIGURE 6. ACCESS TIME 6 HI-516 Test Circuits and Waveforms VDD /LLS = GND, Unless Otherwise Specified. (Continued) +15V 3.5V V+ A3 A2 IN 1 IN 2-15 VA 50Ω A1 A0 2.4V EN VDD /LLS GND tOPEN -15V IN 16 OUTA OUTB V800 Ω VOUT 12.5pF +5V 0V ADDRESS DRIVE (VA) OUTPUT S1 ON 50% 50% S16 ON FIGURE 7A. MEASUREMENT POINTS FIGURE 7. BREAK-BEFORE-MAKE DELAY FIGURE 7B. TEST CIRCUIT +15V 3.5V ENABLE DRIVE (VA) 50% 50% 0V 90% OUTPUT 10% 0V tON(EN) tOFF(EN) VA 50 Ω A1 A0 EN VDD /LLS GND A3 A2 V+ IN 1 +10V IN 2-16 OUTA V- VOUT 800 Ω 12.5pF -15V FIGURE 8A. MEASUREMENT POINTS FIGURE 8. ENABLE DELAYS FIGURE 8B. TEST CIRCUIT +15V 2.4V V+ 3.0V VA VOUT 0V OUT ∆VO EN IN A OR B VOUT CL = 100pF A 0 , A1 , A2 , A3 /SDS VA GND VDD/LLS V- -15V FIGURE 9A. MEASUREMENT POINTS FIGURE 9B. TEST CIRCUIT ∆VO is the measured voltage error due to charge injection. The error in coulombs is Q = CL x ∆VO . FIGURE 9. CHARGE INJECTION 7 HI-516 Die Characteristics DIE DIMENSIONS: 2250µm x 3720µm x 485µm METALLIZATION: Type: CuAl Thickness: 16kÅ ±2kÅ PASSIVATION: Type: Nitride Over Silox Nitride Thickness: 3.5kÅ ±1kÅ Silox Thickness: 12kÅ ±2kÅ WORST CASE CURRENT DENSITY: 1.64 x 105 A/cm2 Metallization Mask Layout HI-516 ENABLE A0 A1 A2 A3 /SDS (18) (17) (16) (15) (14) VDD /LLS GND (13) (12) IN 1/1A (19) (10) IN 9/1B IN 2/2A (20) (9) IN 10/2B IN 3/3A (21) (8) IN 11/3B IN 4/4A (22) (7) IN 12/4B IN 5/5A (23) (6) IN 13/5B IN 6/6A (24) (5) IN 14/6B IN 7/7A (25) (4) IN 15/7B IN 8/8A (26) (3) IN 16/8B (27) (28) -V OUT A (1) +V (2) OUT B All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 8