HI-539

® HI-539 Data Sheet August 2003 FN3149.3 Precision, 4-Channel, Low-Level, Differential Multiplexer The Intersil HI-539 is a monolithic, 4-Channel, differential multiplexer. Two digital inputs are provided for channel selection, plus an Enable input to disconnect all channels. Performance is guaranteed for each channel over the voltage range ±10V, but is optimized for low level differential signals. Leakage current, for example, which varies slightly with input voltage, has its distribution centered at zero input volts. In most monolithic multiplexers, the net differential offset due to thermal effects becomes significant for low level signals. This problem is minimized in the HI-539 by symmetrical placement of critical circuitry with respect to the few heat producing devices. Supply voltages are ±15V and power consumption is only 2.5mW. Features • Differential Performance, Typical: - Low ∆rON , 125oC . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5Ω - Low ∆ID(ON) , 125oC. . . . . . . . . . . . . . . . . . . . . . . 0.6nA - Low ∆ Charge Injection . . . . . . . . . . . . . . . . . . . . 0.1pC - Low Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . -124dB • Settling Time, ±0.01% . . . . . . . . . . . . . . . . . . . . . . . 900ns • Wide Supply Range . . . . . . . . . . . . . . . . . . . ±5V to ±18V • Break-Before-Make Switching • No Latch-Up Applications • Low Level Data Acquisition • Precision Instrumentation • Test Systems TRUTH TABLE Ordering Information PART NUMBER HI1-0539-5 TEMP. RANGE (oC) 0 to 75 PACKAGE 16 Ld CERDIP PKG. DWG. # F16.3 EN L H HI-539 (CERDIP) TOP VIEW A0 1 EN 2 V- 3 IN 1A 4 IN 2A 5 IN 3A 6 IN 4A 7 OUT A 8 16 A1 15 GND 14 V+ 13 IN 1B 12 IN 2B 11 IN 3B 10 IN 4B 9 OUT B ON CHANNEL TO A1 X L L H H A0 X L H L H OUT A None 1A 2A 3A 4A OUT B None 1B 2B 3B 4B Pinouts H H H 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HI-539 Absolute Maximum Ratings V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V V+ or V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V Analog Signal (VIN, VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . V- to V+ Digital Input Voltage (VEN, VA) . . . . . . . . . . . . . . . . . . . . . . V- to V+ Analog Current (IN or OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 75 20 Maximum Junction Temperature Ceramic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC Operating Conditions Temperature Range HI-539-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Supplies = ±15V, VEN = 4V, VAH (Logic Level High) = 4V, VAL (Logic Level Low) = 0.8V, Unless Otherwise Specified TEST CONDITIONS TEMP (oC) MIN TYP MAX UNITS PARAMETER DYNAMIC CHARACTERISTICS Access Time, tA 25 Full 30 30 - 250 85 250 160 0.9 3 0.1 10 -124 -100 5 7 17 0.08 3 750 1,000 750 1,000 650 900 - ns ns ns ns ns ns ns ns µs pC pC pC dB dB pF pF pF pF pF Break-Before-Make Delay, tOPEN 25 Full Enable Delay (ON), tON(EN) 25 Full Enable Delay (OFF), tOFF(EN) 25 Full Settling Time Charge Injection (Output) ∆ Charge Injection (Output) Charge Injection (Input) Differential Crosstalk Single Ended Crosstalk Channel Input Capacitance, CS(OFF) Channel Output Capacitance, CD(OFF) Channel On Output Capacitance, CD(ON) Input to Output Capacitance, CDS(OFF) Digital Input Capacitance, CA DIGITAL INPUT CHARACTERISTICS Input Low Threshold, VAL Input High Threshold, VAH Input Leakage Current (High), IAH Input Leakage Current (Low), IAL ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, VIN To 0.01% 25 Full Full Full Note 4 Note 4 25 25 Full Full Full Note 5 Full Full Full Full Full Full 4.0 - - 0.8 1 1 V V µA µA Full -10 - +10 V 2 HI-539 Electrical Specifications Supplies = ±15V, VEN = 4V, VAH (Logic Level High) = 4V, VAL (Logic Level Low) = 0.8V, Unless Otherwise Specified (Continued) TEST CONDITIONS VIN = 0V VlN = ±10V ∆rON, (Side A-Side B) TEMP (oC) 25 Full 25 Full VIN = 0V VlN = ±10V 25 Full 25 Full Off Input Leakage Current, IS(OFF) Condition 0V (Note 2) Condition ±10V (Note 2) ∆IS(OFF), (Side A-Side B) Condition 0V 25 Full 25 Full 25 Full Condition ±10V 25 Full Off Output Leakage Current, ID(OFF) Condition 0V (Note 2) Condition ±10V (Note 2) ∆ID(OFF), (Side A-Side B) Condition 0V 25 Full 25 Full 25 Full Condition ±10V 25 Full On Channel Leakage Current, ID(ON) Condition 0V (Note 2) Condition ±10V (Note 2) ∆ID(ON), (Side A-Side B) Condition 0V 25 Full 25 Full 25 Full Condition ±10V 25 Full Differential Offset Voltage, ∆VOS Note 3 25 Full POWER SUPPLY CHARACTERISTICS Power Dissipation, PD 25 Full Current, l+ 25 Full 2.3 0.150 45 2.0 mW mW mA mA MIN TYP 650 800 700 900 4.0 4.0 4.5 4.5 30 0.2 100 0.5 3 0.02 10 0.05 30 0.2 100 0.5 3 0.02 10 0.05 50 0.5 150 0.8 10 0.05 30 0.08 0.02 0.08 MAX 850 1K 900 1.1K 24 24 27 27 1 2.5 0.2 0.5 1 2.5 0.2 0.5 2.5 4.0 0.5 0.8 UNITS Ω Ω Ω Ω Ω Ω Ω Ω pA nA pA nA pA nA pA nA pA nA pA nA pA nA pA nA pA nA pA nA pA nA pA nA µV µV PARAMETER On Resistance, rON 3 HI-539 Electrical Specifications Supplies = ±15V, VEN = 4V, VAH (Logic Level High) = 4V, VAL (Logic Level Low) = 0.8V, Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (oC) 25 Full Supply Voltage Range NOTES: 2. See Figures 2B, 2C, 2D. The condition ±10V means: lS(OFF) and ID(OFF): (VS = +10V, VD = -10V), then (VS = -10V, VD = +10V) ID(ON): (+10V, then -10V) 3. ∆VOS (Exclusive of thermocouple effects) = rON ∆ID(ON) + ID(ON) ∆rON . See Applications section for discussion of additional VOS error. 4. VlN = 1kHz, 15VP-P on all but the selected channel. See Figure 7. 5. Calculated from typical Single-Ended Crosstalk performance. Full MIN ±5 TYP 0.001 ±15 MAX 1.0 ±18 UNITS mA mA V PARAMETER Current, l- Test Circuits and Waveforms 100µA Unless Otherwise Specified TA = 25oC, V+ = +15V, V- = -15V, VAH = 4V and VAL = 0.8V VIN = 0V 800 ON RESISTANCE (Ω) V2 700 IN OUT V2 100µA VIN HI-539 rON = 600 500 -50 -25 0 25 50 75 100 125 TEMPERATURE (oC) FIGURE 1A. TEST CIRCUIT FIGURE 1B. ON RESISTANCE vs TEMPERATURE 900 125oC 800 ON RESISTANCE (kΩ) ON RESISTANCE (Ω) 700 25oC 600 500 -55oC 400 -12 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 5 7 9 11 13 SUPPLY VOLTAGE (±V) VIN = 0V -10 -8 -6 -4 -2 0 2 4 ANALOG INPUT (V) 6 8 10 12 15 17 FIGURE 1C. ON RESISTANCE vs ANALOG INPUT VOLTAGE FIGURE 1D. ON RESISTANCE vs SUPPLY VOLTAGE FIGURE 1. ON RESISTANCE 4 HI-539 Test Circuits and Waveforms 10 HI-539† EN ID(ON) 1 A ID(OFF) OUT A 0.8V Unless Otherwise Specified TA = 25oC, V+ = +15V, V- = -15V, VAH = 4V and VAL = 0.8V (Continued) LEAKAGE CURRENT (nA) ID(OFF) = IS(OFF) A0 25 50 75 TEMPERATURE (oC) 100 125 A1 † Similar Connection For Side “B” FIGURE 2B. ID(OFF) TEST CIRCUIT (NOTE 6) FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE HI-539† HI-539† OUT A A IS(OFF) EN ± 10V 0.8V A0 A1 OUT A A EN ID(ON) ±10V 4V † Similar Connection For Side “B” FIGURE 2C. IS(OFF) TEST CIRCUIT (NOTE 6) ± NOTE: 6. Three measurements = ±10V, 10V, and 0V. FIGURE 2. LEAKAGE CURRENT 14 FUNCTIONAL LIMIT I+ SUPPLY CURRENT (mA) 12 10 VSUPPLY = ±15V 8 6 4 2 0 100Hz 5V EN GND VA 1kHz 10kHz 100kHz 1MHz 3MHz 10MHz HIGH = 4.0V LOW = 0V 50% DUTY CYCLE VSUPPLY = ±10V VA 50Ω A1 A0 FIGURE 3A. SUPPLY CURRENT vs TOGGLE FREQUENCY FIGURE 3. DYNAMIC SUPPLY CURRENT ± ±10V 10V A0 A1 †Similar Connection For Side “B” FIGURE 2D. ID(ON) TEST CIRCUIT (NOTE 6) A +15V/+10V +ISUPPLY HI-539 † V+ IN 1A IN 2A IN 3A IN 4A +10V/+5V ±-10V/-5V OUT A V10MΩ A -ISUPPLY -15V/-10V 14pF TOGGLE FREQUENCY †Similar Connection For Side “B” FIGURE 3B. TEST CIRCUIT 5 ± ±10V 10V HI-539 Test Circuits and Waveforms 320 300 A1 ACCESS TIME (ns) 280 260 240 5V 220 200 3 4 5 6 7 8 9 10 11 12 13 14 15 LOGIC LEVEL (HIGH) (V) VA 50Ω A0 HI-539 IN 4A EN GND OUT A V± 10V V+ IN 1A IN 2A, IN 3A ±10V Unless Otherwise Specified TA = 25oC, V+ = +15V, V- = -15V, VAH = 4V and VAL = 0.8V (Continued) +15V 10 kΩ 50 pF -15V FIGURE 4A. ACCESS TIME vs LOGIC LEVEL (HIGH) FIGURE 4B. TEST CIRCUIT VAH = 4V ADDRESS DRIVE (VA) 0V VA INPUT 2V/DIV. S1 ON 50% +10V OUTPUT 10% tA 200ns/DIV. OUTPUT 5V/DIV. -10V S4 ON FIGURE 4C. MEASUREMENT POINTS FIGURE 4. ACCESS TIME FIGURE 4D. WAVEFORMS +15V VAH = 4V HI-539 † ADDRESS DRIVE (VA) A1 OUTPUT 50% 50% VA tOPEN 50Ω 5V A0 EN GND V+ +5V IN 1A IN 2, IN 3A IN 4A VOUT OUT A V700 Ω 12.5pF 0V -15V † Similar connection for side “B” FIGURE 5A. MEASUREMENT POINTS FIGURE 5B. TEST CIRCUIT 6 HI-539 Test Circuits and Waveforms Unless Otherwise Specified TA = 25oC, V+ = +15V, V- = -15V, VAH = 4V and VAL = 0.8V (Continued) VA INPUT 2V/DIV. S1 ON S4 ON OUTPUT 1V/DIV. 100ns/DIV. FIGURE 5C. WAVEFORMS FIGURE 5. BREAK-BEFORE-MAKE DELAY +15V VAH = 4V 50% 50% ENABLE DRIVE (VA) HI-539 † V+ IN 1A +10V A1 0V 90% OUTPUT 10% 0V tON(EN) tOFF(EN) VA 50 Ω A0 EN IN 2A THRU IN 4A VOUT GND OUT A V700 Ω 12.5pF -15V † Similar connection for side “B” FIGURE 6B. TEST CIRCUIT FIGURE 6A. MEASUREMENT POINTS ENABLE DRIVE 2V/DIV. ENABLED DISABLED (S1 ON) OUTPUT 2V/DIV. 100ns/DIV. FIGURE 6C. WAVEFORMS FIGURE 6. ENABLE DELAYS 7 HI-539 Test Circuits and Waveforms HI-539 INSTRUMENTATION AMPLIFIER † G = 1000 + Unless Otherwise Specified TA = 25oC, V+ = +15V, V- = -15V, VAH = 4V and VAL = 0.8V (Continued) HI-539 INSTRUMENTATION AMPLIFIER† G = 1000 + 350Ω 350Ω 1kHz, 15VP-P 350Ω 1kHz, 15VP-P - † AD606 or BB3630, for Example FIGURE 7A. SINGLE-ENDED CROSSTALK TEST CIRCUIT † AD606 or BB3630, for example FIGURE 7B. DIFFERENTIAL CROSSTALK TEST CIRCUIT FIGURE 7. CROSSTALK Application Information General The Hl-539 accepts inputs in the range -15V to +15V, with performance guaranteed over the ±10V range. At these higher levels of analog input voltage it is comparable to the HI-509, and is plug-in compatible with that device (as well as the Hl-509A). However, as mentioned earlier, the Hl-539 was designed to introduce minimum error when switching low level inputs. Special care is required in working with these low level signals. The main concern with signals below 100mV is that noise, offset voltage, and other aberrations can represent a large percentage error. A shielded differential signal path is essential to maintain a noise level below 50µVRMS . Coaxial cable is not suitable for low level signals because the two conductors (center and shield) are unbalanced. Also, ground loops are produced if the shield is grounded at both ends by standard BNC connectors. If coax must be used, carry the signal on the center conductors of two equal-length cables whose shields are terminated only at the transducer end. As a general rule, terminate (ground) the shield at one end only, preferably at the end with greatest noise interference. This is usually the transducer end for both high and low level signals. Watch Small ∆V Errors Printed circuit traces and short lengths of wire can add substantial error to a signal even after it has traveled hundreds of feet and arrived on a circuit board. Here, the small voltage drops due to current flow through connections of a few milliohms must be considered, especially to meet an accuracy requirement of 12 bits or more. Table 1 is a useful collection of data for calculating the effect of these short connections. (Proximity to a ground plane will lower the values of inductance.) As an example, suppose the Hl-539 is feeding a 12-bit converter system with an allowable error of ±1/2 LSB (±1.22mV). lf the interface logic draws 100mA from the 5V supply, this current will produce 1.28mV across 6 inches of #24 wire; more than the error budget. Obviously, this digital current must not be routed through any portion of the analog ground return network. Low Level Signal Transmission The transmission cable carrying the transducer signal is critical in a low level system. It should be as short as practical and rigidly supported. Signal conductors should be tightly twisted for minimum enclosed area to guard against pickup of electromagnetic interference, and the twisted pair should be shielded against capacitively coupled (electrostatic) interference. A braided wire shield may be satisfactory, but a lapped foil shield is better since it allows only 1/10 as much leakage capacitance to ground per foot. A key requirement for the transmission cable is that it presents a balanced line to sources of noise interference. This means an equal series impedance in each conductor plus an equally distributed impedance from each conductor to ground. The result should be signals equal in magnitude but opposite in phase at any transverse plane. Noise will be coupled in phase to both conductors, and may be rejected as common-mode voltage by a differential amplifier connected to the multiplexer output. 8 HI-539 TABLE 1. EQUIVALENT WIDTH OF P.C. CONDUCTOR (2 oz. Cu) 0.47” 0.30” 0.19” 0.12” 0.075” 0.047” 0.029” 0.018” IMPEDANCE PER FOOT DC RESISTANCE PER FOOT 0.0064Ω 0.0102Ω 0.0161Ω 0.0257Ω 0.041Ω 0.066Ω 0.105Ω 0.168Ω INDUCTANCE PER FOOT 0.36µH 0.37µH 0.37µH 0.40µH 0.42µH 0.45µH 0.49µH 0.53µH 60Hz 0.0064Ω 0.0102Ω 0.0161Ω 0.0257Ω 0.041Ω 0.066Ω 0.105Ω 0.168Ω 10kHz 0.0235Ω 0.0254Ω 0.0288Ω 0.0345Ω 0.0488Ω 0.0718Ω 0.110Ω 0.171Ω WIRE GAGE 18 20 22 24 26 28 30 32 Provide Path For IBIAS The input bias current for any DC-coupled amplifier must have an external path back to the amplifier’s power supply. No such path exists in Figure 8A, and consequently the amplifier output will remain in saturation. A single large resistor (1MΩ to 10MΩ) from either signal line to power supply common will provide the required path, but a resistor on each line is necessary to preserve accuracy. A single pair of these bias current resistors on the HI-539 output may be used if their loading effect can be tolerated (each forms a voltage divider with rON). Otherwise, a resistor pair on each input channel of the multiplexer is required. The use of bias current resistors is acceptable only if one is confident that the sum of signal plus common-mode voltage will remain within the input range of the multiplexer/amplifier combination. Another solution is to simply run a third wire from the low side of the signal source, as in Figure 8B. This wire assures a low common-mode voltage as well as providing the path for bias currents. Making the connection near the multiplexer will save wire, but it will also unbalance the line and reduce the amplifier's common-mode rejection. Differential Offset, ∆VOS There are two major sources of ∆VOS . That part due to the expression (rON ∆lD(ON) + lD(ON) ∆rON) becomes significant with increasing temperature, as shown in the Electrical Specifications tables. The other source of offset is the thermocouple effects due to dissimilar materials in the signal path. These include silicon, aluminum, tin, nickel-iron and (often) gold, just to exit the package. For the thermocouple effects in the package alone, the constraint on ∆VOS may be stated in terms of a limit on the difference in temperature for package pins leading to any channel of the Hl-539. For example, a difference of 0.13oC produces a 5µV offset. Obviously, this ∆T effect can dominate the ∆VOS parameter at any temperature unless care is taken in mounting the Hl-539 package. Temperature gradients across the Hl-539 package should be held to a minimum in critical applications. Locate the Hl539 far from heat producing components, with any air currents flowing lengthwise across the package. 9 HI-539 HI-539 rON “FLOATING” SOURCE rON + V+ V- FIGURE 8A. HI-539 rON rON + V+ V- 1M TO 10M POWER SUPPLY COMMON POWER SUPPLY COMMON NOTE: The amplifier in Figure 8A is unusable because its bias currents cannot return to the power supply. Figure 8B shows two alternative paths for these bias currents: either a pair of resistors, or (better) a third wire from the low side of the signal source. FIGURE 8B. 10 HI-539 Die Characteristics DIE DIMENSIONS: 92 mils x 100 mils METALLIZATION: Type: AlCu Thickness: 16kÅ ±2kÅ SUBSTRATE POTENTIAL (NOTE): -VSUPPLY PASSIVATION: Type: Nitride Over Silox Nitride Thickness: 3.5kÅ ±1kÅ Silox Thickness: 12kÅ ±2.0kÅ WORST CASE CURRENT DENSITY: 2.54 x 105 A/cm2 at 20mA TRANSISTOR COUNT: 236 PROCESS: CMOS-DI NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential. Metallization Mask Layout HI-539 V- EN A0 A1 GND V+ IN1A IN1B IN2A IN2B IN3A IN4A OUTA OUTB IN4B IN3B 11 HI-539 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.840 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 21.34 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94 α eA c1 D E e eA eA/2 L Q S1 e DS eA/2 c 0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 16 0.200 0.060 105o 0.015 0.030 0.010 0.0015 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 16 5.08 1.52 105o 0.38 0.76 0.25 0.038 aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. α aaa bbb ccc M N All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12