HI1-0549-2

® HI-546, HI-547, HI-548, HI-549 Data Sheet September 21, 2005 FN3150.5 Single 16 and 8, Differential 8-Channel and 4-Channel CMOS Analog MUXs with Active Overvoltage Protection The HI-546, HI-547, HI-548 and HI-549 are analog multiplexers with active overvoltage protection and guaranteed rON matching. Analog input levels may greatly exceed either power supply without damaging the device or disturbing the signal path of other channels. Active protection circuitry assures that signal fidelity is maintained even under fault conditions that would destroy other multiplexers. Analog inputs can withstand constant 70VP-P levels with ±15V supplies. Digital inputs will also sustain continuous faults up to 4V greater than either supply. In addition, signal sources are protected from short circuiting should multiplexer supply loss occur. Each input presents 1kΩ of resistance under this condition. These features make the HI-546, HI-547, HI-548 and HI-549 ideal for use in systems where the analog inputs originate from external equipment or separately powered circuitry. All devices are fabricated with 44V Dielectrically Isolated CMOS technology. The HI-546 is a single 16-Channel, the HI-547 is an 8-Channel differential, the HI-548 is a single 8-Channel and the HI-549 is a 4-Channel differential device. If input overvoltage protection is not needed the HI-506/507/508/509 multiplexers are recommended. For further information see Application Notes AN520 and AN521. For MIL-STD-883 compliant parts, request the HI-546/883, HI-547/883, HI-548/883 and HI-549/883 datasheets. Features • Analog Overvoltage Protection. . . . . . . . . . . . . . . . . . 70VP-P • No Channel Interaction During Overvoltage • Guaranteed rON Matching • Maximum Power Supply. . . . . . . . . . . . . . . . . . . . . . . 44V • Break-Before-Make Switching • Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . ±15V • Access Time (Typical) . . . . . . . . . . . . . . . . . . . . . . . 500ns • Standby Power (Typical). . . . . . . . . . . . . . . . . . . . . 7.5mW • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Data Acquisition • Industrial Controls • Telemetry 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HI-546, HI-547, HI-548, HI-549 Ordering Information PART NUMBER HI1-0546-5 HI1-0546-2 HI3-0546-5 HI4P0546-5 HI4P0546-5Z (Note) HI9P0546-9** PART MARKING HI1-546-5 HI1-546-2 HI3-546-5 HI4P546-5 HI4P546-5Z HI9P546-9 TEMP. RANGE (oC) 0 to 75 PACKAGE PKG. DWG. # Ordering Information (Continued) PART NUMBER HI9P0548-5** PART MARKING HI9P548-5 TEMP. RANGE (oC) 0 to 75 0 to 75 -40 to 85 -40 to 85 PACKAGE 16 Ld SOIC 16 Ld SOIC (Pb-free) 16 Ld SOIC 16 Ld SOIC (Pb-free) PKG. DWG. # M16.15 M16.15 M16.15 M16.15 28 Ld CERDIP F28.6 -55 to 125 28 Ld CERDIP F28.6 0 to 75 0 to 75 0 to 75 -40 to 85 -40 to 85 0 to 75 0 to 75 0 to 75 0 to 75 0 to 75 -40 to 85 -40 to 85 28 Ld PDIP 28 Ld PLCC 28 Ld PLCC (Pb-free) 28 Ld SOIC 28 Ld SOIC (Pb-free) E28.6 HI9P0548-5Z** HI9P548-5Z (Note) HI9P0548-9 HI9P548-9 HI9P548-9Z HI1-549-2 HI3-549-5 HI4P549-5 HI4P549-5Z HI9P549-9 HI9P549-9Z N28.45 N28.45 M28.3 HI3-0549-5 0 to 75 0 to 75 0 to 75 -40 to 85 -40 to 85 16 Ld PDIP 20 Ld PLCC 20 Ld PLCC (Pb-free) 16 Ld SOIC 16 Ld SOIC (Pb-free) E16.3 N20.35 N20.35 M16.15 M16.15 M28.3 HI4P0549-5 HI4P0549-5Z (Note) HI9P0549-9 HI9P0548-9Z (Note) HI1-0549-2 -55 to 125 16 Ld CERDIP F16.3 HI9P0546-9Z** HI9P546-9Z (Note) HI1-0547-5 HI3-0547-5 HI3-0547-5Z (Note) HI4P0547-5 HI4P0547-5Z (Note) HI9P0547-9 HI9P0547-9Z (Note) HI1-0548-2 HI1-0548-5 HI3-0548-5 HI4P0548-5 HI1-547-5 HI3-547-5 HI3-0547-5Z HI4P547-5 HI4P547-5Z HI9P547-9 HI9P547-9Z HI1-548-2 HI1-548-5 HI3-548-5 HI4P548-5 28 Ld CERDIP F28.6 28 Ld PDIP 28 Ld PDIP* (Pb-free) 28 Ld PLCC 28 Ld PLCC (Pb-free) 28 Ld SOIC 28 Ld SOIC (Pb-free) E28.6 E28.6 HI9P0549-9Z (Note) N28.45 N28.45 M28.3 M28.3 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. **Add “96” suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. -55 to 125 16 Ld CERDIP F16.3 0 to 75 0 to 75 0 to 75 16 Ld CERDIP F16.3 16 Ld PDIP 20 Ld PLCC E16.3 N20.35 Pinouts HI-546 (CERDIP, PDIP, SOIC) TOP VIEW +VSUPPLY 1 28 OUT 27 -VSUPPLY 26 IN 8 25 IN 7 24 IN 6 23 IN 5 22 IN 4 21 IN 3 20 IN 2 19 IN 1 18 ENABLE 17 ADDRESS A0 16 ADDRESS A1 15 ADDRESS A2 HI-547 (CERDIP, PDIP, SOIC) TOP VIEW +VSUPPLY 1 28 OUT A 27 -VSUPPLY 26 IN 8A 25 IN 7A 24 IN 6A 23 IN 5A 22 IN 4A 21 IN 3A 20 IN 2A 19 IN 1A 18 ENABLE 17 ADDRESS A0 16 ADDRESS A1 15 ADDRESS A2 NC 2 NC 3 IN 16 4 IN 15 5 IN 14 6 IN 13 7 IN 12 8 IN 11 9 IN 10 10 IN 9 11 GND 12 VREF 13 ADDRESS A3 14 OUT B 2 NC 3 IN 8B 4 IN 7B 5 IN 6B 6 IN 5B 7 IN 4B 8 IN 3B 9 IN 2B 10 IN 1B 11 GND 12 VREF 13 NC 14 2 HI-546, HI-547, HI-548, HI-549 Pinouts (Continued) HI-546 (PLCC) TOP VIEW +VSUPPLY -VSUPPLY HI-547 (PLCC) TOP VIEW +VSUPPLY -VSUPPLY 27 OUT B OUT A IN 8B IN 16 OUT IN 8 NC NC 4 3 2 1 28 27 26 4 3 2 1 28 IN 15 5 IN 14 6 IN 13 7 IN 12 8 IN 11 9 IN 10 10 IN 9 11 25 IN 7 24 IN 6 23 IN 5 22 IN 4 21 IN 3 20 IN 2 19 IN 1 IN 7B 5 IN 6B 6 IN 5B 7 IN 4B 8 IN 3B 9 IN 2B 10 IN 1B 11 IN 8A 26 NC 25 IN 7A 24 IN 6A 23 IN 5A 22 IN 4A 21 IN 3A 20 IN 2A 19 IN 1A 12 GND 13 VREF 14 A3 15 A2 16 A1 17 A0 18 ENABLE 12 GND 13 VREF 14 NC 15 A2 16 A1 17 A0 19 GND 13 IN 4B 18 ENABLE 18 +VSUPPLY 17 IN 1B 16 NC 15 IN 2B 14 IN 3B HI-548 (CERDIP, PDIP, SOIC) TOP VIEW A0 1 ENABLE 2 -VSUPPLY 3 16 A1 15 A2 14 GND 13 +VSUPPLY 12 IN 5 11 IN 6 10 IN 7 9 IN 8 HI-549 (CERDIP, PDIP, SOIC) TOP VIEW A0 1 ENABLE 2 -VSUPPLY 3 16 A1 15 GND 14 +VSUPPLY 13 IN 1B 12 IN 2B 11 IN 3B 10 IN 4B 9 OUT B IN 1 4 IN 2 5 IN 3 6 IN 4 7 OUT 8 IN 1A 4 IN 2A 5 IN 3A 6 IN 4A 7 OUT A 8 HI-548 (PLCC) TOP VIEW ENABLE ENABLE HI-549 (PLCC) TOP VIEW NC 1 11 NC A0 NC A0 A1 A2 3 2 1 20 19 -VSUPPLY 4 IN 1A 5 NC 6 IN 2A 7 IN 3A 8 3 2 20 -VSUPPLY 4 IN 1 5 NC 6 IN 2 7 IN 3 8 18 GND 17 +V SUPPLY 16 NC 15 IN 5 14 IN 6 IN 4A 9 IN 4 OUT A 3 OUT B 10 OUT 11 NC 12 IN 8 13 IN 7 9 10 12 A1 HI-546, HI-547, HI-548, HI-549 TRUTH TABLE HI-546 A3 X L L L L L L L L H H H H H H H H A2 X L L L L H H H H L L L L H H H H A1 X L L H H L L H H L L H H L L H H A0 X L H L H L H L H L H L H L H L H EN L H H H H H H H H H H H H H H H H “ON” CHANNEL None 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TRUTH TABLE HI-549 TRUTH TABLE HI-547 A2 X L L L L A1 X L L H H A0 X L H L H EN L H H H H “ON” CHANNEL PAIR None 1 2 3 4 A1 X L L H H A0 X L H L H EN L H H H H “ON” CHANNEL PAIR None 1 2 3 4 A2 X L L L L H H H H A1 X L L H H L L H H TRUTH TABLE HI-548 A0 X L H L H L H L H EN L H H H H H H H H “ON” CHANNEL None 1 2 3 4 5 6 7 8 A2 H H H H TRUTH TABLE HI-547 (Continued) A1 L L H H A0 L H L H EN H H H H “ON” CHANNEL PAIR 5 6 7 8 Functional Diagrams HI-546 1K IN 1 1K IN 2 DECODER/ DRIVER 1K IN 16 IN 8B IN 8A 1K IN 1B 1K DECODER/ DRIVER OUT IN 1A 1K OUT B 1K HI-547 OUT A OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 5V REF LEVEL SHIFT OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 5V REF LEVEL SHIFT † DIGITAL INPUT PROTECTION ††††† † DIGITAL INPUT PROTECTION † † † † VREF A0 A1 A2 A3 EN VREF A0 A1 A2 EN 4 HI-546, HI-547, HI-548, HI-549 Functional Diagrams (Continued) HI-548 1K IN 1 1K IN 2 DECODER/ DRIVER 1K IN 8 IN 4B IN 4A 1K IN 1B 1K OUT IN 1A 1K 1K HI-549 OUT A OUT B DECODER/ DRIVER OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 5V REF LEVEL SHIFT OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 5V REF LEVEL SHIFT † DIGITAL INPUT PROTECTION † † † † † DIGITAL INPUT PROTECTION † † † A0 A1 A2 EN A0 A1 EN Schematic Diagrams ADDRESS DECODER V+ P P P P P P P N A 0 O R A0 N N TO P-CHANNEL DEVICE OF THE SWITCH N A1 O R A1 N A2 O R A2 TO N-CHANNEL DEVICE OF THE SWITCH N A 3 O R A3 N ENABLE DELETE A3 OR A3 INPUT FOR HI-547, HI-548, HI-549 DELETE A2 OR A2 INPUT FOR HI-549 V- 5 HI-546, HI-547, HI-548, HI-549 Schematic Diagrams FROM DECODE OVERVOLTAGE PROTECTION N (Continued) MULTIPLEX SWITCH V+ P Q5 R11 1K IN D6 D7 D4 D5 N N OUT Q6 V- P FROM DECODE 6 HI-546, HI-547, HI-548, HI-549 Schematic Diagrams (Continued) ADDRESS INPUT BUFFER AND LEVEL SHIFTER TTL REFERENCE CIRCUIT V+ R10 R9 VREF Q1 Q4 D3 GND LEVEL SHIFTER V+ P P P P P P P P P OVERVOLTAGE PROTECTION V+ D2 P N R2 R5 R3 N N R4 R6 N N N N R8 N N R7 LEVEL SHIFTED ADDRESS TO DECODE R1 200 Ω D1 N GND V- VADD IN 7 HI-546, HI-547, HI-548, HI-549 Absolute Maximum Ratings V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44V V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+22V V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V Digital Input Voltage (VEN , VA) . . . . . . . . . . . . . (V-) -4V to (V+) +4V Analog Signal (VIN, VOUT). . . . . . . . . . . . . . . (V-) -20V to (V+) +20V or 20mA, Whichever Occurs First Continuous Current, IN or OUT . . . . . . . . . . . . . . . . . . . . . . . . 20mA Peak Current, IN or OUT (Pulsed 1ms, 10% Duty Cycle Max) . . 40mA Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) 16 Ld CERDIP Package . . . . . . . . . . . 85 32 28 Ld CERDIP Package . . . . . . . . . . . 55 18 28 Ld PDIP Package*. . . . . . . . . . . . . 60 N/A 16 Ld PDIP Package . . . . . . . . . . . . . 90 N/A 28 Ld PLCC Package . . . . . . . . . . . . . 70 N/A 20 Ld PLCC Package . . . . . . . . . . . . . 80 N/A 28 Ld SOIC Package . . . . . . . . . . . . . 75 N/A 16 Ld SOIC Package . . . . . . . . . . . . . 105 N/A Maximum Junction Temperature Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (PLCC, SOIC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Operating Conditions Temperature Ranges HI-546/548/549-2 . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HI-546/547/548/549-5 . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC HI-546/547/548/549-9 . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = 4V; VAL (Logic Level Low) = 0.8V; Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section TEST CONDITIONS TEMP (oC) -2 MIN TYP MAX MIN -5, -9 TYP MAX UNITS PARAMETER SWITCHING CHARACTERISTICS Access Time, tA 25 Full 25 50 - 0.5 80 300 300 1.2 3.5 68 10 1.0 500 1000 500 1000 - 25 50 - 0.5 80 300 300 1.2 3.5 68 10 1.0 1000 1000 - µs µs ns ns ns ns ns µs µs dB pF Break-Before Make Delay, tOPEN Enable Delay (ON), tON(EN) 25 25 Full Enable Delay (OFF), tOFF(EN) 25 Full Settling Time To 0.1% To 0.01% 25 25 25 25 Off Isolation Channel Input Capacitance, CS(OFF) Channel Output Capacitance CD(OFF) HI-546 HI-547 HI-548 HI-549 Input to Output Capacitance, CDS(OFF) DIGITAL INPUT CHARACTERISTICS Input Low Threshold, TTL Drive, VAL Input High Threshold, VAH (Note 8) MOS Drive, VAL (HI-546/547 Only) Note 6 25 25 25 25 25 - 52 30 25 12 0.1 - - 52 30 25 12 0.1 - pF pF pF pF pF Full Full VREF = 10V 25 4.0 - - 0.8 0.8 4.0 - - 0.8 0.8 V V V 8 HI-546, HI-547, HI-548, HI-549 Electrical Specifications Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = 4V; VAL (Logic Level Low) = 0.8V; Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section (Continued) TEST CONDITIONS VREF = 10V Note 5 TEMP (oC) 25 Full -2 MIN 6.0 TYP MAX 1.0 MIN 6.0 -5, -9 TYP MAX 1.0 UNITS V µA PARAMETER MOS Drive, VAH (HI-546/547 Only) Input Leakage Current (High or Low), IA ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, VIN On Resistance, rON ∆rON , (Any Two Channels) Off Input Leakage Current, IS(OFF) Full Note 2 25 Full 25 Note 3 25 Full -15 - 1.2 1.5 0.03 0.1 4.0 0.1 - +15 1.5 1.8 7.0 50 300 200 200 100 2.0 300 200 200 100 50 -15 - 1.5 1.8 0.03 0.1 4.0 0.1 - +15 1.8 2.0 7.0 50 300 200 200 100 300 200 200 100 50 V kΩ kΩ % nA nA nA nA nA nA nA nA µA nA nA nA nA nA nA Off Output Leakage Current, ID(OFF) HI-546 HI-547 HI-548 HI-549 ID(OFF) With Input Overvoltage Applied Note 3 25 Full Full Full Full Note 4 25 Full On Channel Leakage Current, ID(ON) HI-546 HI-547 HI-548 HI-549 Differential Off Output Leakage Current IDIFF (HI-547, HI-549 Only) POWER SUPPLY CHARACTERISTICS Power Dissipation, PD Current, I+ Current, INOTES: 2. VOUT = ±10V, IOUT = 100µA. Note 3 25 Full Full Full Full Full Full Note 7 Note 7 Full Full - 7.5 0.5 0.02 2.0 1.0 - 7.5 0.5 0.02 2.0 1.0 mW mA mA 3. 10nA is the practical lower limit for high speed measurement in the production test environments. 4. Analog Overvoltage = ±33V. 5. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at 25oC. 6. VEN = 0.8V, RL = 1K, CL = 15pF, VS = 7VRMS , f = 100kHz. 7. VEN , VA = 0V or 4V. 8. To drive from DTL/TTLCircuits, 1kΩ pull-up resistors to +5V supply are recommended. ± 9 HI-546, HI-547, HI-548, HI-549 Test Circuits and Waveforms TA = 25oC, VSUPPLY = ±15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified 100µA V2 IN OUT V2 100µA VIN rON = FIGURE 1A. ON RESISTANCE TEST CIRCUIT 1.4 NORMALIZED ON RESISTANCE (REFERRED TO VALUE AT ±15V) 2 4 6 8 10 1.3 ON RESISTANCE (kΩ) 1.2 1.1 25oC 1.0 0.9 0.8 0.7 0.6 -10 -8 -6 -4 -2 0 -55oC 125oC 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 5 6 7 8 9 10 11 12 13 14 15 ANALOG INPUT (V) SUPPLY VOLTAGE (±V) FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE FIGURE 1C. NORMALIZED ON RESISTANCE vs SUPPLY VOLTAGE FIGURE 1. ON RESISTANCE 100nA 10nA LEAKAGE CURRENT OFF OUTPUT CURRENT ID(OFF) EN OUT +0.8V ON LEAKAGE CURRENT ID(ON) 1nA A ID(OFF) 100pA OFF INPUT LEAKAGE CURRENT IS(OFF) 10pA 25 50 75 100 TEMPERATURE (oC) 125 FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE FIGURE 2B. ID(OFF) TEST CIRCUIT (NOTE 9) 10 ± ±10V 10V HI-546, HI-547, HI-548, HI-549 Test Circuits and Waveforms TA = 25oC, VSUPPLY = ±15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued) OUT A IS(OFF) EN ± 10V +0.8V EN OUT A ID(ON) FIGURE 2C. IS(OFF) TEST CIRCUIT (NOTE 9) NOTE: ± 9. Two measurements per channel: ±10V and FIGURE 2. LEAKAGE CURRENTS 18 OUTPUT OFF LEAKAGE CURRENT (nA) ANALOG INPUT CURRENT (mA) ANALOG INPUT CURRENT (IIN) 15 5 12 4 9 3 A IIN 6 OUTPUT OFF LEAKAGE CURRENT ID(OFF) 2 3 1 ±VIN 0 15 18 21 24 27 30 33 ANALOG INPUT OVERVOLTAGE (±V) 36 0 FIGURE 3A. ANALOG INPUT CURRENT AND OUTPUT OFF LEAKAGE CURRENT vs ANALOG INPUT OVER-VOLTAGE FIGURE 3B. TEST CIRCUIT FIGURE 3. ANALOG INPUT OVERVOLTAGE CHARACTERISTICS ±14 ±12 SWITCH CURRENT (mA) ±10 ±8 ±6 ±4 ±2 0 0 2 4 6 8 10 12 VOLTAGE ACROSS SWITCH (±V) 14 ±VIN A -55oC 25oC 125oC FIGURE 4A. ON CHANNEL CURRENT vs VOLTAGE FIGURE 4. ON CHANNEL CURRENT FIGURE 4B. TEST CIRCUIT 11 ± ± ±10V ±10V 10V 4V FIGURE 2D. ID(ON) TEST CIRCUIT (NOTE 9) 10V.) 10V. (Two measurements per device for ID(OFF): ±10V and A ID(OFF) HI-546, HI-547, HI-548, HI-549 Test Circuits and Waveforms 8 A SUPPLY CURRENT (mA) 6 A3 4 VSUPPLY = ± 15V VA VSUPPLY = ± 10V 2 +4V 50Ω A2 A1 A0 EN GND +15V/+10V +ISUPPLY TA = 25oC, VSUPPLY = ±15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued) V+ IN 1 HI-546 † IN 2 THRU IN 15 ±10V/±5V 10V/ 5V OUT VA 10MΩ 0 1K 10K 100K 1M 10M TOGGLE FREQUENCY (Hz) -ISUPPLY -15V/-10V † Similar connection for HI-547/HI-548/HI-549. FIGURE 5B. TEST CIRCUIT FIGURE 5. DYNAMIC SUPPLY CURRENT FIGURE 5A. SUPPLY CURRENT vs TOGGLE FREQUENCY 900 800 ACCESS TIME (ns) 700 600 500 +15V VA INPUT VREF = OPEN FOR LOGIC HIGH LEVEL < 62V/DIV. V VREF = LOGIC HIGH FOR LOGIC HIGH LEVELS > 6V S1 ON S16 ON 50Ω A3 A2 VA OUTPUT 0.5V/DIV. A1 A0 +4V EN GND VREF V+ IN 1 ±10V IN 2 THRU IN 15 ± HI-546 † IN 16 OUT V10kΩ 50pF 10V 400 300 3 4 5 6 8 7 9 10 11 LOGIC LEVEL (HIGH) (V) 12 13 14 15 100ns/DIV. -15V † Similar connection for HI-547/HI-548/HI-549. FIGURE 6B. TEST CIRCUIT FIGURE 6A. ACCESS TIME vs LOGIC LEVEL (HIGH) VAH = 4.0V 50% ADDRESS DRIVE (VA) 0V S1 ON VA INPUT 2V/DIV. +10V OUTPUT 10% tA OUTPUT 5V/DIV. -10V S16 ON 200ns/DIV. FIGURE 6C. MEASUREMENT POINTS FIGURE 6. ACCESS TIME FIGURE 6D. WAVEFORMS 12 ± ± IN 16 14pF HI-546, HI-547, HI-548, HI-549 Test Circuits and Waveforms A3 A2 HI-546 † IN 1 IN 2 THRU VA 50Ω A1 A0 +4V EN GND IN 15 IN 16 OUT 1kΩ 50pF 50% 50% VOUT 0V ADDRESS DRIVE (VA) TA = 25oC, VSUPPLY = ±15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued) +5V VAH = 4V OUTPUT tOPEN † Similar connection for HI-547/HI-548/HI-549 FIGURE 7A. TEST CIRCUIT FIGURE 7B. MEASUREMENT POINTS FIGURE 7C. WAVEFORMS FIGURE 7. BREAK-BEFORE-MAKE DELAY A3 A2 HI-546 † IN 1 +10V VAH = 4V 50% 50% ENABLE DRIVE (VA) 0V VOUT OUT GND 1kΩ 50pF 90% OUTPUT 10% 0V A1 A0 EN VA 50Ω IN 2 THRU IN16 t ON(EN) † Similar connection for HI-547/HI-548/HI-549 FIGURE 8A. TEST CIRCUIT t OFF(EN) FIGURE 8B. MEASUREMENT POINTS 13 HI-546, HI-547, HI-548, HI-549 Test Circuits and Waveforms TA = 25oC, VSUPPLY = ±15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued) ENABLE DRIVE 2V/DIV. DISABLED OUTPUT 2V/DIV. ENABLED (S1 ON) 100ns/DIV. FIGURE 8C. WAVEFORMS FIGURE 8. ENABLE DELAYS 14 HI-546, HI-547, HI-548, HI-549 Die Characteristics DIE DIMENSIONS: 83.9 mils x 159 mils METALLIZATION: Type: CuAl Thickness: 16kÅ ±2kÅ SUBSTRATE POTENTIAL (NOTE): -VSUPPLY PASSIVATION: Type: Nitride Over Silox Nitride Thickness: 3.5kÅ ±1kÅ Silox Thickness: 12kÅ ±2kÅ WORST CASE CURRENT DENSITY: 1.4 x 105 A/cm2 TRANSISTOR COUNT: 485 PROCESS: CMOS-DI NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential. Metallization Mask Layouts HI-546 EN (18) A0 (17) A1 A2 (16) (15) A3 VREF (14) (13) GND (12) EN (18) A0 (17) HI-547 A1 A2 (16) (15) NC VREF (14) (13) GND (12) IN 1 (19) IN 2 (20) IN 9 (11) IN 10 (10) IN 1A (19) IN 2A (20) IN 1B (11) IN 2B (10) IN 3 (21) IN 4 (22) IN 11 (9) IN 12 (8) IN 3A (21) IN 4A (22) IN 3B (9) IN 4B (8) IN 5 (23) IN 6 (24) IN 13 (7) IN 14 (6) IN 5A (23) IN 6A (24) IN 5B (7) IN 6B (6) IN 7 (25) IN 8 (26) IN 15 (5) IN 16 (4) IN 7A (25) IN 8A (26) IN 7B (5) IN 8B (4) V- (27) OUT (28) +V (1) NC (2) V- (27) OUT A (28) +V (1) OUT B(2) 15 HI-546, HI-547, HI-548, HI-549 Die Characteristics DIE DIMENSIONS: 83 mils x 108 mils METALLIZATION: Type: CuAl Thickness: 16kÅ ±2kÅ SUBSTRATE POTENTIAL (NOTE): -VSUPPLY PASSIVATION: Type: Nitride Over Silox Nitride Thickness: 3.5kÅ ±1kÅ Silox Thickness: 12kÅ ±2kÅ WORST CASE CURRENT DENSITY: 1.4 x 105 A/cm TRANSISTOR COUNT: 253 PROCESS: CMOS-DI NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential. Metallization Mask Layouts HI-548 IN 6 (11) IN 7 IN 8 (10) (9) OUT (8) IN 4 IN 3 (7) (6) IN 3B IN 4B OUT B (11) (10) (9) HI-549 OUT A (8) IN 4A IN 3A (7) (6) IN 5 (12) +V (13) GND (14) IN 2 (5) IN 1 (4) -V (3) IN 2B (12) IN 1B (13) +V (14) IN 2A (5) IN 1A (4) -V (3) A2 (15) A1 (16) A0 (1) EN (2) GND (15) A1 (16) A0 (1) EN (2) 16 HI-546, HI-547, HI-548, HI-549 17 HI-546, HI-547, HI-548, HI-549 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A) 28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.500 MAX 0.232 0.026 0.023 0.065 0.045 0.018 0.015 1.490 0.610 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 12.70 MAX 5.92 0.66 0.58 1.65 1.14 0.46 0.38 37.85 15.49 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94 α eA c1 D E e eA eA/2 L Q S1 e DS eA/2 c 0.100 BSC 0.600 BSC 0.300 BSC 0.125 0.015 0.005 90o 28 0.200 0.060 105o 0.015 0.030 0.010 0.0015 2.54 BSC 15.24 BSC 7.62 BSC 3.18 0.38 0.13 90o 28 5.08 1.52 105o 0.38 0.76 0.25 0.038 aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. α aaa bbb ccc M N 18 HI-546, HI-547, HI-548, HI-549 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E28.6 (JEDEC MS-011-AB ISSUE B) 28 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 3.18 0.356 0.77 0.204 35.1 0.13 15.24 12.32 MAX 6.35 4.95 0.558 1.77 0.381 39.7 15.87 14.73 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 1 12/00 MIN 0.015 0.125 0.014 0.030 0.008 1.380 0.005 0.600 0.485 MAX 0.250 0.195 0.022 0.070 0.015 1.565 0.625 0.580 A E A2 L A C L -AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A1 A2 -C- B B1 C D D1 E E1 e eA eB L N eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 0.100 BSC 0.600 BSC 0.115 28 0.700 0.200 2.54 BSC 15.24 BSC 2.93 28 17.78 5.08 19 HI-546, HI-547, HI-548, HI-549 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER C L 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP N28.45 (JEDEC MS-018AB ISSUE A) 0.004 (0.10) C 28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL A A1 MIN 0.165 0.090 0.485 0.450 0.191 0.485 0.450 0.191 28 MAX 0.180 0.120 0.495 0.456 0.219 0.495 0.456 0.219 MILLIMETERS MIN 4.20 2.29 12.32 11.43 4.86 12.32 11.43 4.86 28 MAX 4.57 3.04 12.57 11.58 5.56 12.57 11.58 5.56 NOTES 3 4, 5 3 4, 5 6 Rev. 2 11/97 0.025 (0.64) R 0.045 (1.14) D2/E2 C L E1 E D2/E2 VIEW “A” D D1 D2 E E1 E2 N D1 D 0.020 (0.51) MAX 3 PLCS A1 A 0.020 (0.51) MIN SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53) 0.045 (1.14) MIN VIEW “A” TYP. 0.025 (0.64) MIN NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. 20 HI-546, HI-547, HI-548, HI-549 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M28.3 (JEDEC MS-013-AE ISSUE C) 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 L MILLIMETERS MIN 2.35 0.10 0.33 0.23 17.70 7.40 MAX 2.65 0.30 0.51 0.32 18.10 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0926 0.0040 0.013 0.0091 0.6969 0.2914 MAX 0.1043 0.0118 0.0200 0.0125 0.7125 0.2992 B C D E α A1 0.10(0.004) C e H h L N 0.05 BSC 0.394 0.01 0.016 28 0o 8o 0.419 0.029 0.050 1.27 BSC 10.00 0.25 0.40 28 0o 10.65 0.75 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 21 HI-546, HI-547, HI-548, HI-549 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.840 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 21.34 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94 α eA c1 D E e eA eA/2 L Q S1 e DS eA/2 c 0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 16 0.200 0.060 105o 0.015 0.030 0.010 0.0015 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 16 5.08 1.52 105o 0.38 0.76 0.25 0.038 aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. α aaa bbb ccc M N 22 HI-546, HI-547, HI-548, HI-549 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E16.3 (JEDEC MS-001-BB ISSUE D) 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280 A E A2 L A C L -AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A1 A2 -C- B B1 C D D1 E eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). E1 e eA eB L N 0.100 BSC 0.300 BSC 0.115 16 0.430 0.150 2.54 BSC 7.62 BSC 2.93 16 10.92 3.81 23 HI-546, HI-547, HI-548, HI-549 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER C L 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP N20.35 (JEDEC MS-018AA ISSUE A) 0.004 (0.10) C 20 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL A A1 MIN 0.165 0.090 0.385 0.350 0.141 0.385 0.350 0.141 20 MAX 0.180 0.120 0.395 0.356 0.169 0.395 0.356 0.169 MILLIMETERS MIN 4.20 2.29 9.78 8.89 3.59 9.78 8.89 3.59 20 MAX 4.57 3.04 10.03 9.04 4.29 10.03 9.04 4.29 NOTES 3 4, 5 3 4, 5 6 Rev. 2 11/97 0.025 (0.64) R 0.045 (1.14) D2/E2 C L E1 E D2/E2 VIEW “A” D D1 D2 E E1 E2 N D1 D 0.020 (0.51) MAX 3 PLCS A1 A 0.020 (0.51) MIN SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53) 0.045 (1.14) MIN VIEW “A” TYP. 0.025 (0.64) MIN NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 24