HI1166-EV

CT UCT O DU RO D E PR ITUTE P er at T T OL E nt OBS LE SUBS port Ce om/tsc up IB l.c SS al S .intersi hnic A PO w FOR l our Tec L or ww SI cal T ER 8-IN 1-88 ® HI1166 August 2000 File Number 3579.5 8-Bit, 250 MSPS, Flash A/D Converter The HI1166 is an 8-bit, ultra high speed, flash Analog-toDigital converter IC capable of digitizing analog signals at a maximum rate of 250 MSPS. The digital I/O levels of the converter are compatible with ECL 100K/10KH/10K. Features • Differential Linearity Error . . . . . . . . . . . ±0.5 LSB or Less • Integral Linearity Error . . . . . . . . . . . . . . ±0.5 LSB or Less • Built-In Integral Linearity Compensation Circuit • Ultra High Speed Operation with Maximum Conversion Rate (Min) . . . . . . . . . . . . . . . . . . . 250 MSPS Applications • Spectrum Analyzers • Radar Systems • Direct RF Down-Conversion • Video Digitizing • Communication Systems • Digital Oscilloscopes • Low Input Capacitance 18pF (Typ) • Wide Analog Input Bandwidth (Min for Full Scale Input) . . . . . . . . . . . . . . . . . . . 250MHz • Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . . -5.2V • Low Power Consumption . . . . . . . . . . . . . . . 1.4W (Typ) Part Number Information PART NUMBER HI1166AIL HI1166-EV TEMP. RANGE (oC) -20 to 100 25 PACKAGE 68 Ld CLCC PKG. NO. J68.A • Low Error Rate • Capable of Driving 50Ω Loads • Evaluation Board Available • Direct Replacement for Sony CXA1166K Evaluation Board Pinout HI1166 (CLCC) TOP VIEW 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 NC 59 NC 58 AVEE 57 NC 56 AGND 55 VIN1 54 VIN1 53 AGND 52 VRM 51 AGND 50 VIN2 49 VIN2 48 AGND 47 NC 46 NC 45 NC 44 NC NC 10 NC D2 D2 D3 D3 DGND2 DGND2 DGND1 D4 D4 D5 D5 NC NC NC NC 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 NC AVEE AVEE VRBS NC AVEE 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved AGND NC DVEE D7 D7 MINV CLK CLK VRB D6 D6 AGND NC DVEE AVEE AVEE VRTS VRT NC AVEE OR OR LINV NC D1 D1 D0 D0 HI1166 Functional Block Diagram MINV R1 VRT 64 VRTS 65 R2 R 1 R 31 D7 (MSB) 2 R 32 D7 29 D6 63 VIN1 54 55 R 64 R 65 OUTPUT 30 D6 21 D5 22 D5 19 D4 20 D4 14 D3 R 126 R R3 R 128 R 129 127 ENCODE LOGIC 15 D3 12 D2 13 D2 6 D1 7 D1 4 D0 (LSB) 5 D0 R/2 0 2 OR 3 OR 33 COMPARATOR VRM 52 R 191 R VIN2 49 50 192 R 193 R 254 R VRBS 39 VRB 40 CLK 35 CLK 34 R5 CLOCK DRIVER 1 LINV R4 R/2 255 2 HI1166 Absolute Maximum Ratings TA = 25oC Supply Voltage (AV EE, DVEE). . . . . . . . . . . . . . . . . . . . -7V to +0.5V Analog Input Voltage (V IN) . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V Reference Input Voltage VRT, VRB, VRM . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V | VRT -VRB | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V Digital Input Voltage MINV, LINV, CLK, CLK . . . . . . . . . . . . . . . . . . . . . . . -4V to +0.5V | CLK-CLK | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V VRM Pin Input Current (IVRM) . . . . . . . . . . . . . . . . . . -3mA to +3mA Digital Output Current (ID0 to ID7, IOR, ID0 to ID7, IOR) . . . . . . . . . . . . . -30mA to 0mA Temperature Range, TA (Note 5) . . . . . . . . . . . . . . -20oC to 100oC TC . . . . . . . . . . . . . . . . . . . . . -20oC to 125oC Thermal Information Thermal Resistance (Typical, Note 2) θJAoC/W θJCoC/W CLCC Package . . . . . . . . . . . . . . . . . . 38 10 Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .2.1W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range (TSTG) . . . -65oC to 150oC Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC Operating Conditions (Note 1) Supply Voltage MIN AVEE , DVEE . . . . . . . . . . . . . . . . . . . . . . . -5.5V AVEE - DVEE . . . . . . . . . . . . . . . . . . . . . . -0.05V AGND - DGND . . . . . . . . . . . . . . . . . . . . . -0.05V TYP -5.2 0 0 MAX -4.95V 0.05V 0.05V Reference Input Voltage MIN TYP VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.1V -2 VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.2V -2 Analog Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . VRB MAX 0.1V -1.8V to VRT CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Electrical Specifications guaranteed within stated operating conditions. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL Differential Linearity Error, DNL DYNAMIC CHARACTERISTICS Signal to Noise Ratio, SINAD RMS Signal = ----------------------------------------------------------------RMS Noise + Distortion Error Rate TA = 25oC, AVEE = DVEE = - 5.2V, VRT , VRTS = 0V, VRB , VRBS = -2V (Note 1) TEST CONDITIONS MIN TYP MAX UNIT fC = 250 MSPS fC = 250 MSPS Input = 1kHz, Full Scale fC = 250MHz Input = 60kHz, Full Scale fC = 250MHz Input = 50MHz, Full Scale Error > 16 LSB, fC = 250MHz Input = 62.499MHz, Full Scale Error > 16 LSB, fC = 250MHz - 8 ±0.3 ±0.3 46 37 10-8 1.0 0.5 1.0 9 1.4 ±0.5 ±0.5 10-9 10-6 2.4 Bits LSB LSB 44 250 0.4 dB dB TPS (Note 3) TPS (Note 3) % Degree ns MSPS ps ns Differential Gain Error, DG Differential Phase Error, DP Overrange Recovery Time Maximum Conversion Rate, fC Aperture Jitter, tAJ Sampling Delay, tDS ANALOG INPUT Analog Input Capacitance, C IN Analog Input Resistance, RIN Input Bias Current, IIN Full Scale Input Bandwidth REFERENCE INPUTS Reference Resistance, RREF NTSC 40 IRE Mod. Ramp, fC = 250 MSPS VIN - 1V + 0.07VRMS VIN = -1V VIN = 2VP-P 50 20 200 18 120 250 450 - pF kΩ µA MHz Ω 83 125 182 3 HI1166 Electrical Specifications PARAMETER Residual Resistance R1 R2 R3 R4 R5 DIGITAL INPUTS Logic H Level, VIH Logic L Level, V IL Logic H Current, IIH Logic L Current, IIL Input Capacitance DIGITAL OUTPUTS Logic H Level, VOH Logic L Level, V OL TIMING CHARACTERISTICS H Pulse Width of Clock, tPW1 L Pulse Width of Clock, tPW0 Output Rise Time, tr Output Fall Time, tf Output Delay, tOD POWER SUPPLY CHARACTERISTICS Supply Current, IEE Power Consumption, PD NOTES: 1. Electrical Specifications guaranteed within stated operating conditions. 2. See Functional Block Diagram. 3. TPS: Times Per Sample. ( V RT – VRB ) 4. PD = I EEA • AVEE + I EED • DV EE + -----------------------------------R R EF 2 TA = 25oC, AVEE = DVEE = - 5.2V, VRT , VRTS = 0V, VRB , VRBS = -2V (Note 1) (Continued) TEST CONDITIONS Note 2 MIN 0.1 300 0.5 300 0.1 TYP 0.6 500 2.0 500 0.6 MAX 2.0 700 5.0 700 2.0 UNIT Ω Ω Ω Ω Ω V V µA µA pF V V -1.13 Input Connected to GND Input Connected to -2V 0 -50 RL = 50Ω RL = 50Ω -1.0 - 4 - -1.5 70 50 -1.6 1.8 1.8 RL = 50Ω RL = 50Ω RL = 50Ω 1.8 0.6 0.6 2.5 1.5 1.5 3.2 ns ns ns ns ns -360 Note 4 - -270 1.4 1.9 mA W 5. TA is specified in still air and without heat sink. To extend temperature range, appropriate heat management techniques must be employed (See Figure 2). Timing Diagram tSD ANALOG IN N N+1 N+2 tPW1 CLK CLK DIGITAL OUT tOD N-1 20% 80% tr N 80% N+1 20% tf tPW0 FIGURE 1. 4 HI1166 Typical Performance Curves 50 THERMAL RESISTANCE θJA (oC/W) 25 40 SOCKET AMP: 173061-5 (WITHOUT HEAT SINK) INPUT CAPACITANCE (pF) 20 SOCKET AMP: 173257-3 (WITH HEAT SINK) 30 SOCKET: YAMAICHI ELECTRONICS CO., LTD IC61-0684-048 0 1.0 2.0 AIR FLOW (m/s) 3.0 15 10 -2.0 -1.5 -1.0 INPUT VOLTAGE (V) -0.5 0 FIGURE 2. THERMAL RESISTANCE OF THE CONVERTER MOUNTED ON A BOARD FIGURE 3. VIN PIN CAPACITANCE vs VOLTAGE CHARACTERISTICS 150 ANALOG INPUT RESISTANCE (kΩ) 200 125 IIN (µA) 100 10 -2.0 100 -1.5 -1.0 INPUT VOLTAGE (V) -0.5 0 0 -2.0 -1.5 -1.0 INPUT VOLTAGE (V) -0.5 0 FIGURE 4. VIN PIN INPUT RESISTANCE vs VOLTAGE CHARACTERISTICS 200 FIGURE 5. VIN PIN INPUT CURRENT vs VOLTAGE CHARACTERISTICS -12 RESISTOR STRING CURRENT (mA) 0 50 100 150 -14 150 INPUT CURRENT (µA) -16 -18 -20 -22 -24 100 50 0 -50 CASE TEMPERATURE (oC) -50 0 50 100 150 CASE TEMPERATURE (oC) FIGURE 6. VIN PIN INPUT CURRENT vs TEMPERATURE CHARACTERISTICS FIGURE 7. RESISTOR STRING CURRENT vs TEMPERATURE CHARACTERISTICS 5 HI1166 Typical Performance Curves -1.25 (Continued) -0.7 CLK OPEN VOLTAGE (V) -1.30 -0.8 -1.35 VOH (V) -50 0 50 100 150 -0.9 -1.40 -1.0 -1.45 -1.1 -50 0 50 100 150 CASE TEMPERATURE (oC) CASE TEMPERATURE (oC) FIGURE 8. CLK OPEN VOLTAGE vs TEMPERATURE CHARACTERISTICS -1.7 FIGURE 9. VOH vs TEMPERATURE CHARACTERISTICS 50 -1.8 SINAD (dB) 45 VOL (V) 40 -1.9 35 -2.0 30 -2.1 -50 0 50 100 150 25 1 10 INPUT FREQUENCY (MHz) 100 CASE TEMPERATURE (oC) FIGURE 10. VOL vs TEMPERATURE CHARACTERISTICS FIGURE 11. SINAD vs INPUT FREQUENCY RESPONSE CHARACTERISTICS HIGH FREQUENCY DISTORTION (dB) CLOCK FREQUENCY = 250MHz -30 -40 -50 -60 -70 -80 0.1 SECOND HARMONIC THIRD HARMONIC CLK (MHz) 300 250 200 150 ERROR RATE = 10-8 TPS INPUT FREQUENCY = CLOCK FREQUENCY/4 - 1kHz ERROR RATE > 16 LSB 1 10 100 1000 -25 25 75 125 INPUT FREQUENCY (MHz) AMBIENT TEMPERATURE (oC) FIGURE 12. HARMONIC DISTORTION vs INPUT FREQUENCY RESPONSE CHARACTERISTICS FIGURE 13. MAXIMUM CONVERSION RATE vs TEMPERATURE CHARACTERISTICS 6 HI1166 Typical Performance Curves (Continued) INPUT = 125MHz, FULL SCALE CLK = 250MHz, ERROR RATE > 16 LSB ERROR RATE (TPS) 200 250 300 10 -7 ERROR RATE (TPS) INPUT FREQUENCY = CLOCK FREQUENCY/4 - 1kHz ERROR RATE > 16 LSB 10-7 10 -8 10 -9 10-8 10 -10 CLOCK FREQUENCY (MHz) 10-9 25 30 35 50 40 45 55 CLK DUTY CYCLE (%) 60 65 70 FIGURE 14. ERROR RATE vs CONVERSION RATE -200 FIGURE 15. ERROR RATE vs CLOCK DUTY CYCLE SUPPLY CURRENT (mA) -250 -300 -350 -50 0 50 100 150 CASE TEMPERATURE (oC) FIGURE 16. SUPPLY CURRENT vs TEMPERATURE CHARACTERISTICS Pin Descriptions PIN NUMBER 4, 5 6, 7 12, 13 14, 15 19, 20 21, 22 29, 30 31, 32 2, 3 SYMBOL D0, D0 D1, D1 D2, D2 D3, D3 D4, D4 D5, D5 D6, D6 D7, D7 OR, OR DVEE 8 28 Di Di I/O O STANDARD VOLTAGE LEVEL ECL EQUIVALENT CIRCUIT DGND2 16 DESCRIPTION LSB and complementary LSB output. D1 to D6: Data Output. D1 to D6: Complementary Data Output. MSB Complementary MSB Data Output. Overrange and Complementary Overrange Output. 7 HI1166 Pin Descriptions PIN NUMBER 1 SYMBOL LINV (Continued) I/O I STANDARD VOLTAGE LEVEL ECL EQUIVALENT CIRCUIT DGND1 18 DESCRIPTION Polarity selection for LSBs (refer to the A/D Output Code Table.) Pulled low when left open. 33 MINV I ECL R R R LINV 1 OR MINV 33 R 8 DVEE 28 -1.3V Polarity selection for MSB (refer to the A/D Output Code Table). Pulled low when left open. 35 34 CLK CLK I I ECL ECL DGND1 18 R R CLK 35 34 CLK DVEE 8 28 R R R R CLK Input. Complementary CLK Input. Pulled down to -1.3V when left open. 64 65 52 39 40 VRT VRTS VRM V RBS V RB I O I O I 0V 0V VRB/2 -2V VRT 64 VRTS 65 R2 R1 Analog Reference Voltage (Top) (0V Typ). Reference Voltage Sense (Top). Reference Voltage Mid Point. Can be used for linearity compensation. Reference Voltage Sense (Bottom). Analog Reference Voltage (Bottom). R3 R TO COMPARATORS R/2 R -2V VRM 52 R VRBS 39 VRB 40 R/2 R4 R5 8 HI1166 Pin Descriptions PIN NUMBER 49, 50 54, 55 SYMBOL VIN2 VIN1 (Continued) I/O I STANDARD VOLTAGE LEVEL VRTS to VRBS VIN2 49 50 54 55 VIN1 TO COMP. 128 TO 255 0 TO 127 EQUIVALENT CIRCUIT 43, 48, 51, 53, 56, 61 DESCRIPTION Analog Input. All of the pins must be wired externally. AGND 43, 48, 51, 53, 56, 61 37, 38, 42, 58, 62, 66, 67 18 16, 17 8, 28 AGND AVEE 0V 61 AGND 48 51 53 56 DGND1 18 DGND2 16 17 Analog ground. Analog supply. Internally connected to DVEE (resistance: 4Ω to 6Ω). -5.2V 43 DGND1 DGND2 DVEE 0V 0V -5.2V INTERNAL ANALOG CIRCUIT INTERNAL DIGITAL CIRCUIT 4Ω TO 6Ω D1 D1 8 28 DVEE Digital ground. Digital ground for output drive. Digital supply. Internally connected to AVEE (resistance: 4Ω to 6Ω). 42 62 37 38 58 66 AVEE 67 TABLE 1. A/D OUTPUT CODE VIN (NOTE 6) 0V 0 1 STEP OR 0 1 1 MINV 1, LINV 1 D7 D0 000 • • • • • 00 000 • • • • • 00 000 • • • • • 01 • • • 011 • • • • • 11 100 • • • • • 00 • • • 111 • • • • • 10 111 • • • • • 11 111 • • • • • 11 OR 0 1 1 0, 1 D7 D0 OR 0 1 1 1, 0 D7 D0 OR 0 1 1 0, 0 D0 D7 -1V 127 128 1 1 1 1 254 255 -2V NOTE: 1 1 1 1 1 1 100 • • • • • 00 100 • • • • • 00 100 • • • • • 01 • • • 111 • • • • • 11 000 • • • • • 00 • • • 011 • • • • • 10 011 • • • • • 11 011 • • • • • 11 1 1 1 1 1 011 • • • • • 11 011 • • • • • 11 011 • • • • • 10 • • • 000 • • • • • 00 111 • • • • • 11 • • • 100 • • • • • 01 100 • • • • • 00 100 • • • • • 00 1 1 1 1 1 111 • • • • • 11 111 • • • • • 11 111 • • • • • 10 • • • 100 • • • • • 00 011 • • • • • 11 • • • 000 • • • • • 01 000 • • • • • 00 000 • • • • • 00 6. VRT = VRTS = 0V, VRM = - 1V or open, VRB = VRBS = -2V. 9 HI1166 Test Circuits and Waveforms FUNC. GENERATOR 100 DUT HI1166 CLK CLK 8 110 ECL LATCH 100 8 110 21 -4.5V SG (CW) 50 DUTY DIVIDER SWITCH POSITION 1. MAXIMUM CONVERSION RATE 2. DG/DP VECTOR SCOPE DG/DP OSCILLOSCOPE MAXIMUM CONVERSION RATE HI20201 10-BIT D/A AMP fms 0V -2V 1 2 NTSC SIGNAL SOURCE AMP VIN 2Ω FIGURE 17. MAXIMUM CONVERSION RATE TEST CIRCUIT +V S2 + S1 S1 : A < B : ON S2 : A > B : ON -V AB 8 COMPARATOR A8 TO A1 A0 B8 TO B1 B0 BUFFER DVM CLK (250MHz) “0” “1” 8 000 • • • 00 TO 111 • • • 10 CONTROLLER FIGURE 18. INTEGRAL AND DIFFERENTIAL LINEARITY ERROR TEST CIRCUIT 10 HI1166 Test Circuits and Waveforms (Continued) IIN A -1V 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 -2V HI1166 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A IEEA -5.2V A IEED -5.2V FIGURE 19. POWER SUPPLY AND ANALOG INPUT BIAS CURRENT TEST CIRCUIT VIN 0V -1V -2V CLK VIN 60MHz OSC1 φ: VARIABLE fR AMP CLK HI1166 CLK OSC2 60MHz ECL BUFFER 8 LOGIC ANALYZER 1024 SAMPLES ∆υ ∆t t 129 128 127 126 125 σ (LSB) VIN APERTURE JITTER APERTURE JITTER IS DEFINED AS FOLLOWS: ∆υ 256 t = σ ⁄ ------ = σ ⁄ --------- × 2 π f AJ ∆t 2 Where σ (unit: LSB) is the deviation of the output codes when the input frequency is exactly the same as the clock and is sampled at the largest slew rate point. FIGURE 20A. FIGURE 20B. APERTURE JITTER TEST METHOD FIGURE 20. SAMPLING DELAY AND APERTURE JITTER TEST CIRCUIT 11    