HI1171

HI1171 August 1997 8-Bit, 40 MSPS, High Speed D/A Converter Description The HI1171 is an 8-bit, 40MHz, high speed D/A converter. The converter incorporates an 8-bit input data register with blanking capability, and current outputs. The HI1171 features low glitch outputs. The architecture is a current cell arrangement to provide low linearity errors. The HI1171 is available in an Industrial temperature range and is offered in a 24 lead (200 mil) SOIC plastic package. For dual version, please refer to the HI1177 Data Sheet. For triple version, please refer to the HI1178 Data Sheet. Features • Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . . 40MHz • Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit • Integral Linearity Error . . . . . . . . . . . . . . . . . . 0.25 LSB • Low Glitch Noise • Single Supply Operation . . . . . . . . . . . . . . . . . . . . . . +5V • Low Power Consumption (Max) . . . . . . . . . . . . . .80mW • Evaluation Board Available (HI1171-EV) • Direct Replacement for the Sony CXD1171 Ordering Information PART NUMBER HI1171JCB HI1171-EV TEMP. RANGE (oC) -40 to 85 25 PACKAGE 24 Ld SOIC PKG. NO. M24.2-S Applications • Wireless Telecommunications • Signal Reconstruction • Direct Digital Synthesis • Imaging • Presentation and Broadcast Video • Graphics Displays • Signal Generators Evaluation Board Pinout HI1171 (SOIC) TOP VIEW Typical Application Circuit +5V 0.1µF 24 DVDD 23 DVDD 22 AVDD 21 IOUT2 20 IOUT1 19 AVDD 18 AVDD 17 VG 16 VREF 15 IREF 14 AVSS 13 DVSS 0.1µF D7 D6 D5 D4 D3 D2 D1 D0 DVDD (23, 24) (18, 19, 22) AVDD D7 (MSB)(8) D6 (7) D5 (6) D4 (5) D3 (4) D2 (3) D1 (2) D0 (LSB) (1) CLK (12) VB (11) BLNK (9) DVSS (10, 13) (15) IREF 3.3kΩ (21) IOUT2 (14) AVSS (20) IOUT1 200Ω D/A OUT (17) VG (16) VREF 0.1µF 1kΩ HI1171 +5V 0.1µF (LSB) D0 D1 D2 D3 D4 D5 D6 D7 BLNK 1 2 3 4 5 6 7 8 9 DVSS 10 VB CLK 11 12 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 File Number 3662.2 1 HI1171 Functional Block Diagram (LSB) D0 D1 D2 D3 D4 DECODER 8-BIT LATCH 6 MSBs CURRENT CELLS 2 LSBs CURRENT CELLS IOUT2 IOUT1 D5 DECODER VG D6 (MSB) D7 BLNK CURRENT CELLS (FOR FULL SCALE) + - VREF IREF VB CLK CLOCK GENERATOR BIAS VOLTAGE GENERATOR 2 HI1171 Absolute Maximum Ratings Digital Supply Voltage DVDD to DVSS . . . . . . . . . . . . . . . . . . . +7.0V Analog Supply Voltage AVDD to AVSS . . . . . . . . . . . . . . . . . . +7.0V Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS V Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0mA to 15mA Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Maximum Junction Temperature, Plastic Package . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER SYSTEM PERFORMANCE Resolution, n Integral Linearity Error, INL Differential Linearity Error, DNL Offset Error, VOS AVDD = +4.75V to +5.25V, DVDD = +4.75 to +5.25V, VREF = +2.0V, fS = 40MHz, CLK Pulse Width = 12.5ns, TA = 25oC (Note 4) TEST CONDITIONS MIN TYP MAX UNITS fS = 40MHz (End Point) fS = 40MHz (Note 2) (Note 2) -0.5 1.9 0.5 8 10 2.0 2.0 1.3 ±0.25 1 ±13 15 2.1 2.1 Bits LSB LSB mV LSB mA V V Full Scale Error, FSE (Adjustable to Zero) Full Scale Output Current, IFS Full Scale Output Voltage, VFS Output Voltage Range, VFSR DYNAMIC CHARACTERISTICS Throughput Rate Glitch Energy, GE Differential Gain, ∆AV (Note 3) Differential Phase, ∆φ (Note 3) REFERENCE INPUT Voltage Reference Input Range Reference Input Resistance DIGITAL INPUTS Input Logic High Voltage, VIH Input Logic Low Voltage, VIL Input Logic Current, IIL, IIH Digital Input Capacitance, CIN TIMING CHARACTERISTICS Data Setup Time, tSU Data Hold Time, tHLD See Figure 7 ROUT = 75Ω 40.0 - 30 1.2 0.5 - MHz pV-s % Degree 0.5 (Note 3) 1.0 - 2.0 - V MΩ (Note 3) (Note 3) (Note 3) (Note 3) 3.0 - 5.0 1.5 ±5.0 - V V µA pF See Figure 1 See Figure 1 5 10 - - ns ns 3 HI1171 Electrical Specifications PARAMETER Propagation Delay Time, tPD Settling Time, tSET (to 1/2 LSB) CLK Pulse Width, tPW1, tPW2 POWER SUPPLY CHARACTERISITICS IAVDD IDVDD Power Dissipation NOTES: 2. Excludes error due to external reference drift. 3. Parameter guaranteed by design or characterization and not production tested. 4. Electrical specifications guaranteed only under the stated operating conditions. 14.3MHz, at Color Bar Data Input 14.3MHz, at Color Bar Data Input 200Ω load at 2VP-P Output 10.9 4.2 11.5 4.8 80 mA mA mW AVDD = +4.75V to +5.25V, DVDD = +4.75 to +5.25V, VREF = +2.0V, fS = 40MHz, CLK Pulse Width = 12.5ns, TA = 25oC (Note 4) (Continued) TEST CONDITIONS See Figure 9 See Figure 1 See Figure 1 MIN 12.5 TYP 10 10 MAX 15 UNITS ns ns ns Timing Diagram tPW1 tPW2 CLK tSU tHLD DATA tSU tHLD tSU tHLD tPD 100% D/AOUT 50% tPD tPD 0% FIGURE 1. 4 HI1171 Typical Performance Curves OUTPUT FULL SCALE VOLTAGE (V) 200 2 GLITCH ENERGY (pV/s) VDD = 5.0V, R = 200Ω 16R = 3.3kΩ , TA = 25oC 1 REFERENCE VOLTAGE (V) 2 100 OUTPUT RESISTANCE (Ω) 200 OUTPUT FULL SCALE VOLTAGE (V) 2.0 1.9 VDD = 5.0V, VREF = 2.0V R = 200Ω, 16R = 3.3kΩ TA = 25oC 0 -25 0 25 50 75 AMBIENT TEMPERATURE (oC) 100 1 FIGURE 2. OUTPUT FULL SCALE VOLTAGE vs REFERENCE VOLTAGE FIGURE 3. OUTPUT RESISTANCE vs GLITCH ENERGY FIGURE 4. OUTPUT FULL SCALE VOLTAGE vs AMBIENT TEMPERATURE Pin Descriptions 24 PIN SOIC 1-8 PIN NAME D0(LSB) thru D7(MSB) BLNK PIN DESCRIPTION Digital Data Bit 0, the Least Significant Bit thru Digital Data Bit 7, the Most Significant Bit. 9 Blanking Line, used to clear the internal data register to the zero condition when High, normal operation when Low. Digital Ground. Voltage Bias, connect a 0.1µF capacitor to DVSS . Data Clock Pin 100kHz to 40MHz. Analog Ground. Current Reference, used to set the current range. Connect a resistor to AVSS that is 16 times greater than the resistor on IOUT1 . (See Typical Applications Circuit). Input Reference Voltage used to set the output full scale range. 10, 13 11 12 14 15 DVSS VB CLK AVSS IREF VREF 16 5 HI1171 Pin Descriptions 24 PIN SOIC 17 18, 19, 22 20 21 23, 24 PIN NAME VG AVDD IOUT1 IOUT2 DVDD (Continued) PIN DESCRIPTION Voltage Ground, connect a 0.1µF capacitor to AVDD . Analog Supply 4.75V to 7V. Current Output Pin. Current Output pin used for a virtual ground connection. Usually connected to AVSS. Digital Supply 4.75V to 7V. Detailed Description The HI1171 is an 8-bit, current out D/A converter. The DAC can convert at 40MHz and run on a single +5V supply. The architecture is an encoded, switched current cell arrangement. Voltage Output Mode The output current of the HI1171 can be converted into a voltage by connecting an external resistor to IOUT1 . To calculate the output resistor use the following equation: ROUT = VFS / IFS , where VFS can range from +0.5V to +2.0V and IFS can range from 0mA to 15mA. In setting the output current the IREF pin should have a resistor connected to it that is 16 times greater than the output resistor: RREF = 16 x ROUT As the values of both ROUT and RREF increase, power consumption is decreased, but glitch energy and output settling time is increased. Clock Phase Relationship The internal latch is closed when the clock line is high. The latch can be cleared by the BLNK line. When BLNK is set (HIGH) the contents of the internal data latch will be cleared. When BLNK is low data is updated by the CLK. Noise Reduction To reduce power supply noise separate analog and digital power supplies should be used with 0.1µF ceramic capacitors placed as close to the body of the HI1171 as possible. The analog (AVSS) and digital (DVSS) ground returns should be connected together back at the power supply to ensure proper operation from power up. Test Circuits (LSB) D0 1 8-BIT COUNTER WITH LATCH D7 8 BLK 9 0.1µF VB CLK 40MHz SQUARE WAVE CLK 11 15 12 3.3kΩ 16 20 2 VG 17 0.1µF VREF 2V IREF AVSS 1kΩ AVDD 200Ω IO OSCILLOSCOPE FIGURE 5. MAXIMUM CONVERSION SPEED TEST CIRCUIT All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 6 HI1171 Test Circuits (Continued) (LSB) D0 1 20 CONTROLLER D7 8 BLK 9 0.1µF VB CLK 11 15 12 3.3kΩ 16 2 VG 17 0.1µF VREF 2V IREF AVSS 1kΩ AVDD 200Ω IO DVM CLK 40MHz SQUARE WAVE FIGURE 6. DC CHARACTERISTICS TEST CIRCUIT (LSB) D0 1 20 2 VG D7 8 BLK FREQUENCY DEMULTIPLIER 9 0.1µF VB CLK 11 15 12 3.3kΩ 16 17 0.1µF VREF 2V IREF AVSS 1kΩ AVDD 200Ω IO OSCILLOSCOPE CLK 10MHz SQUARE WAVE FIGURE 7. PROPAGATION DELAY TIME TEST CIRCUIT (LSB) D0 1 8-BIT COUNTER WITH LATCH D7 8 BLK 9 DELAY CONTROLLER CLK 1MHz SQUARE WAVE 0.1µF VB DELAY CONTROLLER CLK 11 15 12 1.2kΩ 16 20 2 VG 17 0.1µF VREF 2V IREF 1kΩ AVSS AVDD 75Ω IO OSCILLOSCOPE FIGURE 8. SET UP HOLD TIME AND GLITCH ENERGY TEST CIRCUIT 7