HI1175-EV

® R a nd Data-Free Sheet Pb o HS Co a nt mpli HI1175 October 25, 2005 FN3577.8 8-Bit, 20MSPS, Flash A/D Converter The HI1175 is an 8-bit, analog-to-digital converter built in a 1.4µm CMOS process. The low power, low differential gain and phase, high sampling rate, and single 5V supply make the HI1175 ideal for video and imaging applications. The adoption of a 2-step flash architecture achieves low power consumption (60mW) at a maximum conversion speed of 20MSPS (Min), 35MSPS typical with only a 2.5 clock cycle data latency. The HI1175 also features digital output enable/disable and a built in voltage reference. The HI1175 can be configured to use the internal reference or an external reference if higher precision is required. Features • Resolution . . . . . . . . . . . . . . . . . . . . 8-Bit ±0.3 LSB (DNL) • Maximum Sampling Frequency . . . . . . . . . . . . . . 20MSPS • Low Power Consumption . . . . . . 60mW (at 20MSPS Typ) (Reference Current Excluded) • Built-In Sample and Hold Circuit • Built-In Reference Voltage Self Bias Circuit • Three-State TTL Compatible Output • Single +5V Power Supply • Low Input Capacitance. . . . . . . . . . . . . . . . . . . 11pF (Typ) Ordering Information PART NUMBER HI1175JCB HI1175-EV TEMP. RANGE (oC) -40 to 85 25 PACKAGE 24 Ld SOIC Evaluation Board PKG. NO. M24.2-S • Reference Impedance . . . . . . . . . . . . . . . . . . . 300Ω (Typ) • Evaluation Board Available (HI1175-EV) • Low Cost • Direct Replacement for the Sony CXD1175 Applications • Video Digitizing • PC Video Capture • Image Scanners • TV Set Top Boxes • Multimedia • Personal Communication Systems (PCS) Pinout HI1175 (SOIC) TOP VIEW OE DVSS D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) DVDD CLK 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 DVSS VRB VRBS AVSS AVSS VIN AVDD VRT VRTS AVDD AVDD DVDD 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2000, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HI1175 Functional Block Diagram 1 2 3 4 5 6 7 8 9 UPPER DATA LATCHES LOWER DATA LATCHES LOWER ENCODER (4-BIT) LOWER COMPARATORS WITH S/H (4-BIT) REFERENCE VOLTAGE 24 DVSS 23 VRB 22 VRBS 0.6V (Typ) OE DVSS D0 (LSB) D1 D2 D3 D4 D5 D6 21 AVSS 20 AVSS LOWER ENCODER (4-BIT) LOWER COMPARATORS WITH S/H (4-BIT) 19 VIN 18 AVDD 17 VRT D7 (MSB) 10 DVDD 11 CLK 12 CLOCK GENERATOR UPPER ENCODER (4-BIT) UPPER COMPARATORS WITH S/H (4-BIT) 16 VRTS 2.6V (Typ) 15 AVDD 14 AVDD 13 DVDD Typical Application Schematic HC04 CA158A R4 + R11 R3 R5 + CA158A C12 0.1µF HA2544 VIN + R2 C8 † 15 16 17 18 HI1175 19 20 R1 21 22 23 C11 0.1µF C7 4.7µF + 24 6 5 4 3 2 1 D3 D2 D1 D0 (LSB) 10 9 8 7 D7 (MSB) D6 D5 D4 R13 C9 + 4.7µF C10 0.1µF 13 14 12 11 +5V CLOCK IN CLK +5V ICL8069 R12 † : Ceramic Chip Capacitor 0.1µF. : Analog GND. : Digital GND. +5V NOTE: It is necessary that AVDD and DVDD pins be driven from the same supply. The gain of analog input signal can be changed by adjusting the ratio of R2 to R1. 2 HI1175 Pin Descriptions and Equivalent Circuits PIN NUMBER 1 SYMBOL OE EQUIVALENT CIRCUIT DVDD DESCRIPTION When OE = Low, Data is valid. When OE = High, D0 to D7 pins high impedance. 1 DVSS 2, 24 3-10 DVSS D0 to D7 Digital GND. D0 (LSB) to D7 (MSB) Output. D1 11, 13 12 DVDD CLK DVDD Digital +5V. Clock Input. 12 DVSS 16 VRTS AVDD Shorted with VRT generates, +2.6V. 16 17 23 VRT VRB 17 AVDD Reference Voltage (Top). Reference Voltage (Bottom). 23 AVSS 14, 15, 18 19 AVDD VIN AVDD Analog +5V. Analog Input. 19 AVSS 20, 21 22 AVSS VRBS AVSS Analog GND. Shorted with VRB generates +0.6V. 22 3 HI1175 Absolute Maximum Ratings Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Reference Voltage, VRT, VRB . . . . . . . . . . . . . . . . . . . . VDD to VSS Analog Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS Digital Input Voltage, CLK . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS Digital Output Voltage, VOH, VOL . . . . . . . . . . . . . . . . . VDD to VSS Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range, TSTG . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions (Note 1) Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC Supply Voltage AVDD , AVSS , DVDD , DVSS . . . . . . . . . . . . . . . . +4.75V to +5.25V |DGND-AGND|. . . . . . . . . . . . . . . . . . . . . . . . . . . . 0mV to 100mV Reference Input Voltage VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V and Above VRT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8V and Below Analog Input Range, VIN . . . . . . . VRB to VRT (1.8VP-P to 2.8VP-P) Clock Pulse Width tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min) tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER SYSTEM PERFORMANCE Offset Voltage EOT EOB Integral Non-Linearity, INL Differential Non-Linearity, DNL DYNAMIC CHARACTERISTICS Effective Number of Bits, ENOB Spurious Free Dynamic Range Signal to Noise Ratio, SINAD RMS Signal = ----------------------------------------------------------------RMS Noise + Distortion Maximum Conversion Speed, fC Minimum Conversion Speed Differential Gain Error, DG Differential Phase Error, DP Aperture Jitter, tAJ Sampling Delay, tDS Data Latency, tLAT ANALOG INPUTS fC = 20 MSPS, VDD = +5V, VRB = 0.5V, VRT = 2.5V, TA = 25oC (Note 1) TEST CONDITIONS MIN TYP MAX UNIT -60 0 fC = 20 MSPS, VIN = 0.6V to 2.6V fC = 20 MSPS, VIN = 0.6V to 2.6V - -35 +15 ±0.5 ±0.3 -10 +45 ±1.3 ±0.5 mV mV LSB LSB fIN = 1MHz fIN = 1MHz fC = 20MHz, fIN = 1MHz fC = 20MHz, fIN = 3.58MHz VIN = 0.6V to 2.6V, fIN = 1kHz Ramp 20 - 7.6 51 46 46 35 1.0 0.5 30 4 - 0.5 2.5 Bits dB dB dB MSPS MSPS % Degree ps ns Cycles NTSC 40 IRE Mod Ramp, fC = 14.3 MSPS - Analog Input Bandwidth (-1dB), BW Analog Input Capacitance, CIN VIN = 1.5V + 0.07VRMS - 18 11 - MHz pF 4 HI1175 Electrical Specifications PARAMETER REFERENCE INPUT Reference Pin Current, IREF Reference Resistance (VRT to VRB), RREF INTERNAL VOLTAGE REFERENCE Self Bias Mode 1 VRB VRT - VRB Self Bias Mode 2, VRT DIGITAL INPUTS Digital Input Voltage VIH VIL Digital Input Current IIH IIL DIGITAL OUTPUTS Digital Output Current IOH IOL Digital Output Current IOZH IOZL TIMING CHARACTERISTICS Output Data Delay, tDL POWER SUPPLY CHARACTERISTIC Supply Current, IDD NOTE: 2. Electrical specifications guaranteed only under the stated operating conditions. fC = 20 MSPS, NTSC Ramp Wave Input 12 17 mA 18 30 ns OE = VDD , VDD = Max VOH = VDD VOL = 0V OE = VSS , VDD = Min VOH = VDD -0.5V VOL = 0.4V -1.1 3.7 0.01 0.01 16 16 mA mA µA µA VDD = Max VIH = VDD VIL = 0V 4.0 1.0 5 5 V V µA µA VRB = AGND, Short VRT and VRTS Short VRB and VRBS , Short VRT and VRTS 0.60 1.96 2.25 0.64 2.09 2.39 0.68 2.21 2.53 V V V 4.5 230 6.6 300 8.7 450 mA Ω fC = 20 MSPS, VDD = +5V, VRB = 0.5V, VRT = 2.5V, TA = 25oC (Note 1) (Continued) TEST CONDITIONS MIN TYP MAX UNIT Timing Diagrams tPW1 tPW0 CLOCK ANALOG INPUT N N+1 N-2 N-1 N+3 N N+4 N+1 DATA OUTPUT N-3 N-2 : POINT FOR ANALOG SIGNAL SAMPLING tD = 18ns FIGURE 1. 5 HI1175 Timing Diagrams (Continued) VI (1) VI (2) VI (3) VI (4) ANALOG INPUT EXTERNAL CLOCK UPPER COMPARATOR BLOCK S (1) C (1) S (2) C (2) S (3) C (3) S (4) C (4) UPPER DATA MD (0) MD (1) MD (2) MD (3) LOWER REFERENCE VOLTAGE RV (0) RV (1) RV (2) RV (3) LOWER COMPARATOR BLOCK A S (1) H (1) C (1) S (3) H (3) C (3) LOWER DATA A LD (-1) LD (1) LOWER COMPARATOR BLOCK B H (0) C (0) S (2) H (2) C (2) S (4) H (4) LOWER DATA B LD (-2) LD (0) LD (2) DIGITAL OUTPUT OUT (-2) OUT (-1) OUT (0) OUT (1) FIGURE 2. Typical Performance Curves 20 VPP = 5.0V, VRT = 2.5V, VRB = 0.5V TA = 25oC, VIN = 2VP-P POWER DISSIPATION (mW) 20 15 IDD (mA) IDD (mA) 15 100 10 10 5 50 4.0 4.5 5.0 5.5 5 0 5 10 15 20 25 30 35 POWER SUPPLY VOLTAGE (V) SAMPLING RATE (MSPS) FIGURE 3. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 4. SUPPLY CURRENT AND POWER vs SAMPLING RATE 6 HI1175 Typical Performance Curves 1.4 DIFFERENTIAL NON-LINEARITY (LSB) TA = 25oC, VRT = 2.5V, VRB = 0.5V VDD = 5.0V, fC = 20 MSPS (Continued) 50 49 48 ENCODE 21MHz 1.0 47 46 (dB) 45 44 43 42 ENCODE 31MHz ENCODE 26MHz 0.6 0.2 0 0 2 4 6 8 10 INPUT FREQUENCY (MHz) 41 40 0 1 2 3 4 5 6 7 8 INPUT FREQUENCY (MHz) 9 10 11 FIGURE 5. DIFFERENTIAL NON-LINEARITY vs INPUT FREQUENCY FIGURE 6. HI1175JCP SNR vs INPUT FREQUENCY 8.00 7.75 7.50 7.25 7.00 (BITS) 6.75 6.50 6.25 6.00 5.75 5.50 5.25 5.00 0 1 2 3 4 5 6 7 8 9 10 11 INPUT FREQUENCY (MHz) ENCODE 31MHz ENCODE 26MHz (dB) ENCODE 21MHz -30 -33 -35 -38 -40 -43 -45 -48 -50 -53 -55 0 1 2 3 4 5 6 7 8 9 10 11 INPUT FREQUENCY (MHz) ENCODE 21MHz ENCODE 31MHz ENCODE 26MHz FIGURE 7. HI1175JCP ENOB vs INPUT FREQUENCY FIGURE 8. HI1175JCP THD vs INPUT FREQUENCY 8.00 7.75 7.50 7.25 ENOB (BITS) 7.00 6.75 6.50 6.25 6.00 5.75 5.50 5.25 5.00 21 26 31 36 fIN = 10MHz INL (LSB) fIN = 5MHz fIN = 1MHz 1.0 0.8 0.6 0.4 0.2 0 -0.2 -55 -35 -15 5 25 45 65 85 105 125 CLOCK FREQUENCY (MHz) TEMPERATURE (oC) FIGURE 9. ENOB vs CLOCK FREQUENCY FIGURE 10. INL vs TEMPERATURE 7 HI1175 Typical Performance Curves 5.0 4.5 4.0 OUTPUT VOLTAGE (V) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -55 -35 -15 IOH = 1.1mA 10 -55 IOH = -3.7mA SUPPLY CURRENT (mA) 18 (Continued) 20 16 fC = 35MHz 14 fC = 20MHz 12 5 25 45 65 TEMPERATURE (oC) 85 105 125 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (oC) FIGURE 11. DIGITAL OUTPUT VOLTAGE vs TEMPERATURE FIGURE 12. SUPPLY CURRENT vs TEMPERATURE 0.2 0.15 0.1 54 fIN = 1MHz 53 52 0.05 0 -0.05 -0.1 -0.15 -55 49 SFDR (dB) -35 -15 5 25 45 65 85 105 125 DNL (LSB) 51 50 48 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (oC) TEMPERATURE (oC) FIGURE 13. DNL vs TEMPERATURE FIGURE 14. SFDR vs TEMPERATURE -48 fIN = 1MHz -49 8.0 7.9 7.8 ENOB (BITS) fIN = 1MHz -50 THD (dB) 7.7 7.6 7.5 7.4 -51 -52 -53 7.3 7.2 -55 -54 -55 -35 -15 5 25 45 65 85 105 125 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (oC) TEMPERATURE (oC) FIGURE 15. THD vs TEMPERATURE FIGURE 16. ENOB vs TEMPERATURE 8 HI1175 Typical Performance Curves 2.5 VRT SHORTED TO VRTS VRB = AGND 2.45 VRT - VRB (V) 2.15 (Continued) 2.2 VRB SHORTED TO VRBS VRT SHORTED TO VRTS VRT (V) 2.4 2.1 2.35 2.05 2.3 -40 -15 10 35 60 85 2.0 -40 -15 10 35 60 85 TEMPERATURE (oC) TEMPERATURE (oC) FIGURE 17. VRT vs TEMPERATURE FIGURE 18. VRT - VRB vs TEMPERATURE 0.75 VRB SHORTED TO VRBS VRT SHORTED TO VRTS 25 OUTPUT RISING EDGE 20 0.7 DATA DELAY (ns) 15 OUTPUT FALLING EDGE VRB (V) 0.65 10 0.6 5 0.55 -40 -15 10 35 60 85 0 -40 -15 10 35 60 85 TEMPERATURE (oC) TEMPERATURE (oC) FIGURE 19. VRB vs TEMPERATURE FIGURE 20. OUTPUT DATA DELAY vs TEMPERATURE A/D OUTPUT CODE TABLE INPUT SIGNAL VOLTAGE VRT • • • • • • • • DIGITAL OUTPUT CODE STEP 255 • • • 128 127 • • • 0 0 0 0 0 1 0 0 1 0 1 0 1 MSB 1 D6 1 D5 1 D4 1 D3 1 • • • 0 1 • • • 0 0 0 0 0 1 0 1 0 1 D2 1 D1 1 LSB 1 VRB 9 HI1175 Detailed Description The HI1175 is a 2-step A/D converter featuring a 4-bit upper comparator group and two lower comparator groups of 4 bits each. The reference voltage can be obtained from the onboard bias generator or be supplied externally. This IC uses an offset canceling type comparator that operates synchronously with an external clock. The operating modes of the part are input sampling (S), hold (H), and compare (C). The operation of the part is illustrated in Figure 2. A reference voltage that is between VRT -VRB is constantly applied to the upper 4-bit comparator group. VI(1) is sampled with the falling edge of the first clock by the upper comparator block. The lower block A also samples VI(1) on the same edge. The upper comparator block finalizes comparison data MD(1) with the rising edge of the first clock. Simultaneously the reference supply generates a reference voltage RV(1) that corresponds to the upper results and applies it to the lower comparator block A. The lower comparator block finalizes comparison data LD(1) with the rising edge of the second clock. MD(1) and LD(1) are combined and output as OUT(1) with the rising edge of the third clock. There is a 2.5 cycle clock delay from the analog input sampling point to the corresponding digital output data. Notice how the lower comparator blocks A and B alternate generating the lower data in order to increase the overall A/D sampling rate. Power, Grounding, and Decoupling To reduce noise effects, separate the analog and digital grounds. In order to avoid latchup at power up, it is necessary that AVDD and DVDD be driven from the same supply. Bypass both the digital and analog VDD pins to their respective grounds with a ceramic 0.1µF capacitor close to the pin. Analog Input The input capacitance is small when compared with other flash type A/D converters. However, it is necessary to drive the input with an amplifier with sufficient bandwidth and drive capability. In order to prevent parasitic oscillation, it may be necessary to insert a low value (i.e., 0.24Ω) resistor between the output of the amplifier and the A/D input. Reference Input The range of the A/D is set by the voltage between VRT and VRB . The internal bias generator will set VRTS to 2.6V and VRBS to 0.6V. These can be used as the part reference by shorting VRT and VRTS and VRB to VRBS . The analog input range of the A/D will now be from 0.6V to 2.6V and is referred to as Self Bias Mode 1. Self Bias Mode 2 is where VRB is connected to AGND and VRT is shorted to VRTS . The analog input range will now be from 0V to 2.4V. Test Circuits +V S2 + S1 S1 : ON IF A < B S2 : ON IF A > B -V AB 8 COMPARATOR A8 TO A1 A0 B8 TO B1 B0 BUFFER “0” DVM CLK (20MHz) “1” 8 000 • • • 00 TO 111 • • • 10 CONTROLLER FIGURE 21. INTEGRAL AND DIFFERENTIAL NON-LINEARITY ERROR AND OFFSET VOLTAGE TEST CIRCUIT 10 HI1175 Test Circuits (Continued) 2.6V fC -1kHz SG 0.6V 1 2 NTSC SIGNAL SOURCE 40 IRE MODULATION BURST 0.6V -5.2V TTL fC ECL AMP VIN DUT HI1175 8 TTL ECL 620 2.6V -5.2V 620 SYNC DG DP 8 HI20201 1 10-BIT D/A CLK 2 VECTOR SCOPE HPF COUNTER ERROR RATE 100 IRE 0 -40 SG (CW) FIGURE 22. MAXIMUM OPERATIONAL SPEED AND DIFFERENTIAL GAIN AND PHASE ERROR TEST CIRCUIT 2.6V 0.6V VDD VRT VIN VRB HI1175 CLK OE GND VOL 2.6V IOL 0.6V VDD VRT VIN VRB HI1175 CLK IOH + OE GND VOH + - - FIGURE 23. DIGITAL OUTPUT CURRENT TEST CIRCUIT ICL8069 REFERENCE AMP A/D DSP/µP D/A AMP HA5020 (Single) HA5022(Dual) HA5024 (Quad) HA5013 (Triple) HI1175 (8-Bit) HSP9501 HSP48901 HSP43881 HSP43168 HI3338 (8-Bit) HI1171 (8-Bit) HA5020 (Single) HSP9501: Programmable Data Buffer HSP48901: 3 x 3 Image Filter, 30MHz, 8-Bit HSP43881: Digital Filter, 30MHz, 1-D and 2-D FIR Filters HSP43168: Dual FIR Filter, 10-Bit, 33MHz/45MHz CMOS Logic Available in HC, HCT, AC, ACT and FCT. HA5013: HA5020: HA5022: HA5024: Triple, 125MHz, IOUT = 20mA Single, 100MHz, IOUT = 30mA, Output Enable/Disable Dual, 125MHz, IOUT = 20mA, Output Enable/Disable Quad, 125MHz, IOUT = 20mA, Output Enable/Disable FIGURE 24. 8-BIT SYSTEM COMPONENTS 11 HI1175 Static Performance Definitions Offset, full scale, and gain all use a measured value of the internal voltage reference to determine the ideal plus and minus full scale values. The results are all displayed in LSBs. Total Harmonic Distortion This is the ratio of the RMS sum of the first 5 harmonic components to the RMS value of the measured input signal. 2nd and 3rd Harmonic Distortion This is the ratio of the RMS value of the 2nd and 3rd harmonic component respectively to the RMS value of the measured input signal. Offset Error (EOB) The first code transition should occur at a level 1/2 LSB above the bottom reference voltage. Offset is defined as the deviation of the actual code transition from this point. Note that this is adjustable to zero. Spurious Free Dynamic Range (SFDR) SFDR is the ratio of the fundamental RMS amplitude to the RMS amplitude of the next largest spur or spectral component. If the harmonics are buried in the noise floor it is the largest peak. Full Scale Error (EOT) The last code transition should occur for a analog input that is 11/2 LSBs below full scale. Full scale error is defined as the deviation of the actual code transition from this point. Full Power Input Bandwidth Full power bandwidth is the frequency at which the amplitude of the digitally reconstructed output has decreased 3dB below the amplitude of the input sine wave. The input sine wave has a peak-to-peak amplitude equal to the reference voltage. The bandwidth given is measured at the specified sampling frequency. Differential Linearity Error (DNL) DNL is the worst case deviation of a code width from the ideal value of 1 LSB. The converter is guaranteed to have no missing codes. Integral Linearity Error (INL) INL is the worst case deviation of a code center from a best fit straight line calculated from the measured data. Timing Definitions Sampling Delay (tSD) Sampling delay is the time delay between the external sample command (the falling edge of the clock) and the time at which the signal is actually sampled. This delay is due to internal clock path propagation delays. Dynamic Performance Definitions Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the HI1175. A low distortion sine wave is applied to the input, it is sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with a 1024 point FFT and analyzed to evaluate the dynamic performance of the A/D. The sine wave input to the part is -0.5dB down from fullscale for all these tests. The distortion numbers are quoted in dBc (decibels with respect to carrier) and DO NOT include any correction factors for normalizing to fullscale. Aperture Jitter (tAJ) This is the RMS variation in the sampling delay due to variation of internal clock path delays. Data Latency (tLAT) After the analog sample is taken, the data on the bus is available after 2.5 cycles of the clock. This is due to the architecture of the converter where the data has to ripple through the stages. This delay is specified as the data latency. After the data latency time, the data representing each succeeding sample is output at the following clock pulse. The digital data lags the analog input by 2.5 cycles. Signal-to-Noise Ratio (SNR) SNR is the measured RMS signal to RMS noise at a specified input and sampling frequency. The noise is the RMS sum of all of the spectral components except the fundamental and the first five harmonics. Signal-to-Noise + Distortion Ratio (SINAD) SINAD is the measured RMS signal to RMS sum of all other spectral components below the Nyquist frequency excluding DC. Output Data Delay (tD) Output Data Delay is the delay time from when the data is valid (rising clock edge) to when it shows up at the output bus. This is due to internal delays at the digital output. Effective Number Of Bits (ENOB) The effective number of bits (ENOB) is derived from the SINAD data. ENOB is calculated from: ENOB = (SINAD - 1.76 + VCORR) / 6.02, where: VCORR = 0.5dB. 12 HI1175 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 13