HI1177JCQ

HI1177 Data Sheet January 1999 File Number 4114.2 8-Bit, 40MSPS, 2-Channel D/A Converter The HI1177 is a dual 8-bit CMOS digital-to-analog converter. It has input/output equivalent to 2 channels of Y and C for video use or I and Q for modulators. The HI1177 is available in the industrial temperature range and is supplied in a 32 lead plastic metric quad flatpack (MQFP) package. Features • Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit • Maximum Conversion Speed . . . . . . . . . . . . . . . . . 40MHz • YC 2-Channel Input/Output • Differential Linearity Error. . . . . . . . . . . . . . . . . ± 0.3 LSB • Low Power Consumption . . . . . . . . . . . . . . . . . . . .160mW (200Ω Load for 2VP-P Output) • Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . +5V Single Ordering Information PART NUMBER HI1177JCQ TEMP. RANGE (oC) -40 to 85 PACKAGE 32 Ld MQFP PKG. NO. Q32.7x7-S • Power-Down Mode • Low Glitch Noise • Direct Replacment for Sony CXD1177 Pinout HI1177 (MQFP) TOP VIEW DVDD AVDD VREF CO CO YO YO VG Applications • I/Q Modulation • YC Video • Digital TV • Wireless Transmitters 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 1 2 3 4 5 6 7 8 IREF AVSS VB DVSS CCK YCK CE BLK C0 C1 C2 C3 C4 C5 C6 5 C7 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HI1177 Functional Block Diagram (LSB) Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 (LSB) C0 C1 C2 C3 C4 C5 C6 C7 1 2 3 2 LSBs CURRENT CELLS 32 31 DVDD AVDD 28 4 5 6 7 8 9 10 11 26 12 13 14 15 16 DECODER CLOCK GENERATOR + BLK 17 CURRENT CELLS (FOR FULL SCALE) 24 DECODER LATCHES 6 MSBs CURRENT CELLS 27 20 30 DECODER CLOCK GENERATOR 2 LSBs CURRENT CELLS 23 21 DECODER LATCHES 6 MSBs CURRENT CELLS 29 19 Y0 Y0 YCK AVSS DVSS C0 C0 CCK VG VREF IREF - 25 CE 18 BIAS VOLTAGE GENERATOR 22 VB Pin Descriptions NUMBER 1 to 8 9 to 16 SYMBOL Y0 to Y7 C0 to C7 1 EQUIVALENT CIRCUIT DVDD DESCRIPTION Digital Input. 16 DVSS 17 BLK DVDD Blanking pin. No signal at “H” (Output 0V). Output condition at “L”. 17 DVSS 6 HI1177 Pin Descriptions NUMBER 22 SYMBOL VB DVDD (Continued) EQUIVALENT CIRCUIT DVDD DESCRIPTION Connect a capacitor of about 0.1µF. 22 DVSS 19 20 YCK CLK 19 20 DVDD + DVSS Clock pin. Moreover all input pins are TTL-CMOS compatible. 21 23 18 DVSS AVSS CE 18 DVDD Digital GND. Analog GND. Chip enable pin. No signal (Output 0V) at “H” and minimizes power consumption. DVSS 24 25 30 31 IREF VREF VG AVDD 24 AVDD AVDD AVDD Connect a resistance 16 times “16R” that of output resistance value “R”. Set full scale output value. Connect a capacitor of about 0.1µF. + AVSS 25 AVDD Analog VDD . AVSS 30 AVSS 27 29 26 28 CO YO CO YO 27 29 AVDD Current output pin. Voltage output can be obtained by connecting a resistance. Inverted current output pin. Normally dropped to analog GND. AVSS AVDD 26 28 AVSS 32 DVDD Digital VDD . 7 HI1177 Absolute Maximum Ratings TA = 25oC Thermal Information Thermal Resistance (Typical, Note 7) θJA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (MQFP - Lead Tips Only) Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS Output Current (For Each Channel), lOUT . . . . . . . . . . 0mA to 15mA Operating Conditions Supply Voltage AVDD, AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75V to 5.25V DVDD, DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75V to 5.25V Reference Input Voltage, VREF . . . . . . . . . . . . . . . . . . . . . . . . . 2.0V Clock Pulse Width tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5ns (Min) tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5ns (Min) Temperature Range, TOPR . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications fCLK = 40MHz, VDD = 5V, ROUT = 200Ω, VREF = 2.0V, TA = 25oC TEST CONDITIONS TEST LEVEL OR NOTES PARAMETER Resolution Maximum Conversion Speed Linearity Error Differential Linearity Error Full Scale Output Voltage Full Scale Output Ratio Full Scale Output Current Offset Output Voltage Power Supply Current Digital Input Current Setup Time Hold Time Propagation Delay Time Glitch Energy Cross Talk NOTE: High Level Low Level SYMBOL n fMAX EL ED VFS FSR IFS VOS IDD IIH IIL tS tH tPD GE CT ROUT = 75Ω MIN 40 -2.5 -0.3 1.9 TYP 8 2.0 1.5 10 10 30 57 MAX 2.5 0.3 2.2 3 15 1 32 5 - UNITS bit MHz LSB LSB V % mA mV mA µA µA ns ns ns pV-s dB Note 1 0 - 14.3MHz, at Color Bar Data Input -5 5 10 - 1MHz Sin Wave Output Full-scale voltage of channel 1. Full scale output ratio = ------------------------------------------------------------------------------------------------------------------------------- ( – 1 ) x100(%) . Average of the full-scale voltage of the channels I/O Correspondence Table (Output Full Scale Voltage: 2V) INPUT CODE OUTPUT VOLTAGE LSB 1 1 1 • • • 1 1 1 1 2.0V MSB 1 1 0 0 0 • • • 0 0 0 0 1.0V 0 0 0 0 0 0 0 0 0V 8 HI1177 Timing Diagram tPW1 tPW0 CLK tS tHL DATA tS tHL tS tHL tPD 100% D/AOUT 50% tPD tPD 0% FIGURE 1. Test Circuits 8-BIT COUNTER WITH LATCH Y0 ~ Y7 1~8 Y0 29 200 AVSS C0 27 200 OSCILLOSCOPE C0 ~ C7 9 ~ 18 17 0.1µ 18 22 DVSS BLK AVSS CE VB VG 30 0.1µ 19 20 YCK CCK VREF 25 IREF 24 3.3K AVSS 1K AVDD CLK 40MHz SQUARE WAVE FIGURE 2. MAXIMUM CONVERSION 9 HI1177 Test Circuits (Continued) Y0 29 75 AVSS C0 27 75 17 DELAY CONTROLLER 0.1µ 18 22 DVSS CLK 1MHz SQUARE WAVE 19 DELAY CONTROLLER 20 YCK CCK BLK AVSS CE VB VG 30 0.1µ VREF 25 IREF 24 1.2K AVSS 1K AVDD OSCILLOSCOPE 8-BIT COUNTER WITH LATCH Y0 ~ Y7 1~8 C0 ~ C7 9 ~ 18 FIGURE 3. SETUP HOLD TIME AND GLITCH ENERGY ALL “1” Y0 ~ Y7 1~8 DIGITAL WAVEFORM GENERATOR Y0 29 200 AVSS C0 27 200 17 0.1µ 18 22 DVSS CLK 40MHz SQUARE WAVE 19 20 YCK CCK BLK AVSS CE VB VG 30 0.1µ VREF 25 IREF 24 3.3K AVSS 1K AVDD SPECTRUM ANALIZER C0 ~ C7 9 ~ 18 FIGURE 4. CROSSTALK Y0 ~ Y7 1~8 CONTROLLER C0 ~ C7 9 ~ 18 17 0.1µ 18 22 DVSS CLK 40MHz SQUARE WAVE 19 20 YCK CCK BLK Y0 29 200 AVSS C0 27 200 AVSS DVM CE VB VG 30 0.1µ VREF 25 IREF 24 3.3K AVDD 1K AVSS FIGURE 5. DC CHARACTERISTICS 10 HI1177 Test Circuits (Continued) Y0 ~ Y7 1~8 FREQUENCY DEMULTIPLIER C0 ~ C7 9 ~ 18 17 0.1µ 18 22 DVSS CLK 10MHz SQUARE WAVE 19 20 YCK CCK BLK Y0 29 200 AVSS C0 27 200 AVSS OSCILLOSCOPE CE VB VG 30 0.1µ VREF 25 IREF 24 3.3K AVDD 1K AVSS FIGURE 6. PROPAGATION DELAY TIME Typical Performance Curves VFS, OUTPUT FULL SCALE VOLTAGE (V) 200 2 100 1 VDD = 5.0V R = 200Ω 16R = 3.3kΩ TA = 25oC 1 2 VREF , REFERENCE VOLTAGE (V) 100 OUTPUT RESISTANCE (Ω) 200 FIGURE 7. OUTPUT FULL SCALE VOLTAGE vs REFERENCE VOLTAGE FIGURE 8. GLITCH ENERGY vs OUTPUT RESISTANCE 60 OUTPUT FULL SCALE VOLTAGE (V) 2.0 CROSSTALK (dB) VDD = 5V VREF = 2V R = 200Ω 16R = 3.3kΩ 0 -25 0 25 50 75 AMBIENT TEMPERATURE (oC) 100 50 1.9 40 100K 1M OUTPUT FREQUENCY (Hz) 10M FIGURE 9. OUTPUT FULL SCALE VOLTAGE vs AMBIENT TEMPERATURE FIGURE 10. CROSSTALK vs OUTPUT FREQUENCY 11 HI1177 Application Circuit Y OUT C OUT 200 AVSS DVDD AVDD 0.1µF 32 1 2 3 4 Y IN 5 6 7 (MSB) 8 9 10 11 12 13 14 15 16 17 DVSS 20 19 18 31 30 29 28 27 AVSS 25 24 3.3K 23 AVSS 22 0.1µF 21 DVSS CLOCK 200 AVSS AVDD 1K AVSS (LSB) 26 (LSB) C IN (MSB) FIGURE 11. Operation • How to select the output resistance: - The HI1177 is a D/A converter of the current output type. To obtain the output voltage connect the resistance to IO pin (Y0, C0). For specifications we have: Output full scale voltage Output full scale current VFS = less than 2V IFS = less than 15mA • Phase relation between data and clock: - To obtain the expected performance as a D/A converter, it is necessary to set properly the phase relation between data and clock applied from the exterior. Be sure to satisfy the provisions of the set up time (tS) and hold time (tH) as stipulated in the Electrical Characteristics. • VDD, VSS : - To reduce noise effects separate analog and digital systems in the device periphery. For VDD pins, both digital and analog, bypass respective GNDs by using a ceramic capacitor of about 0.1µF, as close as possible to the pin. - Calculate the output resistance value from the relation of VFS = IFS X R. Also, 16 times resistance of the output resistance is connected to reference current pin IREF. In some cases, however, this turns out to be a value that does not actually exist. In such a case a value close to it can be used as a substitute. Here please note that VFS becomes VFS = VREF X 16R/R’. R is the resistance connected to IO while R’ is connected to IREF. Increasing the resistance value can curb power consumption. On the other hand glitch energy and data settling time will inversely increase. Set the most suitable value according to the desired application. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 12