HI1178

HI1178 March 1998 Triple 8-Bit, 40 MSPS, RGB, 3-Channel D/A Converter Description The HI1178 is a triple 8-bit, high-speed, CMOS D/A converter designed for video band use. It has three separate, 8-bit, pixel inputs, one each for red, green, and blue video data. A single 5.0V power supply and pixel clock input is all that is required to make the device operational. A bias voltage generator is internal. Each channel clock input can be controlled individually, or connected together as one. The HI1178 also has BLANK video control signal. Refer to the HI2304 for 3.3V operation. Features • Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . Triple 8-Bit • Maximum Conversion Speed . . . . . . . . . . . . . . . 40MHz • RGB 3-Channel Input/Output • Differential Linearity Error . . . . . . . . . . . . . . . +0.3 LSB • Low Power Consumption . . . . . . . . . . . . . . . . . .240mW (200Ω Load for 2VP-P Output) • Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . +5V • Low Glitch Noise • Direct Replacement for Sony CXD1178 Ordering Information PART NUMBER HI1178JCQ TEMP. RANGE (oC) -40 to 85 PACKAGE 48 Ld MQFP PKG. NO. Q48.12x12-S Applications • Digital TV • Graphics Display • High Resolution Color Graphics • Video Reconstruction • Instrumentation • Image Processing • I/Q Modulation Pinout HI1178 (MQFP) TOP VIEW DVDD DVDD AVDD AVDD AVDD AVDD VG BO GO GO BO RO R0 R1 R2 R3 R4 R5 R6 R7 G0 G1 G2 G3 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 RO IREF VREF AVSS VB DVSS DVSS BCK GCK RCK CE BLK G6 G7 B2 B3 B1 G4 G5 B0 B4 B5 B6 B7 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 File Number 4115.2 10-1100 HI1178 Functional Block Diagram (LSB) R0 R1 R2 R3 R4 R5 R6 R7 (LSB) G0 G1 G2 G3 G4 G5 G6 G7 1 2 3 2 LSBs CURRENT CELLS 47 48 DVDD DVDD 36 4 5 6 7 8 DECODER CLOCK GENERATOR 43 44 45 46 DECODER LATCHES 6 MSBs CURRENT CELLS 37 27 R0 R0 RCK AVSS AVDD AVDD AVDD 9 10 11 2 LSBs CURRENT CELLS 38 12 13 14 15 16 DECODER CLOCK GENERATOR 2 LSBs CURRENT CELLS 33 30 (LSB) B0 B1 B2 B3 B4 B5 B6 B7 17 18 19 20 21 22 23 24 DECODER CLOCK GENERATOR + BLK 25 CURRENT CELLS (FOR FULL SCALE) 40 DECODER LATCHES 6 MSBs CURRENT CELLS 41 29 42 31 DECODER LATCHES 6 MSBs CURRENT CELLS 39 28 G0 G0 GCK AVSS DVSS DVSS B0 B0 BCK VG VREF IREF - 34 35 CE 26 BIAS VOLTAGE GENERATOR 32 VB 10-1101 HI1178 Pin Descriptions PIN NO. 1 to 8 9 to 16 17 to 24 SYMBOL R0 to R7 G0 to G7 1 EQUIVALENT CIRCUIT DVDD DESCRIPTION Digital input. B0 to B7 24 DVSS 25 BLK DVDD Blanking pin. No signal at “H” (Output 0V). Output condition at “L”. 25 DVSS 32 VB DVDD Connect a capacitor of about 0.1µF. DVDD 32 + - DVSS 27 28 29 RCK CLK BCK 27 28 29 DVDD Clock pin. Moreover all input pins are TTL-CMOS compatible. DVSS 30, 31 33 26 DVSS AVSS CE DVDD Digital GND. Analog GND. Chip enable pin. No signal (Output 0V) at “H” and minimizes power consumption. 26 DVSS 10-1102 HI1178 Pin Descriptions PIN NO. 35 SYMBOL IREF VREF VG 35 AVDD (Continued) EQUIVALENT CIRCUIT AVDD AVDD DESCRIPTION Connect a resistance 16 times “16R” that of output resistance value “R”. Set full scale output value. Connect a capacitor of about 0.1µF. 34 42 + AVSS 34 AVDD AVSS 42 AVSS 43 to 46 37 39 41 36 38 40 AVDD RO GO BO RO GO AVSS 37 39 41 AVDD Analog VDD . Current output pin. Voltage output can be obtained by connecting a resistance. Inverted current output pin. Normally dropped to analog GND. BO 36 38 40 AVDD AVSS 47, 48 DVDD Digital VDD . 10-1103 HI1178 Absolute Maximum Ratings TA = 25oC Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range (TSTG) . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (Lead Tips Only) Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS Output Current (IOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS Digital Input Voltage (CLK) . . . . . . . . . . . . . . . . . . . . . .0mA to 15mA (Every Each Channel) Operating Conditions Temperature Range (TOPR) . . . . . . . . . . . . . . . . . . . . -40oC to 85oC Supply Voltage AVDD , AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.75V to 5.25V DVDD , DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75V to 5.25V Reference Input Voltage (VREF). . . . . . . . . . . . . . . . . . . . . . . . . . 2V Clock Pulse Width tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5ns (Min) tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5ns (Min) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER Resolution Maximum Conversion Speed Linearity Error Differential Linearity Error Full Scale Output Voltage Full Scale Output Ratio (Note 1) Full Scale Output Current Offset Output Voltage Power Supply Current Digital Input Current Set Up Time Hold Time Propagation Delay Time Glitch Energy Crosstalk H Level L Level fCLK = 40MHz, VDD = 5V, ROUT = 200Ω , VREF = 2.0V, TA = 25oC SYMBOL n TEST CONDITIONS MIN 40 -2.5 -0.3 1.8 0 - TYP 8 2.0 1.5 10 10 30 57 MAX 2.5 0.3 2.2 3 15 1 48 5 - UNITS bit MSPS LSB LSB V % mA mV mA µA µA ns ns ns pV/s dB fMAX EL ED VFS FSR IFS VOS IDD IIH IIL tS tH tPD GE CT ROUT = 75Ω 1MHz Sin Wave Output 14.3MHz, at Color Bar Data Input -5 5 10 - NOTE: Full Scale Voltage of Channel 1. Full scale output ratio = ------------------------------------------------------------------------------------------------------------------------------------ – 1 x 100(%) Average of the Full Scale Voltage of the Channels I/O Chart (When Full Scale Output Voltage at 2.00V) INPUT CODE MSB 1 1 1 1 1 1 1 LSB 1 OUTPUT CODE 2.0V • • • 1 0 0 0 0 0 0 0 1.0V • • • 0 0 0 0 0 0 0 0 0V 10-1104 HI1178 Timing Diagram tPW1 tPW0 CLK tS tHL DATA tS tHL tS tHL tPD 100% D/AOUT 50% tPD tPD 0% FIGURE 1. Test Circuits 8-BIT COUNTER WITH LATCH R0 ~ R7 1~8 G0 ~ G7 9 ~ 18 B0 ~ B7 17 ~ 24 R0 37 200 AVSS G0 39 200 AVSS B0 41 HI1178 200 AVSS AVDD VG 42 0.1µ VREF 34 IREF 35 3.3K AVSS 1K OSCILLOSCOPE 25 26 32 0.1µ DVSS CLK 40MHz SQUARE WAVE BLK CE VB 27 RCK 28 GCK 29 BCK FIGURE 2. MAXIMUM CONVERSION RATE TEST CIRCUIT 10-1105 HI1178 Test Circuits (Continued) 8-BIT COUNTER WITH LATCH R0 ~ R7 1~8 G0 ~ G7 9 ~ 18 B0 ~ B7 17 ~ 24 R0 37 75 G0 39 AVSS 75 AVSS B0 41 OSCILLOSCOPE 25 BLK DELAY CONTROLLER 0.1µ 26 CE 32 VB DVSS 27 RCK CLK 1MHz SQUARE WAVE DELAY CONTROLLER 28 GCK 29 BCK VREF 34 1.2K IREF 35 AVSS HI1178 75 AVSS AVDD VG 42 0.1µ 1K FIGURE 3. SETUP HOLD TIME AND GLITCH ENERGY TEST CIRCUIT R0 ~ R7 1~8 DIGITAL WAVEFORM GENERATOR ALL “1” G0 ~ G7 9 ~ 16 B0 ~ B7 17 ~ 24 R0 37 G0 39 AVSS SPECTRUM ANALYZER AVSS B0 25 BLK 26 CE 0.1µ 32 VB DVSS VG 27 RCK CLK 40MHz SQUARE WAVE 28 GCK 29 BCK VREF IREF 34 42 0.1µ 1K AVDD HI1178 AVSS 41 35 AVSS FIGURE 4. CROSSTALK TEST CIRCUIT 10-1106 HI1178 Test Circuits (Continued) R0 37 R0 ~ R7 1~8 CONTROLLER G0 ~ G7 9 ~ 16 B0 ~ B7 17 ~ 24 200 AVSS G0 39 200 AVSS 25 BLK 0.1µ DVSS VG 42 CLK 40MHz SQUARE WAVE 27 RCK 28 GCK 29 BCK VREF 34 IREF 35 3.3K AVSS 26 CE 32 VB B0 41 HI1178 200 AVSS AVDD 0.1µ 1K DVM FIGURE 5. DC CHARACTERISTICS TEST CIRCUIT R0 ~ R7 1~8 FREQUENCY DEMULTIPLIER G0 ~ G7 9 ~ 16 B0 ~ B7 17 ~ 24 R0 37 200 AVSS G0 39 200 AVSS OSCILLOSCOPE 25 BLK 26 CE 0.1µ 32 VB DVSS HI1178 B0 41 200 AVSS 0.1µ VG 42 27 RCK AVDD CLK 10MHz SQUARE WAVE VREF 34 28 GCK 29 BCK IREF 35 3.3K 1K AVSS FIGURE 6. PROPAGATION DELAY TIME TEST CIRCUIT 10-1107 HI1178 Typical Performance Curves VFS , OUTPUT FULL SCALE VOLTAGE (V) 200 2.0 100 1.0 VDD = 5.0V R = 200Ω 16R = 3.3kΩ TA = 25oC 1.0 2.0 VREF , REFERENCE VOLTAGE (V) 100 OUTPUT RESISTANCE (Ω) 200 FIGURE 7. OUTPUT FULL SCALE VOLTAGE vs REFERENCE VOLTATE FIGURE 8. GLITCH ENERGY vs OUTPUT RESISTANCE OUTPUT FULL SCALE VOLTAGE (V) 60 2.0 CROSSTALK (dB) VDD = 5.0V VREF = 2.0V R = 200Ω 16R = 3.3kΩ 0 -25 0 25 50 75 AMBIENT TEMPERATURE (oC) 100 100K 1M OUTPUT FREQUENCY (Hz) 10M 50 1.9 40 FIGURE 9. OUTPUT FULL SCALE VOLTAGE vs AMBIENT TEMPERATURE FIGURE 10. CROSSTALK vs OUTPUT FREQUENCY 10-1108 HI1178 Application Circuit B(BLUE)OUT 200 AVSS G(GREEN)OUT 200 AVDD 0.1µ 200 48 47 46 45 44 43 42 41 40 39 38 37 (LSB) 1 2 3 R(RED)IN 4 5 6 7 (MSB) (LSB) 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (LSB) G(GREEN)IN (MSB) (MSB) HI1178 AVSS 36 35 34 33 32 31 30 (BCK) 29 (GCK) 28 (RCK) 27 26 25 DVSS DVSS CLOCK IN 0.1µ 2V AVDD 1K AVSS AVSS 3.3K AVSS R(RED)OUT DVDD B(BLUE)IN FIGURE 11. Notes On Operation • How to select the output resistance The HI1178 is a current-output D/A converter. To obtain the output voltage, connect the resistance to IO pin (RO, GO, BO). For specifications we have: Output Full Scale Voltage VFS = less than 2.0 [V] Output Full Scale Current IFS = less than 15 [mA] Calculate the output resistance value from the relation of VFS = IFS X R. Also, 16 times resistance of the output resistance is connected to reference current pin IREF . In some cases, however, this turns out to be a value that does not actually exist. In such a case a value close to it can be used as a substitute. Here please note that VFS becomes VFS = VREF X 16R/R'. R is the resistance connected to IO while R' is connected to IREF . Increasing the resistance value can curb power consumption. On the other hand glitch energy and data settling time will inversely increase. Set the most suitable value according to the desired application. • Phase Relation Between Data and Clock To obtain the expected performance as a D/A converter, it is necessary to set properly the phase relation between data and clock applied from the exterior. Be sure to satisfy the provisions of the set up time (tS) and hold time (tH) as stipulated in the Electrical Characteristics. • VDD , VSS To reduce noise effects separate analog and digital systems in the device periphery. For VDD pins, both digital and analog, bypass respective GNDs by using a ceramic capacitor of 0.1µF, as close as possible to the pin. 10-1109 HI1178 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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