HI1386JCP

® T DUC E NT PRO LACEM r at TE e nt e OL E R EP OBS ENDED upport C om/tsc .c MM nical S rsil EC O h .inte NO R our Tec or www IL act cont -INTERS 88 1-8 HI1386 March 2003 8-Bit, 75 MSPS, Flash A/D Converter Features • • • • • • • • • • • • • • • • • • • Differential Linearity Error ±0.5 LSB or Less Integral Linearity Error ±0.5 LSB or Less Built-In Integral Linearity Compensation Circuit High-Speed Operation with Maximum Conversion Rate (Min) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 MSPS Low Input Capacitance (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . 17pF Wide Analog Input Bandwidth (Min for Full Scale Input) 150MHz Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.2V Low Power Consumption (Typ) . . . . . . . . . . . . . . . . . . . . . 580mW Low Error Rate Operable at 50% Clock Duty Cycle Capable of Driving 50Ω Loads Direct Replacement for CXA1386 Video Digitizing RGB Graphics Processing HDTV (High Definition TV) Radar Systems Communication Systems Direct RF Down-Conversion Digital Oscilloscopes Description The HI1386 is an 8-bit, high-speed flash analog-to-digital converter IC capable of digitizing analog signals at a maximum rate of 75 MSPS. The digital I/O levels of this A/D converter are compatible with ECL 100K/10KH/10K. The HI1386 is available in the commercial and industrial temperature range and is supplied in 28 lead plastic DIP and 44 lead ceramic LCC packages. Part Number Information PART NUMBER HI1386JCP HI1386AIL TEMP. RANGE (oC) -20 to 75 -20 to 100 PACKAGE 28 Ld PDIP 44 Ld CLCC PKG. NO. E28.6A-S J44.B Applications Pinouts HI1386 (PDIP) TOP VIEW DGND2 DVEE HI1386 (CLCC) TOP VIEW AVEE AVEE AVEE 39 NC 38 NC 37 AGND 36 VIN 35 AGND 34 VRM 33 AGND 32 VIN 31 AGND 30 NC 29 NC 18 19 20 21 22 23 24 25 26 27 28 LINV DVEE 2 DGND 3 (LSB) D0 4 D1 5 D2 6 D3 7 D4 8 D5 9 D6 10 (MSB) D7 11 DGND 12 DVEE 13 MINV 14 27 VRT 26 AVEE 25 AGND 24 VIN 23 AGND 22 VRM 21 AGND 20 VIN 19 AGND 18 AVEE 17 VRB 16 CLK 15 CLK NC 7 (LSB) D0 8 D1 9 D2 10 D3 11 D4 12 D5 13 D6 14 (MSB) D7 15 DGND2 16 NC 17 6 5 4 3 2 1 44 43 42 41 40 DVEE VRB VRT LINV 1 NC NC NC 28 AVEE DGND1 AVEE DGND1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners. 1 AVEE MINV CLK NC NC CLK NC FN3583.5 HI1386 Functional Block Diagram MINV R1 VRT R/2 R 1 R D7 (MSB) 2 R D6 COMPARATOR 63 R VIN 64 R 65 OUTPUT D3 R 126 R R2 VRM R 128 R D0 (LSB) 129 127 ENCODE LOGIC D1 D2 D4 D5 R 191 R VIN 192 R 193 R 254 R 255 VRB CLK CLK R3 R/2 CLOCK DRIVER LINV 2 HI1386 Pin Descriptions PIN NUMBER DIP 19, 21, 23, 25 LCC 31, 33, 35, 37 SYMBOL AGND I/O STANDARD VOLTAGE LEVEL 0V EQUIVALENT CIRCUIT DESCRIPTION Analog GND. Used as GND for input buffers and latches of comparators. Isolated from DGND, DGND1, and DGND2. Analog VEE -5.2V (Typ). Internally connected to DVEE (Resistance: 4Ω to 6Ω). Bypass with 0.1µF to AGND. CLK Input. 18, 26, 28 27, 28, 40, 41, 44 AVEE - -5.2V 16 15 23 22 CLK CLK I ECL DGND, DGND1 R R CLK CLK R R Input Complementary to CLK. When open pulled down to -1.3V. Device is operable without CLK input, but use of complementary inputs of CLK and CLK is recommended to obtain stable high speed operation. DVEE R R 3, 12 - DGND - 0V Digital GND (used for internal circuits and output transistors). Digital GND (used for internal circuits and output transistors). Digital GND (used for output buffers). Digital VEE . Internally connected to AVEE (resistance: 4Ω to 6Ω). Bypass with 0.1µF to DGND LSB of Data Outputs. External pull-down resistor is required. Data Outputs. External pull-down resistors are required. D1 - 5, 19 DGND1 - 0V - 6, 16 DGND2 - 0V 2, 13 4, 20 DVEE - -5.2V 4 8 D0 O ECL DGND 5 6 7 8 9 10 11 9 10 11 12 13 14 15 D1 D2 D3 D4 D5 D6 D7 DVEE MSB of Data Outputs. External pull-down resistor is required. 3 HI1386 Pin Descriptions PIN NUMBER DIP 1 LCC 3 SYMBOL LINV I/O I (Continued) STANDARD VOLTAGE LEVEL ECL DGND, DGND1 EQUIVALENT CIRCUIT DESCRIPTION Input Pin for D0 (LSB) to D6 Output Polarity Inversion (see A/D Output Code Table). Pulled low when left open. 14 21 MINV I ECL R R LINV OR MINV R -1.3V Input Pin for D7 (MSB) Output Polarity Inversion (see A/D Output Code Table). Pulled low when left open. DVEE R 20, 24 32, 36 VIN I VRT to VRB AGND VIN VIN Analog Input Pins. These two pins must be connected externally, since they are not internally connected. See Application Note for precautions. AVEE 17 26 VRB I -2V VRT R1 R/2 Reference Voltage (Bottom). Typically -2V. Bypass with a 0.1µF and 10µF to AGND. R COMPARATOR 1 R 22 34 VRM I VRB/2 Reference Voltage Mid Point. Can be used as a pin for integral linearity compensation. Reference Voltage (Top) Typically 0V. 27 42 VRT I 0V R VRM R2 R COMPARATOR 2 COMPARATOR 127 COMPARATOR 128 R COMPARATOR 129 R COMPARATOR 130 R COMPARATOR 255 VRB R3 R/2 4 HI1386 Absolute Maximum Ratings TA = 25oC Supply Voltage (AVEE , DVEE) . . . . . . . . . . . . . . . . . . . -7V to +0.5V Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V Reference Input Voltage VRT , VRB , VRM . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V |VRT -VRB | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V Digital Input Voltage CLK, CLK, MINV, LINV . . . . . . . . . . . . . . . . . . . . . . . -4V to +0.5V |CLK-CLK | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V VRM Pin Input Current (IVRM) . . . . . . . . . . . . . . . . . . -3mA to +3mA Digital Output Current (ID0 to ID7) . . . . . . . . . . . . . . . -30mA to 0mA Thermal Information Thermal Resistance (Typical, Note 1) θJAoC/W θJCoC/W PDIP Package . . . . . . . . . . . . . . . . . . . 58 N/A CLCC Package . . . . . . . . . . . . . . . . . . 45 11 Maximum Junction Temperature CLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range (TSTG) . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . 300oC Operating Conditions Temperature Ranges (Note 4) PDIP Package (TA). . . . . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC CLCC Package (TC) . . . . . . . . . . . . . . . . . . . . . . . -20oC to100oC Supply Voltage AVEE , DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5V to -4.95V AVEE - DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V AGND - DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V Reference Input Voltage VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.1V to 0.1V VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.2V to -1.8V Analog Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . VRB to VRT Pulse Width of Clock tPW1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6ns (Min) tPW0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6ns (Min) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL Differential Linearity Error, DNL DYNAMIC CHARACTERISTICS TA = 25oC, AVEE = DVEE = -5.2V, VRT = 0V, VRB = -2V (Note 1) TEST CONDITIONS MIN TYP MAX UNIT fC = 75MHz fC = 75MHz - 8 ±0.3 ±0.3 ±0.5 ±0.5 Bits LSB LSB Signal to Noise and Distortion Ratio, SINAD Input = 1MHz, Full Scale fC = 75MHz RMS Signal = ----------------------------------------------------------------RMS Noise + Distortion Input = 18.75MHz, Full Scale fC = 75MHz Error Rate Differential Gain Error, DG Differential Phase Error, DP Maximum Conversion Rate, fC Aperture Jitter, tAJ Sampling Delay, tDS ANALOG INPUT Input Bandwidth Analog Input Capacitance, CIN Analog Input Resistance, RIN Input Bias Current, IIN REFERENCE INPUTS Reference Resistance, RREF VIN = -1V VIN = 2VP-P (-3dB) VIN = 1V + 0.07VRMS Input = 18.749MHz, Full Scale Error > 16 LSB, fC = 75MHz NTSC 40 IRE Mod. Ramp, fC = 75 MSPS Error Rate of 10-9 TPS (Note 2) 75 - 46 40 1.0 0.5 10 3.0 10-9 - dB dB TPS (Note 2) % Degree MSPS ps ns 150 - 17 390 - 200 MHz pF kΩ µA 75 110 155 Ω 5 HI1386 Electrical Specifications PARAMETER Offset Voltage EOT EOB DIGITAL INPUTS Logic H Level, VIH Logic L Level, VIL Logic H Current, IIH Logic L Current, IIL Input Capacitance DIGITAL OUTPUTS Logic H Level, VOH Logic L Level, VOL TIMING CHARACTERISTICS H Pulse Width of Clock, tPW1 L Pulse Width of Clock, tPW0 Output Rise Time, tr Output Fall Time, tf Output Delay, tOD POWER SUPPLY CHARACTERISTICS Supply Current, IEE Power Consumption, PD Note 3 -150 -104 580 mA mW RL = 620Ω to DVEE , 20% to 80% RL = 620Ω to DVEE , 20% to 80% 6.6 6.6 4.0 0.9 2.1 6.5 9.0 ns ns ns ns ns RL = 620Ω to DVEE RL = 620Ω to DVEE -1.03 -1.62 V V -0.8V is Applied to Input -1.6V is Applied to Input -1.13 0 -50 7 -1.50 50 50 V V µA µA pF VRT VRB 8 0 18 10 32 24 mV mV TA = 25oC, AVEE = DVEE = -5.2V, VRT = 0V, VRB = -2V (Note 1) (Continued) TEST CONDITIONS MIN TYP MAX UNIT NOTES: 1. Electrical Specifications guaranteed within stated operating conditions. 2. TPS: Times Per Sample. 3. ( V RT -V RB ) P D = I EE • V EE + -----------------------------------R REF 2 4. TA specified in still air and without heat sink. To extend temperature range, appropriate heat management techniques must be employed. Timing Diagram tDS ANALOG IN N N+1 N+2 tPW1 CLK CLK tPW0 DIGITAL OUT tOD N-1 20% 80% N 80% N+1 20% tf tr FIGURE 1. 6 HI1386 A/D OUTPUT CODE TABLE MINV 1 LINV 1 STEP D7 D0 D7 0 1 D0 D7 1 0 D0 D7 0 0 D0 VIN (NOTE 1) 0V 000 • • • • • 00 0 1 000 • • • • • 00 000 • • • • • 01 • • • 100 • • • • • 00 100 • • • • • 00 100 • • • • • 01 • • • 111 • • • • • 11 000 • • • • • 00 • • • 011 • • • • • 10 011 • • • • • 11 011 • • • • • 11 011 • • • • • 11 011 • • • • • 11 011 • • • • • 10 • • • 000 • • • • • 00 111 • • • • • 11 • • • 100 • • • • • 01 100 • • • • • 00 100 • • • • • 00 111 • • • • • 11 111 • • • • • 11 111 • • • • • 10 • • • 100 • • • • • 00 011 • • • • • 11 • • • 000 • • • • • 01 000 • • • • • 00 000 • • • • • 00 -1V 127 128 011 • • • • • 11 100 • • • • • 00 • • • 254 255 -2V NOTE: 5. VRT = 0V, VRB = -2V. 111 • • • • • 10 111 • • • • • 11 111 • • • • • 11 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 7