HI2303EVAL

HI2303 Data Sheet December 1998 File Number 4106.2 Triple 8-Bit, 50 MSPS, Video A/D Converter with Clamp Function The HI2303 is a highly integrated 8-bit, 3-channel analog-todigital converter that is designed for component (like RGB) digitizing applications. The internal DC Restore (video clamp) function and voltage reference simplifies system design and saves board space. The HI2303 can digitize RGB, YUV, YIQ and any other analog component color signals used in video systems. The variety of sub-sampling modes is compatible with RGB, YUV and YIQ color systems where 4:4:4, 4:2:2 and 4:1:1 data reduction is needed. The 2-step architecture boasts, low power operation, and excellent video performance. Features • Resolution 8-Bit 1/2 LSB (DL) • Low Power Consumption (at 50 MSPS Typ) (Reference Current Excluded) . . . . . . . . . . . . . . . .500mW • Synchronizing Digital Clamp Function • Clamp ON/OFF Function • Reference Voltage Self-Bias Circuit • Input CMOS/TTL Compatible • Three-State TTL Compatible Output • Single 5V Power Supply or Dual 5V or 3.3V Power Supplies • Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . .15pF • Different Digital Output Multiplex Format - 4:4:4 - 4:2:2 - 4:1:1 • Direct Replacement for Sony CXD2303 Ordering Information PART NUMBER HI2303JCQ HI2303EVAL TEMP. RANGE (oC) -40 to 85 25 PACKAGE 80 Ld MQFP Evaluation Kit PKG. NO. Q80.14x20-S Applications • Video Digitizing (Composite and Y-C) • LCD Projectors • LCD Panels • RGB Graphics Processing Pinout HI2303 (MQFP) TOP VIEW AVSS DVDD DVDD TGR A7 (MSB) A6 A5 A4 A3 A2 A1 A0 (LSB) DVSS DVSS B7 (MSB) B6 B5 B4 B3 B2 B1 B0 (LSB) DVDD DVDD 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ARBS ARB AVSS AIN AIO AVDD ART ARTS BRTS BRT AVDD BIO BIN AVSS BRB BRBS 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 AVDD AVDD TEST XAOE XBOE XCOE CTL0 CTL1 CTL2 SY SEL CLK CLP REF0 REF1 REF2 REF3 CLE TEST AVSS AVSS AVDD CRBS CRB 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 C7 (MSB) C6 C5 C4 C3 C2 C1 C0 (LSB) DVSS DVSS CRTS CRT AVDD CIO CIN AVSS 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HI2303 Functional Block Diagram DVDD DVDD DVDD DVDD AVDD AVDD AVDD AVDD AVDD AVDD DVSS DVSS 12 DVSS 71 72 DVSS ARTS 32 ART 31 AIN 28 ARB 26 ARBS 25 AIO 29 8-BIT DAC 8 8 A-CH 8-BIT ADC DIGITAL CLAMP CIRCUIT 13 A0 (LSB) 30 35 41 42 62 68 22 23 1 2 11 20 A7 (MSB) 44 XAOE BRTS 33 BRT 34 BIN 37 BRB 39 BRBS 40 BIO 36 8 8-BIT DAC 8 B-CH 8-BIT ADC DIGITAL CLAMP CIRCUIT DATA SELECTOR + LATCH 3 B0 (LSB) 10 B7 (MSB) 45 XBOE CRTS 70 CRT 69 CIN 66 CRB 64 CRBS 63 CIO 67 8-BIT DAC 8 8 C-CH 8-BIT ADC DIGITAL CLAMP CIRCUIT 73 C0 (LSB) 80 C7 (MSB) 46 XCOE 21 TGR AVSS 24 AVSS 27 DIGITAL CONTROL AVSS 38 DECODER 47 CTL0 48 CTL1 49 CTL2 50 SY 60 61 65 AVSS AVSS AVSS 52 CLK 58 CLE 53 CLP 51 SEL 54 REF0 57 REF3 59 TEST 43 TEST 2 HI2303 Pin Description PIN NO. 1, 2, 22, 23 13 to 20 3 to 10 73 to 80 21 SYMBOL DVDD A0 to A7 B0 to B7 C0 to C7 TGR O DVDD EQUIVALENT CIRCUIT DESCRIPTION Digital Power Supply. +5V or +3.3V. Digital output. A0 (LSB) to A7 (MSB) B0 (LSB) to B7 (MSB) C0 (LSB) to C7 (MSB). Trigger Output O DVSS 11, 12, 71, 72 24, 27, 38, 60, 61, 65 25 40 63 26 39 64 31 34 69 32 33 70 28 37 66 DVSS AVSS ARBS BRBS CRBS ARB BRB CRB ART BRT CRT ARTS BRTS CRTS AIN BIN CIN AVDD Digital Ground. Analog Ground. Shorting the RBS pins to AVSS generates voltage of approximately 0.6V at the ARB, BRB and CRB pins. Reference Voltage (Bottom). RTS 32 33 RB 26 RT 39 RREF RB 64 25 40 63 AVSS RBS - 70 31 - 34 69 Reference Voltage (Top). - RT Shorting the RTS pins to AVDD generates voltage of about 2.5V at the ART, BRT and CRT pins. Analog Input. I AVDD 28 37 66 AVSS 29 36 67 AIO BIO CIO O AVDD Analog Output. These pins are the D/A converter outputs which comprise the digital clamp circuit. 200Ω 29 36 67 AVSS 3 HI2303 Pin Description PIN NO. 30, 35, 41, 42, 62, 68 43 59 44 45 46 (Continued) EQUIVALENT CIRCUIT DESCRIPTION Analog +5V Power Supply. I I Normally open. Pull-down resistors are incorporated. Output Enable Input. When these pins are Low, data is output from the digital output pins. When these pins are High, the digital output pins are High impedance. The A, B and C Channels can be controlled separately. Also, these pins are not synchronized with the clock signal. Pull-down resistors are incorporated. Determines the digital output mode. See the Mode tables and Timing Charts. Pull-down resistors are incorporated. AVSS SYMBOL AVDD TEST XAOE XBOE XCOE AVDD 47 48 49 50 CTL0 CTL1 CLT2 SY I I Controls the digital output mode switching timing. The mode is switched by detecting the transition point where this pin changes from Low to High. See the Mode Tables and Timing Charts for details. A pull-down resister is incorporated. 51 SEL I Controls the CLP signal polarity. When this pin is Low, CLP is High active. When this pin is High, CLP is Low active. This pin has a built-in pulldown resistor. AVDD 52 53 CLK CLP I I Clock Input. A pull-down resistor is incorporated. Clamp Pulse Input. The polarity can be set to either High or Low by setting SEL. This pin has a built-in pull-down resistor. Determines the clamp circuit reference data. See the mode tables for the set data. These pins are not synchronized with the clock input signal. Pull-down resistors are incorporated. Clamp Enable. When this pin is Low the clamp circuit does not operate. When this pin is High, the clamp circuit operates. A pull-down resistor is incorporated. 54 55 56 57 REF0 REF1 REF2 REF3 I AVSS 58 CLE I 4 HI2303 Absolute Maximum Ratings TA = 25oC Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range (TSTG). . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (Lead Tips Only) Supply Voltage (AVDD, DVDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V Input Voltage (VIN , All Pins). . . . . . . . . . . . VDD +0.5V to VSS -0.5V Output Voltage (VD, Digital) . . . . . . . . . . . . VDD +0.5V to VSS -0.5V Operating Conditions Supply Voltage: AVDD, AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75V to 5.25V DVDD, DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0V to 5.5V |DVSS , AVSS| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0mV to 100mV Reference Input Voltage: VARB , VBRB , VCRB . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V or More VART, VBRT, VCRT . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7V or Less Analog Input: AIN , BIN , CIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7VP-P or More Clock Pulse Width: tPW1 , tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . 9ns (Min) to 1.1ms (Max) Ambient Temperature (TOPR) . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER ANALOG CHARACTERISTICS Conversion Rate Analog Input Band (-1dB) fC = 50 MSPS, AVDD = 5V, DVDD = 3.0V to 5.0V, VRB = 0.5V, VRT = 2.5V, TA = 25oC SYMBOL DVDD = 3V to 5.5V fC BW AVDD = 4.75V to 5.25V, TA = -20oC to 75oC, VIN = 0.5V to 2.5V, fIN = 1kHz Triangular Wave Envelope RIN = 33Ω -1dB -3dB 0.5 Potential Difference to ART , BRT , CRT Potential Difference to ARB , BRB , CRB NTSC 40 IRE Mod Ramp, fC = 14.3 MSPS -50 0 fIN = 1MHz Sinewave VIN = DC CIN = 10µF tPCW = 2.75µs fCLK = 14.3MHz fCLP = 15.75kHz fIN = 150kHz fIN = 500kHz fIN = 1MHz fIN = 3MHz fIN = 10MHz fIN = 20MHz Ref Data = 00010000 Ref Data = 10000000 60 100 ±0.3 ±0.7 3 1.5 52 50 ±0.5 ±1.5 -10 40 ±1 ±1 MSPS MHz MHz LSB LSB mV mV % Deg dB LSB LSB TEST CONDITIONS MIN TYP MAX UNITS Differential Non-Linearity Error Integral Non-Linearity Error Offset Voltage (Note 2) ED EL EOT EOB End Point Differential Gain Error Differential Phase Error Cross Talk Clamp Offset Voltage DG DP CT EOC Signal To Noise Ratio SNR - 43 42 42 41 38 35 - dB dB dB dB dB dB 5 HI2303 Electrical Specifications PARAMETER Spurious Free Dynamic Range fC = 50 MSPS, AVDD = 5V, DVDD = 3.0V to 5.0V, VRB = 0.5V, VRT = 2.5V, TA = 25oC SYMBOL SFDR fIN = 150kHz fIN = 500kHz fIN = 1MHz fIN = 3MHz fIN = 10MHz fIN = 20MHz DC CHARACTERISTICS Supply Current DVDD = 5V or 3.3V Both Analog Digital Both Analog Digital Reference Current Reference Resistance (VRT to VRB) Self Bias IAD + IDD IAD IDD IAD + IDD IAD IDD IREF RREF VRB For Every Channel For Every Channel Short AVSS and ARBS , BRBS , CRBS NTSC Ramp Wave Input CLE = Low DVDD = 5V DVDD = 3.3V NTSC Ramp Wave Input CLE = High fCLP = 15.75kHz DVDD = 5V DVDD = 3.3V 4.1 260 0.50 1.8 2.2 VI = 0V to AVDD -40 -40 XOE = 0V DVDD = 5V XOE = 0V DVDD = 3.3V XOE = 3V DVDD = 3V to 5.5V VOH = DVDD - 0.8V VOL = 0.4V VOH = DVDD - 0.8V VOL = 0.4V VOH = DVDD VOL = 0V 4 2.4 -40 -40 80 70 5 70 60 5 5.4 370 0.54 1.92 13 16 30 15 100 90 10 90 80 10 7.7 480 0.58 2.04 9 9 11 11 0.8 240 240 -2 -1.2 40 40 mA mA mA mA mA mA mA Ω V V kΩ kΩ kΩ pF pF pF pF pF V V µA µA mA mA mA mA mA mA TEST CONDITIONS MIN TYP 59 59 55 49 44 41 MAX UNITS dB dB dB dB dB dB VRT - VRB Short AVDD and ARTS , BRTS , CRTS Analog Input Resistance RIN VIN fCLK = 50MHz fCLK = 35MHz fCLK = 20MHz Input Capacitance CA11 CA12 CDIN Output Capacitance CAO CDO Digital Input Voltage VIH VIL Digital Input Current IIH IIL Digital Output Current IOH IOL IOH IOL IOZH IOZL AIN , BIN , CIN , VIN = 1.5V + 0.07VRMS ARTS , ART , ARB , ARBS , BRTS , BRT , BRB , BRBS , CRTS , CRT , CRB , CRBS Digital Input Pin AIO , BIO , CIO Digital Output Pin AVDD = 4.75V to 5.25V, DVDD = 3V to 5.5V 6 HI2303 Electrical Specifications PARAMETER Digital Output Voltage fC = 50 MSPS, AVDD = 5V, DVDD = 3.0V to 5.0V, VRB = 0.5V, VRT = 2.5V, TA = 25oC SYMBOL VOH VOL VOH VOL NOTES: 2. The offset voltage EOB is a potential difference between ARB , BRB , CRB and a point of position where the voltage drops equivalent to 1/2 LSB of the voltage when the output data changes from “00000000” to “00000001”. EOR is a potential difference between ART , BRT , CRT and a potential of point where the voltage rises equivalent to 1/2 LSB of the voltage when the output data changes from “11111111” to “11111110”. (2V + E OT -E OB ) of each channel 3. Full scale input ratio = -------------------------------------------------------------------------------------------------------------------------- -1 x100(%) . Average of (2V + E OT -E OB ) of each channel fC = 50 MSPS, AVDD = 5V, DVDD = 5V or 3.3V, VRB = 0.5V, VRT = 2.5V, TA = 25oC PARAMETER Output Data Delay SYMBOL tPLH tPHL tPLH tPHL Three-State Output Enable Time tPZH tPZL tPZH tPZL Three-State Output Disable Time tPHZ tPLZ tPHZ tPLZ Sampling Delay Set-up Time Hold Time Pulse Width Pulse Width tSD tS tH CLP TEST CONDITIONS XOE = 0V DVDD = 5V XOE = 0V DVDD = 3.3V IOH = -2mA IOL = 4mA IOH = -1.2mA IOL = -2.4mA MIN DVDD -0.8 DVDD -0.8 - TYP - MAX 0.4 0.4 UNITS V V V V Timing TEST CONDITIONS CL = 15pF XOE = 0V DVDD = 5V MIN 4.5 4.5 TYP 8.5 7.4 10 6.7 7.1 8.0 8.4 7.2 6.8 6.3 6.8 6.0 -3 - MAX 11 11 13.8 13.8 11.3 11.3 12.8 12.8 9.5 9.5 10.5 10.5 - UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Cycles Cycles DVDD = 3.3V 3.8 3.8 RL = 1kΩ CL = 15PF XOE = 0V → 3V DVDD = 5V 4.2 4.2 DVDD = 3.3V 3.5 3.5 RL = 1kΩ CL = 15pF XOE = 0V → 3V DVDD = 5V 3.6 3.6 DVDD = 3.3V 2.9 2.9 3.5 4.5 2.0 1 SY 7 HI2303 Digital Output The following table shows the relationship between analog input voltage and digital output code. . TABLE 1. I/O CORRESPONDENCE DIGITAL OUTPUT CODE STEP 0 • • 127 128 • • 255 MSB 1111 • • 1000 0000 0111•1111 • • 0000 0000 LSB 1111 INPUT SIGNAL VOLTAGE VART, VBRT, VCRT • • • • • • VARB , VBRB , VCRB Test Circuits MEASUREMENT POINT TO OUTPUT PIN MEASUREMENT POINT CL TO OUTPUT PIN CL RL DVDD RL NOTE: CL includes capacitance of probes. FIGURE 1. OUTPUT DATA DELAY MEASUREMENT CIRCUIT +V FIGURE 2. THREE-STATE MEASUREMENT CIRCUIT S2 S1: ON IF A < B S2: ON IF B > A + +5V - S1 2.5V VDD ART, BRT, CRT AIN A BIN CIN DUT HI2303 B C -V 8 8 8 “0” 8 AB COMPARATOR A8 B8 A1 A0 B1 B0 8 BUFFER + A AIN , BIN , CIN ARB , BRB , CRB “1” 8 000...00 111...10 + V 0.5V CLK GND DVM CLK (50MHz) CONTROLLER FIGURE 3. INTEGRAL NON-LINEARITY ERROR, DIFFERENTIAL NON-LINEARITY ERROR AND OFFSET VOLTAGE TEST CIRCUIT FIGURE 4. ANALOG INPUT RESISTANCE TEST CIRCUIT 8 HI2303 Test Circuits (Continued) HI20201 AIN NTSC SIGNAL SOURCE AMP BIN CIN 100 IAE 0 -40 40 IRE MODULATION BURST SYNC FC S.G. (CW) 0.5V 620 TTL 2.5V -5.2V DUT HI2303 A B C 8 8 8 8 TTL ↓ 8 ECL 620 10-BIT D/A VECTOR SCOPE CLK D.G. D.P. ↓ ECL -5.2V FIGURE 5. DIFFERENTIAL GAIN AND PHASE ERROR vs TEST CIRCUIT VDD 2.5V ART, BAT, CRT AIN , BIN , CIN 0.5V DATA ARB , BRB , CRB OUT CLK OE VSS VOL IOL A 0.5V 2.5V VDD ART, BRT, CRT AIN , BIN , CIN DATA ARB , BRB , CAB OUT CLK IOL A + - OE VSS VOL + - FIGURE 6. DIGITAL OUTPUT TEST CIRCUIT Description of Operation TABLE 2. SETTING VALUES AND OUTPUT FORMATS Digital Output Format The HI2303 supports eight different output formats as detailed in Table 2. For clarity, these formats are labeled mode 0 to 7. The modes are selected via three control pins labeled CTL0, CTL1 and CTL2. The converter has a latency of five clock cycles which places a constraint on the users ability to change the mode on the fly without corrupting the data within the converter. Please refer to Figure 10. The SY pin is used to control mode changes. This is achieved by using the SY as a reset/latch signal. The Mode is reset when the SY is asserted low. When SY transitions from low to high the control pins are latched internally and mode is changed per timing diagram latency. SETTING CTL2 L L L L H H H H CTL1 L L H H L L H H CTLO L H L H L H L H MODE 0 1 2 3 4 5 6 7 4:4:4 4:2:2 (8FS) 4:2:2 (D2) 4:2:2 (Special) 4:1:1 4:1:1 (Special) Simple Boundary, Scan 1 Simple Boundary, Scan 2 OUTPUT FORMAT 9 HI2303 Timing Diagrams tr 4ns tf 4ns 90% 1.3V 10% 2.2V 0.8V tH 0.7VDD DIGITAL OUTPUT 0.3VDD tPLH, tPHL 3V CLOCK INPUT 0V 3V DIGITAL INPUT 0V tS FIGURE 7. tr = 4.5ns 90% OE INPUT 1.3V tf = 4.5ns 3V 10% tPLZ OUTPUT 1 10% tPHZ 90% OUTPUT 2 1.3V tPZH tPZL 0V VOH 1.3V VOL (DVSS) VOH (DVDD) VOL FIGURE 8. TIMING CHART I-2 tPW1 tPW0 CLOCK 1.3V INPUT tSD ANALOG INPUT N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 DIGITAL OUTPUT N-5 N-4 N-3 N-2 N-1 N N+1 N+2 N+3 N+4 N+5 N+6 : ANALOG SIGNAL SAMPLING POINT FIGURE 9. 10 HI2303 Timing Diagrams (Continued) N-5 CLOCK 1.3V INPUT N-4 N-3 N-2 N-1 N N+1 N+2 N+3 N+4 N+5 N+6 SY CTL2 TO CTL0 MODE N 2CLK 5CLK N-8 PROHIBITED FIGURE 10. MODE M 5CLK N-4 N-3 MODE #0 N-2 N-1 N N+1 N+2 DIGITAL OUTPUT N - 10 N-9 MODE N MODE M Mode #0 4:4:4 BIT A73 SAMPLING TIMING (NOTE) ADC CHANNEL ADC CHANNEL A OUTPUT A7 A6 A5 A4 A3 A2 A1 A0 A70 A60 A50 A40 A30 A20 A10 A00 B70 B60 B50 B40 B30 B20 B10 B00 C70 C60 C50 C40 C30 C20 C10 C00 Low A71 A61 A51 A41 A31 A21 A11 A01 B71 B61 B51 B41 B31 B21 B11 B01 C71 C61 C51 C41 C31 C21 C11 C01 A72 A62 A52 A42 A32 A22 A12 A02 B72 B62 B52 B42 B32 B22 B12 B02 C72 C62 C52 C42 C32 C22 C12 C02 A73 A63 A53 A43 A33 A23 A13 A03 B73 B63 B53 B43 B33 B23 B13 B03 C73 C63 C53 C43 C33 C23 C13 C03 DATA A74 A64 A54 A44 A34 A24 A14 A04 B74 B64 B54 B44 B34 B24 B14 B04 C74 C64 C54 C44 C34 C24 C14 C04 A75 A65 A55 A45 A35 A25 A15 A05 B75 B65 B55 B45 B35 B25 B15 B05 C75 C65 C55 C45 C35 C25 C15 C05 A76 A66 A56 A46 A36 A26 A16 A06 B76 B66 B56 B46 B36 B26 B16 B06 C76 C66 C56 C46 C36 C26 C16 C06 A77 A67 A57 A47 A37 A27 A17 A07 B77 B67 B57 B47 B37 B27 B17 B07 C77 C67 C57 C47 C37 C27 C17 C07 B B7 B6 B5 B4 B3 B2 B1 B0 C C7 C6 C5 C4 C3 C2 C1 C0 TGR NOTE: See Figure 9. 11 HI2303 Mode #2 4:2:2 (D2) BIT A73 SAMPLING TIMING (NOTE) ADC CHANNEL ADC CHANNEL A OUTPUT A7 A6 A5 A4 A3 A2 A1 A0 A70 A60 A50 A40 A30 A20 A10 A00 B70 B60 B50 B40 B30 B20 B10 B00 HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HIGH LOW HIGH LOW A71 A61 A51 A41 A31 A21 A11 A01 C70 C60 C50 C40 C30 C20 C10 C00 A72 A62 A52 A42 A32 A22 A12 A02 B72 B62 B52 B42 B32 B22 B12 B02 A73 A63 A53 A43 A33 A23 A13 A03 C72 C62 C52 C42 C32 C22 C12 C02 DATA A74 A64 A54 A44 A34 A24 A14 A04 B74 B64 B54 B44 B34 B24 B14 B04 A75 A65 A55 A45 A35 A25 A15 A05 C74 C64 C54 C44 C34 C24 C14 C05 A76 A66 A56 A46 A36 A26 A16 A06 B76 B66 B56 B46 B36 B26 B16 B06 A77 A67 A57 A47 A37 A27 A17 A07 C76 C66 C56 C46 C36 C26 C16 C06 B B7 B6 B5 B4 B3 B2 B1 B0 C C7 C6 C5 C4 C3 C2 C1 C0 TGR HIGH LOW HIGH LOW HiZ: High Impedance NOTE: See Figure 9. 12 HI2303 Mode #3 4:2:2 (Special) BIT A73 SAMPLING TIMING (NOTE) ADC CHANNEL ADC CHANNEL A OUTPUT A7 A6 A5 A4 A3 A2 A1 A0 A70 A60 A50 A40 A30 A20 A10 A00 B70 B60 B50 B40 B30 B20 B10 B00 HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HIGH LOW HIGH LOW A71 A61 A51 A41 A31 A21 A11 A01 C71 C61 C51 C41 C31 C21 C11 C01 A72 A62 A52 A42 A32 A22 A12 A02 B72 B62 B52 B42 B32 B22 B12 B02 A73 A63 A53 A43 A33 A23 A13 A03 C73 C63 C53 C43 C33 C23 C13 C03 DATA A74 A64 A54 A44 A34 A24 A14 A04 B74 B64 B54 B44 B34 B24 B14 B04 A75 A65 A55 A45 A35 A25 A15 A05 C75 C65 C55 C45 C35 C25 C15 C05 A76 A66 A56 A46 A36 A26 A16 A06 B76 B66 B56 B46 B36 B26 B16 B06 A77 A67 A57 A47 A37 A27 A17 A07 C77 C67 C57 C47 C37 C27 C17 C07 B B7 B6 B5 B4 B3 B2 B1 B0 C C7 C6 C5 C4 C3 C2 C1 C0 TGR HIGH LOW HIGH LOW HiZ: High Impedance NOTE: See Figure 9. 13 HI2303 Mode #1 4:2:2 (8FS) BIT A73 SAMPLING TIMING (NOTE) ADC CHANNEL ADC CHANNEL A OUTPUT A7 A6 A5 A4 A3 A2 A1 A0 A70 A60 A50 A40 A30 A20 A10 A00 B70 B60 B50 B40 B30 B20 B10 B00 B70 B60 B50 B40 B30 B20 B10 B00 HIGH A70 A60 A50 A40 A30 A20 A10 A00 B70 B60 B50 B40 B30 B20 B10 B00 A70 A60 A50 A40 A30 A20 A10 A00 LOW A72 A62 A52 A42 A32 A22 A12 A02 C70 C60 C50 C40 C30 C20 C10 C00 C70 C60 C50 C40 C30 C20 C10 C00 A72 A62 A52 A42 A32 A22 A12 A02 C70 C60 C50 C40 C30 C20 C10 C00 A72 A62 A52 A42 A32 A22 A12 A02 DATA A74 A64 A54 A44 A34 A24 A14 A04 B74 B64 B54 B44 B34 B24 B14 B04 B74 B64 B54 B44 B34 B24 B14 B04 HIGH A74 A64 A54 A44 A34 A24 A14 A04 B74 B64 B54 B44 B34 B24 B14 B04 A74 A64 A54 A44 A34 A24 A14 A04 LOW A76 A66 A56 A46 A36 A26 A16 A06 C74 C64 C54 C44 C34 C24 C14 C04 C74 C64 C54 C44 C34 C24 C14 C04 A76 A66 A56 A46 A36 A26 A16 A06 C74 C64 C54 C44 C34 C24 C14 C04 A76 A66 A56 A46 A36 A26 A16 A06 B B7 B6 B5 B4 B3 B2 B1 B0 C C7 C6 C5 C4 C3 C2 C1 C0 TGR NOTE: See Figure 9. 14 HI2303 Mode #4 4:1:1 BIT A73 SAMPLING TIMING (NOTE) ADC CHANNEL ADC CHANNEL A OUTPUT A7 A6 A5 A4 A3 A2 A1 A0 A70 A60 A50 A40 A30 A20 A10 A00 B70 B60 C10 C60 HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HIGH LOW HiZ: High Impedance A71 A61 A51 A41 A31 A21 A11 A01 B60 B40 C50 C40 A72 A62 A52 A42 A32 A22 A12 A02 B30 B20 C30 C20 A73 A63 A53 A43 A33 A23 A13 A03 B10 B00 C10 C00 DATA A74 A64 A54 A44 A34 A24 A14 A04 B74 B64 C74 C64 A75 A65 A55 A45 A35 A25 A15 A05 B54 B44 C54 C44 A76 A66 A56 A46 A36 A26 A16 A06 B34 B24 C34 C24 A77 A67 A57 A47 A37 A27 A17 A07 B14 B04 C14 C04 B B7 B6 B5 B4 B3 B2 B1 B0 C C7 C6 C5 C4 C3 C2 C1 C0 TGR HIGH LOW NOTE: See Figure 9. 15 HI2303 Mode #5 4:1:1 (Special) BIT A73 SAMPLING TIMING (NOTE) ADC CHANNEL ADC CHANNEL A OUTPUT A7 A6 A5 A4 A3 A2 A1 A0 A70 A60 A50 A40 A30 A20 A10 A00 B30 B20 B10 B00 HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HIGH LOW HiZ: High Impedance A71 A61 A51 A41 A31 A21 A11 A01 B70 B60 B50 B40 A72 A62 A52 A42 A32 A22 A12 A02 C32 C22 C12 C02 A73 A63 A53 A43 A33 A23 A13 A03 C72 C62 C52 C42 DATA A74 A64 A54 A44 A34 A24 A14 A04 B34 B24 B14 B04 A75 A65 A55 A45 A35 A25 A15 A05 B74 B64 B54 B44 A76 A66 A56 A46 A36 A26 A16 A06 C36 C26 C16 C06 A77 A67 A57 A47 A37 A27 A17 A07 C76 C66 C56 C46 B B7 B6 B5 B4 B3 B2 B1 B0 C C7 C6 C5 C4 C3 C2 C1 C0 TGR HIGH LOW NOTE: See Figure 9. 16 HI2303 Mode #6, #7 - Simple Boundary Scan 1 and Scan 2 The HI2303 has a simple boundary scan function. TABLE 3. SIMPLE BOUNDARY SCAN OUTPUT DATA BITS A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0 MODE #6 H L H L H L H L MODE #7 L H L H L H L H NOTE: CLK and SY must be set. Clamp Function The following two points should be noted when using the digital clamp circuit. - The clamp pulse must be supplied externally. - The clamp circuit is not designed for V cycle clamping. 16 different reference levels can be selected for the digital clamp circuit through a combination of the REF0, REF1, REF2 and REF3 inputs as shown in the table below. Note that the REF0, REF1, REF2 and REF3 input signals are fetched asynchronously with the clock input signal. A IN ( pedestal ) = V RB + ( Binary Code * LSB ) + E OB TABLE 4. SETTING VALUES AND REFERENCE LEVEL SETTING REFERENCE LEVEL CHANNEL A REF3 L L L L L L L L H H H H H H H H REF2 L L L L H H H H L L L L H H H H REF1 L L H H L L H H L L H H L L H H REF0 L H L H L H L H L H L H L H L H MODE 0 1 2 3 4 5 6 7 8 9 A B C D E F DECIMAL 16 32 48 64 1 16 32 48 239 223 207 191 254 239 223 207 BINARY 00010000 00100000 00110000 01000000 00000001 00010000 00100000 00110000 11101111 11011111 11001111 10111111 11111110 11101111 11011111 11001111 CHANNELS B AND C DECIMAL 128 128 128 128 1 16 32 48 127 127 127 127 254 239 223 207 BINARY 10000000 10000000 10000000 10000000 00000001 00010000 00100000 00110000 01111111 01111111 01111111 01111111 11111110 11101111 11011111 11001111 17 HI2303 Metric Plastic Quad Flatpack Packages (MQFP/PQFP) D D1 Q80.14x20-S 80 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE INCHES SYMBOL A A1 B MIN 0.103 0.002 0.010 0.926 0.784 0.689 0.548 0.024 80 0.032 BSC 24 16 MAX 0.122 0.011 0.019 0.956 0.803 0.720 0.566 0.039 MILLIMETERS MIN 2.60 0.05 0.25 23.50 19.90 17.50 13.90 0.60 80 0.80 BSC 24 16 MAX 3.10 0.30 0.50 24.30 20.40 18.30 14.40 1.00 NOTES 5 2 3, 4 2 3, 4 6 Rev. 0 5/97 0.10 0.004 -C0.24 M B E E1 D D1 E E1 e PIN 1 SEATING PLANE L N e ND -H- A NE NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. Dimensions D and E to be determined at seating plane -C- . 3. Dimensions D1 and E1 to be determined at datum plane -H- . 4. Dimensions D1 and E1 do not include mold protrusion. 5. Dimension B does not include dambar protrusion. 6. “N” is the number of terminal positions. 0o-10o A1 L 0.100/0.250 0.004/0.010 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: () 724-7000 FAX: () 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 18