HI3-5701K-5

HI-5701 Data Sheet June 1999 File Number 2937.8 6-Bit, 30MSPS, Flash A/D Converter The HI-5701 is a monolithic, 6-bit, CMOS flash Analog-toDigital Converter. It is designed for high speed applications where wide bandwidth and low power consumption are essential. Its 30MSPS speed is made possible by a parallel architecture which also eliminates the need for an external sample and hold circuit. The HI-5701 delivers ±0.7 LSB differential nonlinearity while consuming only 250mW (Typ) at 30MSPS. Microprocessor compatible data output latches are provided which present valid data to the output bus 1.5 clock cycles after the convert command is received. An overflow bit is provided to allow the series connection of two converters to achieve 7-bit resolution. The HI-5701 is available in Commercial and Industrial temperature ranges and is supplied in 18 lead Plastic DIP and SOIC packages Features • 30MSPS with No Missing Codes • Full Power Input Bandwidth . . . . . . . . . . . . . . . . . . 20MHz • No Missing Codes Over Temperature • Sample and Hold Not Required • Single Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . +5V • Power Dissipation (Max). . . . . . . . . . . . . . . . . . . . .300mW • CMOS/TTL Compatible • Overflow Bit • /883 Version Available Applications • Video Digitizing • Radar Systems Ordering Information PART NUMBER HI3-5701K-5 HI9P5701K-5 HI3-5701B-9 HI9P5701B-9 HI5701-EV TEMP. RANGE (oC) 0 to 70 0 to 70 -40 to 85 -40 to 85 25 PACKAGE 18 Ld PDIP 18 Ld SOIC 18 Ld PDIP 18 Ld SOIC Evaluation Board PKG. NO. E18.3 M18.3 E18.3 M18.3 • Communication Systems • High Speed Data Acquisition Systems Pinout HI-5701 (PDIP, SOIC) TOP VIEW D5 (MSB) OVF VSS NC CE2 CE1 CLK PHASE VREF + 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 D4 D3 1/ R 2 D2 D1 D0 (LSB) VDD VIN VREF - 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HI-5701 Functional Block Diagram φ1 φ2 φ1 φ1 φ2 VIN R/2 VREF + COMP 64 R D Q CL D5 (MSB) D Q CL OVERFLOW (OVF) R COMP 63 R 1/ R 2 D Q CL D4 R COMP 32 R COMPARATOR LATCHES AND 63 TO 6 ENCODER LOGIC D Q CL D3 D Q CL D2 R COMP 2 D Q CL D1 VREF R/2 COMP 1 D Q CL D0 (LSB) CE1 CE2 CLOCK φ2 (SAMPLE) φ1 (AUTO BALANCE) VDD VSS PHASE 2 HI-5701 Absolute Maximum Ratings Supply Voltage, VDD to VSS . . . . . . . . . . . (VSS - 0.5) < VDD < +7V Analog and Reference Input Pins (VSS - 0.5) < VINA < (VDD +0.5V) Digital I/O Pins . . . . . . . . . . . . . . . .(VSS - 0.5) < VI/O < (VDD +0.5V) Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Maximum Power Dissipation at 70oC (Note 2) . . . . . . . . . . .635mW Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range HI3-5701-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC HI9P5701-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on an evaluation PC board in free air. 2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. Electrical Specifications VDD = +5.0V; VREF + = +4.0V; VREF- = VSS = GND; fS = Specified Clock Frequency at 50% Duty Cycle; CL = 30pF; Unless Otherwise Specified (NOTE 3) 0oC TO 70oC -40oC TO 85oC MAX MIN MAX UNITS 25oC PARAMETER SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL (Best Fit Line) Differential Linearity Error, DNL (Guaranteed No Missing Codes) Offset Error, VOS (Adjustable to Zero) Full Scale Error, FSE (Adjustable to Zero) DYNAMIC CHARACTERISTICS Maximum Conversion Rate Minimum Conversion Rate Full Power Input Bandwidth Signal to Noise Ratio, SNR RMS Signal = -------------------------------RMS Noise Signal to Noise Ratio, SINAD RMS Signal = ------------------------------------------------------------RMS Noise + Distortion Total Harmonic Distortion No Missing Codes No Missing Codes (Note 3) fS = 30MHz fS = 1MHz, fIN = 100kHz fS = 30MHz, fIN = 4MHz 30 40 20 36 31 0.125 fS = 20MHz fS = 30MHz fS = 20MHz fS = 30MHz fS = 20MHz (Note 3) fS = 30MHz fS = 20MHz (Note 3) fS = 30MHz 6 ±0.5 ±1.5 ±0.3 ±0.7 ±0.5 ±0.5 ±0.25 ±0.25 ±1.25 ±0.6 ±2.0 ±2.0 TEST CONDITIONS MIN TYP 6 - ±2.0 ±0.75 Bits LSB LSB LSB LSB ±2.5 ±2.5 - LSB LSB LSB LSB 30 - 0.125 - MSPS MSPS MHz dB dB fS = 1MHz, fIN = 100kHz fS = 30MHz, fIN = 4MHz fS = 1MHz, fIN = 100kHz fS = 30MHz, fIN = 4MHz - 35 30 - - - dB dB - -44 -38 2 2 - - - dBc dBc % Degree Differential Gain Differential Phase fS = 14.32MHz, fIN = 3.58MHz fS = 14.32MHz, fIN = 3.58MHz 3 HI-5701 Electrical Specifications VDD = +5.0V; VREF + = +4.0V; VREF- = VSS = GND; fS = Specified Clock Frequency at 50% Duty Cycle; CL = 30pF; Unless Otherwise Specified (Continued) (NOTE 3) 0oC TO 70oC -40oC TO 85oC MAX MIN MAX UNITS 25oC PARAMETER ANALOG INPUTS Analog Input Resistance, RIN Analog Input Capacitance, CIN Analog Input Bias Current, IB REFERENCE INPUTS Total Reference Resistance, RL Reference Resistance Tempco, TC DIGITAL INPUTS Input Logic High Voltage, VIH Input Logic Low Voltage, VIL Input Logic High Current, IIH Input Logic Low Current, IIL Input Capacitance, CIN DIGITAL OUTPUTS Output Logic Sink Current, IOL Output Logic Source Current, IOH Output Leakage, IOFF Output Capacitance, COUT TIMING CHARACTERISTICS Aperture Delay, tAP Aperture Jitter, tAJ Data Output Enable Time, tEN Data Output Disable Time, tDIS Data Output Delay, tOD Data Output Hold, tH POWER SUPPLY REJECTION Offset Error PSRR, ∆VOS Gain Error PSRR, ∆FSE POWER SUPPLY CURRENT Supply Current, IDD NOTE: 3. Parameter guaranteed by design or characterization and not production tested. fS = 20MHz 50 60 VDD = 5V ±10% VDD = 5V ±10% ±0.1 ±0.1 ±1.0 ±1.0 (Note 3) (Note 3) (Note 3) (Note 3) 5 6 30 12 11 14 10 20 20 20 VO = 0.4V VO = 4.5V CE2 = 0V CE2 = 0V 3.2 -3.2 5.0 ±1.0 VIN = 5V VIN = 0V 2.0 7 0.8 1.0 1.0 250 370 +0.266 VIN = 4V VIN = 0V VIN = 0V, 4V 30 20 0.01 ±1.0 TEST CONDITIONS MIN TYP - ±1.0 MΩ pF µA 235 - - Ω Ω/oC 2.0 - 0.8 1.0 1.0 - V V µA µA pF 3.2 ±1.0 - mA mA µA pF -3.2 - 5 20 20 20 - ns ps ns ns ns ns - ±1.5 ±1.5 LSB LSB - 75 mA 4 HI-5701 Timing Waveforms COMPARATOR DATA IS LATCHED CLOCK INPUT PHASE - HIGH ENCODED DATA IS LATCHED INTO THE OUTPUT REGISTERS φ2 φ1 φ2 φ1 φ2 φ1 φ2 φ1 φ2 CLOCK INPUT PHASE - LOW SAMPLE N-2 AUTO BALANCE tAB SAMPLE N-1 tS AUTO BALANCE SAMPLE N AUTO BALANCE SAMPLE N+1 AUTO BALANCE SAMPLE N+2 ANALOG INPUT tAP tAJ tH tOD DATA OUTPUT DATA N - 4 DATA N - 3 DATA N - 2 DATA N - 1 DATA N FIGURE 1. INPUT-TO-OUTPUT TIMING CE1 CE2 tDIS tEN tDIS tEN D0 - D5 DATA HIGH IMPEDANCE DATA HIGH IMPEDANCE DATA OVF DATA HIGH IMPEDANCE DATA FIGURE 2. OUTPUT ENABLE TIMING 5 HI-5701 Typical Performance Curves 6 fS = 20MHz EFFECTIVE BITS EFFECTIVE BITS 6 fS = 1MHz, fIN = 100kHz 5 fS = 30MHz, fIN = 4MHz 5 fS = 30MHz fS = 40MHz 4 VDD = 5V, VREF + = 4V TA = 25oC 3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 INPUT FREQUENCY (fIN) - MHz 4 VDD = 5V, VREF + = 4V 3 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (oC) FIGURE 3. EFFECTIVE NUMBER OF BITS vs fIN 38 VDD = 5V, VREF + = 4V 36 34 32 dBc dB -40 -42 30 28 26 24 -40 -30 -20 -10 fS = 30MHz, fIN = 4MHz fS = 1MHz, fIN = 100kHz -36 -38 FIGURE 4. ENOB vs TEMPERATURE -34 fS = 30MHz, fIN = 4MHz VDD = 5V, VREF + = 4V fS = 1MHz, fIN = 100kHz -44 -46 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (oC) TEMPERATURE (oC) FIGURE 5. SNR vs TEMPERATURE FIGURE 6. TOTAL HARMONIC DISTORTION vs TEMPERATURE 2 fIN = 100kHz VDD = 5V, VREF + = 4V 1.5 1 fIN = 100kHz VDD = 5V, VREF + = 4V 0.75 LSBs LSBs fS = 30MHz 1 fS = 30MHz 0.5 0.5 fS = 1MHz 0 -40 -30 -20 -10 0.25 fS = 1MHz 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (oC) TEMPERATURE (oC) FIGURE 7. INL vs TEMPERATURE FIGURE 8. DNL vs TEMPERATURE 6 HI-5701 Typical Performance Curves 1 VDD = 5V ±10%, VREF + = 4V 0.5 IDD (mA) PSRR VOS LSBs 0 PSRR FSE -0.5 (Continued) 60 55 50 45 40 35 30 25 20 15 fS = 1MHz fS = 20MHz VDD = 5V, VREF + = 4V -1 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 10 -40 -20 0 20 40 60 80 100 TEMPERATURE (oC) TEMPERATURE (oC) FIGURE 9. POWER SUPPLY REJECTION vs TEMPERATURE FIGURE 10. SUPPLY CURRENT vs TEMPERATURE 60 55 50 EFFECTIVE BITS 45 IDD (mA) 40 35 30 25 20 15 10 0.1 1 10 100 t AB D = ----------------------t AB + t S D = 25% VDD = 5V, VREF + = 4V TA = 25oC D = 50% 6.0 fI = 1MHz 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 30 40 50 60 CLOCK FREQUENCY (MHz) CLOCK FREQUENCY (MHz) D = 10% FIGURE 11. SUPPLY CURRENT vs CLOCK AND DUTY CYCLE FIGURE 12. EFFECTIVE NUMBER OF BITS vs CLOCK FREQUENCY 7 HI-5701 TABLE 1. PIN DESCRIPTIONS PIN # 1 2 3 4 5 6 7 8 NAME D5 OVF VSS NC CE2 CE1 CLK PHASE DESCRIPTION Bit 6, Output (MSB). Overflow, Output. Digital Ground. No Connection. Three-State Output Enable Input, Active High (See Table 2). Three-State Output Enable Input, Active Low (See Table 2). Clock Input. Sample Clock Phase Control Input. When Phase is Low, Sample Unknown (φ1) Occurs When the Clock is Low and Auto Balance (φ2) Occurs When the Clock is High (See Text). Reference Voltage Positive Input. Reference Voltage Negative Input. Analog Signal Input. Power Supply, +5V. Bit 1, Output (LSB). Bit 2, Output. Bit 3, Output. Reference Ladder Midpoint. Bit 4, Output. Bit 5, Output. eliminated during operation. The block diagram and timing diagram illustrate how the HI-5701 CMOS flash converter operates. The input clock which controls the operation of the HI-5701 is first split into a non-inverting φ1 clock and an inverting φ2 clock. These two clocks, in turn, synchronize all internal timing of analog switches and control logic within the converter. In the “Auto Balance” mode (φ1), all φ1 switches close and φ2 switches open. The output of each comparator is momentarily tied to its own input, self-biasing the comparator midway between VSS and VDD and presenting a low impedance to a small input capacitor. Each capacitor, in turn, is connected to a reference voltage tap from the resistor ladder. The Auto Balance mode quickly precharges all 64 input capacitors between the self-bias voltage and each respective tap voltage. In the “Sample” mode (φ2), all φ1 switches open and φ2 switches close. This places each comparator in a sensitive high gain amplifier configuration. In this open loop state, the input impedance is very high and any small voltage shift at the input will drive the output either high or low. The φ2 state also switches each input capacitor from its reference tap to the input signal. This instantly transfers any voltage difference between the reference tap and input voltage to the comparator input. All 64 comparators are thus driven simultaneously to a defined logic state. For example, if the input voltage is at mid-scale, capacitors precharged near zero during φ1 will push comparator inputs higher than the self bias voltage at φ2; capacitors precharged near the reference voltage push the respective comparator inputs lower than the bias point. In general, all capacitors precharged by taps above the input voltage force a “low” voltage at comparator inputs; those precharged below the input voltage force “high” inputs at the comparators. During the next φ1 state, comparator output data is latched into the encoder logic block and the first stage of encoding takes place. The following φ2 state completes the encoding process. The 6 data bits (plus overflow bit) are latched into the output flip-flops at the next falling clock edge. The Overflow bit is set if the input voltage exceeds VREF + - 1/2 LSB. The output bus may be either enabled or disabled according to the state of CE1 and CE2 (See Table 2). When disabled, output bits assume a high impedance state. As shown in the timing diagram, the digital output word becomes valid after the second φ1 state. There is thus a one and a half cycle pipeline delay between input sample and digital output. “Data Output Delay” time indicates the slight time delay for data to become valid at the end of the φ1 state. Refer to the Glossary of Terms for other definitions. 9 10 11 12 13 14 15 16 17 18 VREF + VREF VIN VDD D0 D1 D2 1/ R2 2 D3 D4 TABLE 2. CHIP ENABLE TRUTH TABLE CE1 0 1 X X = Don’t Care CE2 1 1 0 Valid Three-State Three-State D0 - D5 Valid Valid Three-State OVF Theory of Operation The HI-5701 is a 6-bit analog-to-digital converter based on a parallel CMOS “flash” architecture. This flash technique is an extremely fast method of A/D conversion because all bit decisions are made simultaneously. In all, 64 comparators are used in the HI-5701; 63 comparators to encode the output word, plus an additional comparator to detect an overflow condition. The CMOS HI-5701 works by alternately switching between a “Sample” mode and an “Auto Balance” mode. Splitting up the comparison process in this CMOS technique offers a number of significant advantages. The offset voltage of each CMOS comparator is dynamically canceled with each conversion cycle such that offset voltage drift is virtually 8 HI-5701 D5 OVF VSS D4 D3 1/2R D2 D1 D0 VDD 0.01µF 10µF +9V to +12V 0.01µF 10µF +5V NC DATA OUPUT +5V CE2 CE1 CLOCK INPUT CLK 50Ω PHASE VIN 100Ω HA-5033 50Ω ANALOG SIGNAL INPUT +4V 10µF 0.01µF VREF+ VREF0.01µF -9V to -12V 10µF FIGURE 13. TEST CIRCUIT Application Information Voltage Reference The reference voltage is applied across the resistor ladder at the input of the converter, between VREF + and VREF -. In most applications, VREF - is simply tied to analog ground such that the reference source drives VREF +. The reference must be capable of supplying enough current to drive the minimum ladder resistance of 235Ω over temperature. The HI-5701 is specified for a reference voltage of 4.0V, but will operate with voltages as high as the VDD supply. In the case of 4.0V reference operation, the converter encodes the analog input into a binary output in LSB increments of (VREF + -VREF )/64, or 62.5mV. Reducing the reference voltage reduces the LSB size proportionately and thus increases linearity errors. The minimum practical reference voltage is about 2V. Because the reference voltage terminals are subjected to internal transient currents during conversion, it is important to drive the reference pins from a low impedance source and to decouple thoroughly. Again, ceramic and tantalum (0.01µF and 10µF) capacitors near the package pin are recommended. It is not necessary to decouple the 1/2R tap point pin for most applications. It is possible to elevate VREF - from ground if necessary. In this case, the VREF - pin must be driven from a low impedance reference capable of sinking the current through the resistor ladder. Careful decoupling is again recommended. clock and phase inputs control the sample and auto balance modes. The digital outputs change state on the clock phase which begins the sample mode. Two chip enable inputs control the three-state outputs of output bits D0 through D5 and the Overflow OVF bit. As indicated in Table 2, all output bits are high impedance when CE2 is low, and output bits D0 through D5 are independently controlled by CE1. Although the Digital Outputs are capable of handling typical data bus loading, the bus capacitance charge/discharge currents will produce supply and local ground disturbances. Therefore, an external bus driver is recommended. Clock The clock should be properly terminated to digital ground near the clock input pin. Clock frequency defines the conversion frequency and controls the converter as described in the “Theory of Operation” section. The Auto Balance φ1 half cycle of the clock may be reduced to 16ns; the Sample φ2 half cycle may be varied from a minimum of 16ns to a maximum of 8µs. TABLE 3. PHASE CONTROL CLOCK 0 0 1 1 PHASE 0 1 0 1 INTERNAL GENERATION Sample Unknown (φ2) Auto Balance (φ1) Auto Balance (φ1) Sample Unknown (φ2) Digital Control and Interface The HI-5701 provides a standard high speed interface to external CMOS and TTL logic families. Four digital inputs are provided to control the function of the converter. The 9 Gain and Offset Adjustment In applications where accuracy is of utmost importance, three adjustments can be made; i.e., offset, gain, and HI-5701 midpoint trim. In general, offset and gain correction can be done in the preamp circuitry. Signal Source A current pulse is present at the analog input (VIN) at the beginning of every sample and auto balance period. The transient current is due to comparator charging and switch feed through in the capacitor array. It varies with the amplitude of the analog input and the sampling rate. The signal source must be capable of recovering from the transient prior to the end of the sample period to ensure a valid signal for conversion. Suitable broad band amplifiers or buffers which exhibit low output impedance and high output drive include the HFA-0005, HA-5004, HA-5002, and HA5033. The signal source may drive above or below the power supply rails, but should not exceed 0.5V beyond the rails or damage may occur. Input voltages of -0.5V to +1/2 LSB are converted to all zeros; input voltages of VREF + - 1/2 LSB to VDD + 0.5 are converted to all ones with the Overflow bit set. Offset Adjustment The preferred offset correction method is to introduce a DC component to VIN of the converter. An alternate method is to adjust the VREF - input to produce the desired offset adjustment. The theoretical input voltage to produce the first transition is 1/2 LSB. VIN (0 to 1 transition) = 1/2 LSB = 1/2(VREF/64) = VREF/128. Gain Adjustment In general, full scale error correction can be done in the preamp circuitry by adjusting the gain of the op amp. An alternate method is to adjust the VREF + input voltage. This adjustment is performed by setting VIN to the 63 to overflow transition. The theoretical input voltage to produce the transition is 1/2 LSB less than VREF + and is calculated as follows: VIN (63 to 64 transition) = VREF - (VREF /128) = VREF (127/128). To perform the gain trim, first do the offset trim and then apply the required VIN for the 63 to overflow transition. Now adjust VREF + until that transition occurs on the outputs. Power Supply The HI-5701 operates nominally from a 5V supply, but will function from 3V to 6V. The supply should be well regulated and “clean” of significant noise, especially high frequency noise. It is recommended that power supply decoupling capacitors be placed as close to the supply pin as possible. A combination of 0.01µF ceramic and 10µF tantalum capacitors is recommended for this purpose as shown in the test circuit Figure 13. Midpoint Trim The reference center (1/2R) is available to the user as the midpoint of the resistor ladder. The 1/2 R point can be used to improve linearity or create unique transfer functions. The offset and gain trims should be done prior to adjusting the midpoint. The theoretical transition from count 31 to 32 occurs at 31.5 LSBs. That voltage is calculated as follows: VIN (31 to 32 transition) = 31.5(VREF/64) = VREF(63/128). An adjustable voltage follower can be used to drive the 1/2 R pin. Set VIN to the 31 to 32 transition voltage, then adjust the voltage follower until the transition occurs on the output bits. Reducing Power Consumption Power dissipation in the HI-5701 is related to clock frequency and clock duty cycle. For a fixed 50% clock duty cycle, power may be reduced by lowering the clock frequency. For a given conversion frequency, power may be reduced by shortening the Auto Balance φ1 portion of the clock duty cycle. TABLE 4. OUTPUT CODE TABLE INPUT VOLTAGE† VREF + = 4V VREF - = 0V (V) 4.000 3.9063 3.8438 • • 2.9688 • • • BINARY OUTPUT CODE DECIMAL COUNT 127 63 62 MSB OVF 1 0 0 D5 1 1 1 D4 1 1 1 D3 1 1 1 • • • 0 • • • D2 1 1 1 D1 1 1 1 LSB D0 1 1 0 CODE DESCRIPTION Overflow (OVF) Full Scale (FS) FS - 1 LSB 3/ F S 4 48 0 1 1 0 0 0 10 HI-5701 TABLE 4. OUTPUT CODE TABLE (Continued) INPUT VOLTAGE† VREF + = 4V VREF - = 0V (V) 1.9688 • • • 0.9688 • • • 0.0313 0 BINARY OUTPUT CODE DECIMAL COUNT 32 MSB OVF 0 D5 1 D4 0 D3 0 • • • 0 • • • 0 0 D2 0 D1 0 LSB D0 0 CODE DESCRIPTION 1/ F S 2 1/ F S 4 16 0 0 1 0 0 0 1 LSB Zero 1 0 0 0 0 0 0 0 0 0 0 0 1 0 † The voltages listed above represent the ideal transition of each output code shown as a function of the reference voltage. Glossary of Terms Aperture Delay - is The time delay between the external sample command (the rising edge of the clock) and the time at which the signal is actually sampled. This delay is due to internal clock path propagation delays. Aperture Jitter, tAJ - This is the RMS variation in the aperture delay due to variation of internal φ1 and φ2 clock path delays and variation between the individual comparator switching times. Differential Linearity Error, DNL - The differential linearity error is the difference in LSBs between the spacing of the measured midpoint of adjacent codes and the spacing of ideal midpoints of adjacent codes. The ideal spacing of each midpoint is 1 LSB. The range of values possible is from -1 LSB (which implies a missing code) to greater than +1 LSB. Full Power Input Bandwidth - Full power bandwidth is the frequency at which the amplitude of the fundamental of the digital output word has decreased 3dB below the amplitude of an input sine wave. The input sine wave has a peak-topeak amplitude equal to the reference voltage. The bandwidth given is measured at the specified sampling frequency. Full Scale Error, FSE - is The difference between the actual input voltage of the 63 to 64 code transition and the ideal value of VREF + - 1.5 LSB. This error is expressed in LSBs. Integral Linearity Error, INL - The integral linearity error is the difference in LSBs between the measured code centers and the ideal code centers. The ideal code centers are calculated using a best fit line through the converter’s transfer function. LSB - Least Significant Bit = (VREF + - VREF -)/64. All HI-5701 specifications are given for a 62.5mV LSB size VREF + = 4V, VREF - = 0V. Offset Error, VOS - Offset error is the difference between the actual input voltage of the 0 to 1 code transition and the ideal value of VREF - + 0.5 LSB. VOS error is expressed in LSBs. Power Supply Rejection Ratio, PSRR - Is expressed in LSBs and is the maximum shift in code transition points due to a power supply voltage shift. This is measured at the 0 to 1 code transition point and the 62 to 63 code transition point with a power supply voltage shift from the nominal value of 5.0V. Signal to Noise Ratio, SNR - SNR is the ratio in dB of the RMS signal to RMS noise at specified input and sampling frequencies. Signal to Noise and Distortion Ratio, SINAD - Is the ratio in dB of the RMS signal to the RMS sum of the noise and harmonic distortion at specified input and sampling frequencies. Total Harmonic Distortion, THD - Is the ratio in dBc of the RMS sum of the first five harmonic components to the RMS signal for a specified input and sampling frequency 11 HI-5701 Die Characteristics DIE DIMENSIONS: 86.6 mils x 130.7 mils x 19 mils ±1 mil METALLIZATION: Type: SiAl Thickness: 11kÅ ±1kÅ PASSIVATION: Type: SiO2 Thickness: 8kÅ ±1kÅ WORST CASE CURRENT DENSITY: