HI3026A

HI3026A August 1997 8-Bit, 140 MSPS, Flash A/D Converter Description The HI3026A is an 8-bit, high-speed, flash analog-to-digital converter optimized for high speed, low power, and ease of use. With a 140 MSPS encode rate capability and full-power analog bandwidth of 150MHz, this component is ideal for applications requiring the highest possible dynamic performance. To minimize system cost and power dissipation, only a +5V power supply is required. The HI3026A’s clock input interfaces directly to TTL, ECL, or PECL logic and will operate with singleended inputs. The user may select 16-bit demultiplexed output or 8-bit single-channel digital outputs. The demultiplexed mode interleaves the data through two 8-bit channels at 1/2 the clock rate. Operation in demultiplexed mode reduces the speed and cost of external digital interfaces, while allowing the A/D converter to be clocked to the full 140 MSPS conversion rate. Fabricated with an advanced bipolar process, the HI3026A is provided in a space-saving 48-lead MQFP surface mount plastic package and is specified over the -20oC to 75oC temperature range. Features • Differential Linearity Error . . . . . . . . . . . . . . . ±0.5 LSB • Integral Linearity Error . . . . . . . . . . . . . . . . . . ±0.5 LSB • Integral Linearity Compensation Circuit • Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . 21pF • Wide Analog Input Bandwidth . . . . . . . . . . . . . 150MHz • Low Power Consumption . . . . . . . . . . . . . . . . . 790mW • Internal 1/2 Frequency Divider Circuit (With Reset Function) • CLK/2 Clock Output Pin • Compatible with ECL, PECL and TTL Digital Input Levels • 1:2 Demultiplexed Output • Direct Replacement for Sony CXA3026A Applications • RGB Graphics Processing (LCD, PDP) • Digital Oscilloscopes • Digital Communications (QPSK, QAM) • Magnetic Recording (PRML) Ordering Information PART NUMBER HI3026AJCQ HI3026AEVAL TEMPT. RANGE (oC) -20 to 75 25 PACKAGE 48 Ld MQFP PKG. NO. Q48.12x12-S Evaluation Board Pinout HI3026A (MQFP) TOP VIEW RESETN/E RESET/E RESET/T SELECT INV CLKOUT DVCC2 DGND2 P1D7 P1D6 P1D5 DVEE3 VRB AGND VRM1 AVCC VIN VRM2 AVCC VRM3 AGND VRT DGND3 1 2 3 4 5 6 7 8 9 10 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 P1D4 P1D3 P1D2 P1D1 P1D0 DGND2 DVCC2 DVCC1 DGND1 P2D7 P2D6 P2D5 P2D4 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 DVCC2 DGND2 CLK/T NC CLKN/E P2D0 P2D1 NC NC CLK/E P2D2 P2D3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 File Number 4246 4-1378 HI3026A Block Diagram AVCC 5 VRT 11 R1 R/2 R 1 R 39 P1D6 2 R 63 VRM3 9 R 64 R 35 P1D2 65 R 126 R 127 VRM2 VIN 7 6 R 129 R 191 VRM1 4 R LATCHB TTLOUT 192 R 193 R 254 R 255 VRB CLK/T CLK/E CLKN/E 2 R2 15 13 14 D RESETN/T RESETN/E RESET/E 46 48 47 3 10 45 29 20 32 41 DGND2 1 DVEE3 Q SELECT Q 43 CLKOUT DELAY 16 17 18 NC R/2 21 P2D0 (LSB) 26 P2D5 25 P2D4 24 P2D3 23 P2D2 22 P2D1 R 128 ENCODER (MSB) 40 P1D7 8 INV 44 DVCC1 30 DVCC2 19 31 42 DGND3 12 . . . 6 BITS 38 P1D5 LATCHA TTLOUT 37 P1D4 36 P1D3 8 BITS . . . 6 BITS 34 P1D1 6-BIT LATCH + ENCODER 33 P1D0 (LSB) 8 BITS . . . (MSB) 28 P2D7 27 P2D6 6 BITS . . . 6 BITS AGND SELECT DGND1 4-1379 HI3026A Absolute Maximum Ratings TA = 25oC Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (MQFP - Lead Tips Only) Supply Voltage AVCC , DVCC1 , DVCC2 . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V DGND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V DVEE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7.0V to 0.5V DGND3 - DVEE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . . VRT - 2.7V to AVCC Reference Input Voltage VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7V to AVCC VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN - 2.7V to AVCC |VRT - VRB| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V Digital Input Voltage ECL (***/E (Note 2)) . . . . . . . . . . . . . . . . . . . . . . . . DVEE3 to 0.5V PECL (***/E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to DGND3 TTL (***/T, INV) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to DVCC1 Other (SELECT) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to DVCC1 VID (|***/E - ***N/E| (Note 3)) . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V Recommended Operating Conditions WITH A SINGLE POWER SUPPLY MIN TYP MAX Supply Voltage DVCC1 , DVCC2 , AVCC . . . . . . . . . . . . . . . +4.75 +5.0 +5.25V DGND1, DGND2, AGND . . . . . . . . . . . . . -0.05 0 +0.05V DGND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75 +5.0 +5.25V DVEE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05 0 +0.05V Analog Input Voltage (VIN) . . . . . . . . . . . . . . VRB VRT Reference Input Voltage VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.9 +4.1V VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 +2.6V |VRT - VRB| . . . . . . . . . . . . . . . . . . . . . . . . 1.5 2.1V Digital Input Voltage PECL (***/E) VIH . . . . . . . . . . . . . . . DGND3 - 1.05 DGND3 - 1.4V PECL (***/E) VIL . . . . . . . . . . . . . . . DGND3 - 3.2 DGND3 - 1.4V TTL (***/T, INV) VIH. . . . . . . . . . . . . . . . . . 2.0V TTL (***/T, INV) VIL . . . . . . . . . . . . . . . . . . 0.8V Other (SELECT) VIH . . . . . . . . . . . . . . . . . DVCC1 Other (SELECT) VIL . . . . . . . . . . . . . . . . . DGND1 VID (Note 3) (|***/E- ***N/E|) . . . . . . . . . . . 0.4 0.8 Max Conversion Rate (fC , Straight Mode) . . . 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSPS Max Conversion Rate (fC , DMUX Mode) . . . . 140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSPS Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC WITH DUAL POWER SUPPLIES MIN TYP MAX Supply Voltage DVCC1 , DVCC2 , AVCC . . . . . . . . . . . . . . +4.75 +5.0 +5.25V DGND1, DGND2, AGND . . . . . . . . . . . . . -0.05 0 +0.05V DGND3 . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05 0 +0.05V DVEE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5 -5.0 -4.75V Analog Input Voltage (VIN) . . . . . . . . . . . . . VRB VRT Reference Input Voltage VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.9 +4.1V VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 +2.6V |VRT - VRB| . . . . . . . . . . . . . . . . . . . . . . . 1.5 2.1V Digital Input Voltage ECL (***/E) VIH DGND3 . . . . . . . . . DGND3 - 1.05 DGND3 - 0.5V ECL (***/E) VIL DGND3. . . . . . . . . . DGND3 - 3.2 DGND3 - 1.4V TTL (***/T, INV) VIH . . . . . . . . . . . . . . . . . 2.0V TTL (***/T, INV) VIL . . . . . . . . . . . . . . . . . 0.8V Other (SELECT) VIH . . . . . . . . . . . . . . . . DVCC1 Other (SELECT) VIL . . . . . . . . . . . . . . . . DGND1 VID (Note 3) (|***/E- ***N/E|) . . . . . . . . . . 0.4 0.8 Max Conversion Rate (fC , Straight Mode) . . . 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSPS Max Conversion Rate (fC , DMUX Mode) . . . . 140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSPS Ambient Temperature (TA). . . . . . . . . . . . . . . . . . . . . .-20oC to 75oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on an evaluation PC board in free air. 2. ***/E and ***T indicate CLK/E and CLK/T, etc. for the pin name. 3. VID : Input Voltage Differential. Electrical Specifications PARAMETER Resolution DC CHARACTERISTICS Integral Linearity Error Differential Linearity Error DVCC1 , 2 , AVCC , DGND3 = +5V, DGND1, 2, AGND, DVEE3 = 0V, VRT = 4V, VRB = 2V, TA = 25oC SYMBOL TEST CONDITIONS MIN TYP 8 MAX UNITS Bits EIL EDL VIN = 2VP-P, fC = 5 MSPS - - ±0.5 ±0.5 LSB LSB 4-1380 HI3026A Electrical Specifications PARAMETER ANALOG INPUT Analog Input Capacitance Analog Input Resistance Analog Input Current REFERENCE INPUT Reference Resistance (Note 4) Reference Current (Note 5) Offset Voltage, VRT Side Offset Voltage, VRB Side DIGITAL INPUT (ECL, PECL) Digital Input Voltage: High Digital Input Voltage: Low Threshold Voltage Digital Input Current: High Digital Input Current: Low Digital Input Capacitance DIGITAL INPUT (TTL) Digital Input Voltage: High Digital Input Voltage: Low Threshold Voltage Digital Input Current: High Digital Input Current: Low Digital Input Capacitance DIGITAL OUTPUT (TTL) Digital Output Voltage: High Digital Output Voltage: Low SWITCHING CHARACTERISTICS Maximum Conversion Rate Aperture Jitter Sampling Delay Clock High Pulse Width Clock Low Pulse Width Reset Pulse Width (Note 6) RESETN_CLK Setup CLKOUT Output Delay Data Output Delay (Note 6) fC tAJ tDS tPW1 tPW0 tPWR t_RST tDCLK tDO1 tDO2 Output Rise Time Output Fall Time DYNAMIC CHARACTERISTICS Input Bandwidth S/N Ratio VIN = 2VP-P , -3dB fC = 140 MSPS, fIN = 1kHz Full Scale, DMUX Mode fC = 140 MSPS, fIN = 34.999MHz Full Scale, DMUX Mode 150 46 40 MHz dB dB tr tf CLK CLK RESETN RESETN-CLK (CL = 5pF) DMUX Mode (CL = 5pF) (CL = 5pF) 0.8V to 2.0V (CL = 5pF) 0.8V to 2.0V (CL = 5pF) DMUX Mode 140 3 2.8 2.8 tx2 3.5 3.5 t 4.5 10 4.5 7 t+1 8 2 2 6 9 t+2 10 MSPS ps ns ns ns ns ns ns ns ns ns ns VOH VOL IOH = -2mA IOL = 1mA 2.4 0.5 V V VIH VIL VTH IIH IIL VIH = 3.5V VIL = 0.2V 2.0 -50 -500 1.5 0.8 0 0 5 V V V µA µA pF VIH VIL VTH IIH IIL VIH = DGND3 - 0.8V VIL = DGND3 - 1.6V DGND3 - 1.05 DGND3 - 3.2 -50 -75 DGND3 - 1.2 DGND3 - 0.5 DGND3 - 1.4 +50 0 5 V V V µA µA pF RREF IREF EOT EOB 75 9.7 2 2 115 17.4 155 28 15 10 Ω mA mV mV CIN RIN IIN VIN = +3.0V + 0.07VRMS 4 0 21 50 500 pF kΩ µA DVCC1 , 2 , AVCC , DGND3 = +5V, DGND1, 2, AGND, DVEE3 = 0V, VRT = 4V, VRB = 2V, TA = 25oC (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 4-1381 HI3026A Electrical Specifications PARAMETER Error Rate DVCC1 , 2 , AVCC , DGND3 = +5V, DGND1, 2, AGND, DVEE3 = 0V, VRT = 4V, VRB = 2V, TA = 25oC (Continued) SYMBOL TEST CONDITIONS fC = 140 MSPS, fIN = 1kHz Full Scale, DMUX Mode, Error > 16 LSB fC = 140 MSPS, fIN = 34.999MHz Full Scale, DMUX Mode, Error > 16 LSB fC = 100 MSPS, fIN = 24.999MHz Full Scale, Straight Mode, Error > 16 LSB POWER SUPPLY Supply Current Supply Current Power Consumption (Note 8) ICC IEE PD 130 0.4 690 150 0.6 790 190 0.8 990 mA mA mW MIN TYP MAX 10-12 UNITS TPS - - 10-9 TPS - - 10-9 TPS (Note 7) NOTES: 4. RREF: Resistance value between VRT and VRB . V RT – V RB 5. I REF = ---------------------------- . R REF 1 6. t = ---- . fC 7. TPS = Times Per Sample. ( V RT – V RB ) 2 8. P D = ( I CC + I EE ) • V CC + ------------------------------------ . V REF Timing Waveforms N-1 VIN N+2 tDS 4.5ns N t N+1 N+3 CLK tPW1 tPW0 tDO2 8ns P1D0 TO D7 N-2 2.0V N 0.8V N+2 P2D0 TO D7 tDCLK 7ns 2.0V CLK OUT 0.8V N-3 tDO1 T + 1ns 2.0V 0.8V 2.0V 0.8V N-1 N+1 RESET PULSE tPWR FIGURE 1. DEMUX MODE TIMING CHART (SELECT = VCC) 4-1382 HI3026A Timing Waveforms (Continued) N-1 VIN N+1 tDS N t CLK tPW1 tPW0 2.0V 0.8V 2.0V 0.8V N+2 N+3 P1D0 TO D7 N-4 N-3 N-2 N-1 N P2D0 TO D7 N-5 N-4 N-3 N-2 N-1 tDO2 CLK OUT (CLK IS INVERTED AND OUTPUT) 2.0V 0.8V tDCLK RESET PULSE FIGURE 2. STRAIGHT MODE TIMING CHART (SELECT = GND) DGND3 VIH (MAX) VIL VTH (DGND3 -1.2V) VID VIH VIL (MIN) FIGURE 3. ECL AND PECL SWITCHING LEVEL Pin Descriptions TYPICAL VOLTAGE LEVEL GND +5V (Typ) GND +5V (Typ) PIN NO 3, 10 5, 8 20, 29 32, 41 19, 30 31, 42 SYMBOL AGND AVCC DGND1 DGND2 DVCC1 DVCC2 I/O EQUIVALENT CIRCUIT DESCRIPTION Analog Ground. Separated from the digital ground. Analog Power Supply. Separated from the digital power supply. Digital Ground. Digital Power Supply. 4-1383 HI3026A Pin Descriptions (Continued) TYPICAL VOLTAGE LEVEL +5V (Typ) (With a Single Power Supply) GND (With Dual Power Supplies) 1 DVEE3 GND (With a Single Power Supply) -5V (Typ) (With Dual Power Supplies) 16, 17, 18 13 14 NC CLK/E CLKN/E I I R 13 14 48 47 R PIN NO 12 SYMBOL DGND3 I/O EQUIVALENT CIRCUIT DESCRIPTION Digital Power Supply. Ground for ECL input. +5V for PECL and TTL input. Digital Power Supply. -5V for ECL input. Ground for PECL and TTL Input No Connect pin. Not connected with the internal circuits. ECL/PECL DGND3 Clock Input. CLK/E Complementary Input. When left open, this pin goes to the threshold potential. Only CLK/E can be used for operation, but complementary input is recommended to attain fast and stable operation. Reset Input. When the input is set to low level, the built-in CLK frequency divider circuit can be reset. 1.2V R R 48 RESETN/E I 47 RESET/E I DVEE3 RESETN/E Complementary Input. When left open, this pin goes to the threshold voltage. Only RESETN/E can be used for operation. Clock Input. 15 46 CLK/T RESETN/T I I TTL DVCC1 R/2 Reset Input. When left open, this input goes to high level. When the input is set to low level, the built-in CLK frequency divider circuit can be reset. 15 46 DGND1 DVEE3 R 1.5V 44 INV I TTL DVCC1 Data Output Polarity Inversion Input. When left open, this input goes to high level. (See Table 1, I/O Correspondence Table.) 44 DGND1 DVEE3 4-1384 HI3026A Pin Descriptions (Continued) TYPICAL VOLTAGE LEVEL VCC or GND DVCC1 PIN NO 45 SYMBOL SELECT I/O EQUIVALENT CIRCUIT DESCRIPTION Data Output Mode Selection. (See Table 2, Operating Mode Table.) 45 DGND1 DVEE3 11 VRT I 4.0V (Typ) 11 R1 R/2 Top Reference Voltage. By-pass to AGND with a 1µF tantal capacitor and a 0.1µF chip capacitor. Reference Voltage Mid Point. Bypass to AGND with a 0.1µF chip capacitor. 9 VRM3 VRB + 3 -- (VRT - VRB) 4 VRB + 2 -- (VRT - VRB) 4 VRB + 1 (V - V ) -RT RB 4 R COMPARATOR 1 R 7 VRM2 COMPARATOR 63 9 R COMPARATOR 64 COMPARATOR 127 7 R COMPARATOR 128 COMPARATOR 191 4 R COMPARATOR 192 R COMPARATOR 255 R2 2 R2 Reference Voltage Mid Point. Bypass to AGND with a 0.1µF chip capacitor. 4 VRM1 Reference Voltage Mid Point. Bypass to AGND with a 0.1µF chip capacitor. 2 VRB I 2.0V (Typ) Bottom Reference Voltage. Bypass to AGND with a 1µF tantal capacitor and a 0.1µF chip capacitor. 6 VIN I VRT to VRB AVCC COMPARATOR AVCC Analog Input. 6 VREF AGND DVEE3 33 to 40 21 to 28 43 P1D0 to P1D7 P2D0 to P2D7 CLKOUT O O O TTL DVCC1 DVCC2 21 TO 28 33 TO 40 100K 43 DGND2 DVEE3 Port 1 Side Data Output. Port 2 Side Data Output. Clock Output. (See Table 2, Operating Mode Table.) DGND1 4-1385 HI3026A TABLE 1. A/D CODE TABLE INV 1 VIN VRT STEP 255 254 • • • VRM2 128 127 • • • 1 VRB 0 D7 D0 D7 0 D0 1111111100000000 1111111000000001 • • • • • • 1000000001111111 0111111110000000 • • • • • • 0000000111111110 0000000011111111 Notes On Operation • The HI3026A is a high-speed A/D converter which is capable of TTL, ECL and PECL level clock input. Characteristic impedance should be properly matched to ensure optimum performance during high-speed operation. • The power supply and grounding have a profound influence on converter performance. The power supply and grounding method are particularly important during high-speed operation. General points for caution are as follows: - The ground pattern should be as large as possible. It is recommended to make the power supply and ground patterns wider at an inner layer using a multi-layer board. - To prevent interference between AGND and DGND and between AVCC and DVCC , make sure the respective patterns are separated. To prevent a DC offset in the power supply pattern, connect the AVCC and DVCC lines at one point each via a ferrite-bead filter. Shorting the AGND and DGND patterns in one place immediately under the A/D converter improves A/D converter performance. - Ground the power supply pins (AVCC , DVCC1 , DVCC2 , DVEE3) as close to each pin as possible with a 0.1µF or larger ceramic chip capacitor. (Connect the AVCC pin to the AGND pattern and the DVCC1 , DVCC2 , DVEE3 pins to the DGND pattern.) - The digital output wiring should be as short as possible. If the digital output wiring is long, the wiring capacitance will increase, deteriorating the output slew rate and resulting in reflection to the output waveform since the original output slew rate is quite fast. • The analog input pin VIN has an input capacitance of approximately 21pF. To drive the A/D converter with proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance or parasitic inductance by using a large capacity drive circuit, keeping wiring as short as possible, and using chip parts for resistors and capacitors, etc. • The VRT and VRB pins must have adequate bypass to protect them from high-frequency noise. Bypass them to AGND with approximately 1µF tantal capacitor and, 0.1µF capacitor as short as possible. • When the digital input level is ECL or PECL level, ***/E pins should be used and ***/T pins left open. When the digital input level is TTL, ***/T pins should be used and III/E pins left open. Test Circuits +V 5V A ICC 4V VRT AVCC DVCC1 DVCC2 5V A IEE S2 + - S1 S1: ON WHEN A < B S2: ON WHEN A > B DGND3 -V CLK/E 5MHz PECL VIN 8 AB COMPARATOR HI3026A A8 TO A1 A0 B8 TO B1 B0 8 BUFFER 1.95V VIN 2V VRB DGND2 DGND1 AGND DVEE3 “0” DVM “1” 000...00 TO 111..10 CONTROLLER FIGURE 4. CURRENT CONSUMPTION MEASUREMENT CIRCUIT FIGURE 5. INTEGRAL LINEARITY ERROR/DIFFERENTIAL LINEARITY ERROR MEASUREMENT CIRCUIT 4-1386 HI3026A Test Circuits SIGNAL SOURCE fC 4 (Continued) VIN HI3026A 8 LATCH A COMPARATOR A>B PULSE COUNTER -1kHz CLK CLK B + LATCH 2VP-P SINE WAVE 16 LSB 8 SIGNAL SOURCE fC 1/ FIGURE 6. ERROR RATE MEASUREMENT CIRCUIT VRT 100MHz VIN VRM2 VRB AMP OSC1 φ: VARIABLE CLK ∆V VIN HI3026A CLK 1024 SAMPLES OSC2 ECL BUFFER 100MHz ∆t 8 LOGIC ALALYZER VIN 129 128 127 126 125 CLK SAMPLING TIMING FLUCTUATION (= APERTURE JITTER) σ (LSB) fR NOTE: Where σ (LSB) is the deviation of the output codes when the largest slew rate point is sampled at the clock which has exactly the same frequency as the analog input signal, the aperture jitter, tAJ is: 256 σ / ∆V t AJ =  -------------  = σ /  --------- x 2 π f . 2   ∆t  FIGURE 8. APERTURE JITTER MEASUREMENT METHOD FIGURE 7. SAMPLING DELAY/APERTURE JITTER MEASUREMENT CIRCUIT Operating Modes The HI3026A has two types of operating modes which are selected with Pin 45 (SELECT). TABLE 2. OPERATING MODE TABLE OPERATING MODE DMUX Mode Straight Mode SELECT VCC GND MAXIMUM CONVERSION RATE 140 MSPS 100 MSPS DATA OUTPUT Demultiplexed Output 70 Mbps Straight Output 100 Mbps CLOCK OUTPUT The input clock is 1/2 frequency divided and output at 70MHz. The input clock is inverted and output at 100MHz. DMUX Mode (See Application Circuits, Figures 18, 19, 20) Set the SELECT pin to VCC for this mode. In this mode, the clock frequency is divided by 2 in the IC, and the data is output after being demultiplexed by this 1/2 frequency divided clock. The 1/2 frequency divided clock, which has adequate setup time and hold time for the output data, is output from the CLKOUT pin. When using multiple HI3026A units in parallel in this mode, differences in the start timing of the 1/2 frequency divided clock may cause operation as shown in the figure below. As a countermeasure, the HI3026A is equipped with a function which resets the 1/2 frequency divided clock. When resetting this clock, the RESET pulse must be input to the RESET pin. See the Timing Charts for the RESET pulse input timing. The A/D converter can operate at fC (Min) = 140 MSPS in this mode. Straight Mode (See Application Circuits, Figures 21, 22, 23) Set the SELECT pin to GND for this mode. In this mode, data output can be obtained in accordance with the clock frequency applied to the A/D converter for applications which use the clock applied to the A/D converter as the system clock. 4-1387 HI3026A The A/D converter can operate at fC (Min) = 100 MSPS in this mode. Digital Input Level and Supply Voltage Settings The logic input level for the HI3026A supports ECL, PECL and TTL levels. The power supplies (DVEE3 , DGND3) for the logic input block must be set to match the logic input (CLK and RESET signals) level. TABLE 3. LOGIC INPUT LEVEL AND POWER SUPPLY SETTINGS DIGITAL INPUT LEVEL ECL PECL TTL APPLICATION CIRCUITS (FIGURE) (18) (19) (20) (21) (22) (23) DVEE3 -5V 0V 0V DGND3 0V +5V +5V SUPPLY VOLTAGE ±5V +5V +5V CLK HI3026A CLK CLK A 8 BITS DATA CLKOUT RESETN HI3026A CLK B 8 BITS CLKOUT DATA RESETN FIGURE 9. WHEN THE RESET PULSE IS NOT USED CLK RESET PULSE HI3026A CLK CLK A 8 BITS DATA CLKOUT RESETN HI3026A CLK RESET PULSE B 8 BITS CLKOUT DATA RESETN FIGURE 10. WHEN THE RESET PULSE IS USED Typical Performance Curves 170 CURRENT CONSUMPTION (mA) CURRENT CONSUMPTION (mA) 170 160 160 150 150 140 140 fIN = fCLK -1kHz 4 DMUX MODE CL = 5pF 130 -25 130 25 AMBIENT TEMPERATURE (oC) 75 0 70 CONVERSION RATE (MSPS) 140 FIGURE 11. CURRENT CONSUMPTION vs AMBIENT TEMPERATURE CHARACTERISTICS FIGURE 12. CURRENT CONSUMPTION vs CONVERSION RATE CHARACTERISTICS RESPONSE 4-1388 HI3026A Typical Performance Curves 200 VRT = 4V ANALOG INPUT CURRENT (µA) REFERENCE CURRENT (mA) 3 ANALOG INPUT VOLTAGE (V) 4 VRB = 2V (Continued) 20 100 15 0 2 10 -25 25 AMBIENT TEMPERATURE (oC) 75 FIGURE 13. ANALOG INPUT CURRENT vs ANALOG INPUT VOLTAGE CHARACTERISTICS FIGURE 14. REFERENCE CURRENT vs AMBIENT TEMPERATURE CHARACTERISTICS 50 fC = 140 MSPS 10-6 fIN = 10-7 ERROR RATE (TPS) -1kHz 4 ERROR > 16 LSB fCLK 40 SNR (dB) 10-8 30 10-9 20 1 3 5 10 30 50 INPUT FREQUENCY (MHz) 10-10 140 160 CONVERSION RATE (MSPS) 180 FIGURE 15. SNR vs INPUT FREQUENCY RESPONSE FIGURE 16. ERROR RATE vs CONVERSION RATE CHARACTERISTICS 180 MAXIMUM CONVERSION (MSPS) fIN = 170 fCLK 4 -1kHz ERROR > 16 LSB ERROR RATE: 10-9 TPS 160 150 140 -25 25 AMBIENT TEMPERATURE (Co) 75 FIGURE 17. MAXIMUM CONVERSION RATE vs AMBIENT TEMPERATURE CHARACTERISTICS 4-1389 HI3026A Typical Application Circuits +5V (D) DG ECL RESET PULSE 48 47 46 45 44 43 42 41 40 39 38 37 -5V (D) AG AG 2V 1 2 3 4 +5V (A) AG 5 6 7 +5V (A) AG AG DG 4V 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ECL - CLK DG +5V (D) 36 P1D0 TO P1D7 35 8-BIT DIGITAL DATA 34 33 32 31 30 29 28 27 26 P2D0 TO P2D7 8-BIT DIGITAL DATA 25 LATCH 8-BIT DIGITAL DATA DG DG +5V (D) LATCH 8-BIT DIGITAL DATA FIGURE 18. DMUX ECL INPUT +5V (D) DG PECL RESET PULSE 48 47 46 45 44 43 42 41 40 39 38 37 1 2 2V 3 4 +5V (A) AG 5 6 7 +5V (A) AG AG +5V (D) 4V 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PECL - CLK DG +5V (D) 36 P1D0 TO P1D7 35 8-BIT DIGITAL DATA 34 33 32 31 30 29 28 27 26 P2D0 TO P2D7 8-BIT DIGITAL DATA 25 LATCH 8-BIT DIGITAL DATA +5V (D) DG DG LATCH DG AG AG 8-BIT DIGITAL DATA FIGURE 19. DMUX PECL INPUT 4-1390 HI3026A Typical Application Circuits (Continued) +5V (D) DG TTL RESET PULSE 48 47 46 45 44 43 42 41 40 39 38 37 1 2 2V 3 4 +5V (A) AG +5V (A) AG AG +5V (D) 4V 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 P1D0 TO P1D7 35 8-BIT DIGITAL DATA 34 33 32 31 30 29 28 27 26 P2D0 TO P2D7 8-BIT DIGITAL DATA 25 LATCH 8-BIT DIGITAL DATA DG +5V (D) DG LATCH DG AG AG 8-BIT DIGITAL DATA TTL - CLK DG +5V (D) FIGURE 20. DMUX TTL INPUT DG +5V (D) DG 48 47 46 45 44 43 42 41 40 39 38 37 -5V (D) AG AG 2V 1 2 3 4 +5V (A) AG 5 6 7 +5V (A) AG AG DG 4V 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ECL - CLK ECL - TTL DG +5V (D) 36 P1D0 TO P1D7 35 8-BIT DIGITAL DATA 34 33 32 31 30 29 28 27 26 25 DG DG +5V (D) LATCH 8-BIT DIGITAL DATA FIGURE 21. STRAIGHT ECL INPUT 4-1391 HI3026A Typical Application Circuits DG (Continued) +5V (D) DG 48 47 46 45 44 43 42 41 40 39 38 37 DG AG AG +5V (A) AG +5V (A) AG AG 4V +5V(D) 2V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PECL - CLK PECL - TTL DG +5V (D) 36 P1D0 TO P1D7 35 8-BIT DIGITAL DATA 34 33 32 31 30 29 28 27 26 25 DG +5V (D) DG LATCH 8-BIT DIGITAL DATA FIGURE 22. STRAIGHT PECL INPUT DG +5V (D) DG 48 47 46 45 44 43 42 41 40 39 38 37 DG AG AG +5V (A) AG +5V (A) AG AG +5V(D) 4V 2V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TTL - CLK 36 P1D0 TO P1D7 35 8-BIT DIGITAL DATA 34 33 32 31 30 29 28 27 26 25 DG +5V (D) DG LATCH 8-BIT DIGITAL DATA DG +5V (D) FIGURE 23. STRAIGHT TTL INPUT 4-1392 HI3026A Typical Application Circuits (Continued) AG ANALOG INPUT 4V +5V (D) + AG + AG +5V (A) + AG 10µF + 2V - 1µF DG 1µF - + + SHORT SHORT + 10µF AG 12 DGND3 11 VRT 10 AGND 9 VRM3 8 AVCC 7 VRM2 6 VIN 5 AVCC 4 VRM1 3 AGND 2 VRB 1 DVEE3 RESETN/E 48 RESET/E 47 RESETN/T 46 SELECT 45 INV 44 CLKOUT 43 DVCC2 42 DGND2 41 P1D7 40 P1D6 39 P1D5 38 P1D4 37 36 P1D3 P1D3 13 14 TTL CLK 15 16 17 18 19 20 21 22 23 24 CLK/E CLKN/E CLK/T NC NC NC DVCC2 DGND2 P2D0 P2D1 P2D2 DGND1 DGND2 DVCC1 DVCC2 P2D3 P2D4 P2D5 P2D6 P2D7 P1D0 P1D1 34 P1D1 25 26 27 28 29 30 31 32 33 35 P1D2 P1D2 P1D4 P1D5 SHORT THE ANALOG SYSTEM AND DIGITAL SYSTEM AT ONE POINT IMMEDIATELY UNDER THE A/D CONVERTER. SEE THE NOTES ON OPERATION. IS THE CHIP CAPACITOR OF 0.1µF. FIGURE 24. STRAIGHT MODE TTL I/O (WHEN A SINGLE POWER SUPPLY IS USED) (MSB) P2D7 4-1393 P1D6 (MSB) P1D7 (LSB) P2D0 P2D1 P2D2 P2D3 P2D4 P2D5 P2D6 (LSB) P1D0 HI3026A All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 4-1394