HI3197

HI3197 Data Sheet October 1998 File Number 4356.1 10-Bit, 125 MSPS D/A Converter The HI3197 is a high-speed D/A converter which can perform the multiplexed input of the two system 10-bit data. The maximum conversion rate achieves 125 MSPS. The multiplexed operation is possible by the 1/2 frequencydivided clock or by halving the frequency of the clock with the clock frequency divider circuit having the reset pin in the IC. The data input is TTL; the clock input pin and reset input pin can select either TTL or PECL according to the application. Features • Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bits • Conversion Rate 125 MSPS (PECL) 100 MSPS (TTL) • Data Input Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TTL • Low Power Consumption . . . . . . . . . . . . . . . 400mW (Typ) • Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . 1.5pV•s • Clock, Reset Input Level: TTL and PECL Compatible 2:1 Multiplexed Input Function • 1/2 Frequency-Divided Clock Output Possible by the BuiltIn Clock Frequency Divider Circuit • Voltage Output (50Ω Load Drive Possible) • Single Power Supply or ±Dual Power Supplies • Polarity Switching Function of Reset Signal Ordering Information PART NUMBER HI3197JCQ TEMP. RANGE (oC) -20 to 75 PACKAGE 48 Ld MQFP/ PQFP PKG. NO. Q48.7x7-S Applications • LCD • DDS • HDTV • Communications (QPSK, QAM) Pinout HI3197 (MQFP) TOP VIEW AOUTN AGND2 AOUTP AVCC2 DGND2 AVCC0 DVCC2 VREF VSET AGND2 VOCLP R POLARITY INV PS DVCC1 NC DGND1 (MSB) DA9 DA8 DA7 DA6 37 38 39 40 41 42 43 44 45 46 47 48 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 1 2 3 4 5 6 7 8 13 9 10 11 12 C2 C1 C3 RESETN/E RESETP/E RESET/T CLKN/E CLKP/E CLK/T DIV2OUT DIV2IN DB0 (LSB) DB1 DB2 DB3 (MSB) DB9 DB8 DA3 DA2 (LSB) DA0 DB7 DB6 DA4 DA1 DB5 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 DB4 DA5 HI3197 Block Diagram VREF 34 BGR VSET 35 + - CURRENT CONT. 36 AVCC2 AGND2 DVCC1 42 DVCC2 29 D/A 30 10-BIT DA0 TO DA9 1 TO 6 45 TO 48 INPUT LATCH 10-BIT MUX 10-BIT DB0 TO DB9 7 TO 16 INPUT LATCH 10-BIT LATCH 31 AOUTN 10-BIT 10-BIT RO = 50Ω 32 AOUTP AVCC0 AGND2 37 33 AGND2 AGND2 DIV2OUT D DIV2IN 17 Q Q 18 CLK/T 19 CLKP/E 20 CLKN/E 21 RESET/T 22 RESETP/E 23 RESETN/E 24 R POLARITY 39 44 DGND1 25 DGND2 26 C1 27 C2 28 C3 41 PS 40 INV 38 VOCLP 2 HI3197 Pin Descriptions and I/O Pin Equivalent Circuits PIN NO 1 to 6 45 to 48 7 to 16 SYMBOL DA0 to DA9 DB0 to DA9 I/O I I TYPICAL VOLTAGE LEVEL TTL DVCC1 EQUIVALENT CIRCUIT DESCRIPTION Side A Data Input. Side B Data Input. TTL 1 TO 6 VREF 7 TO 16 45 TO 48 DGND1 17 DIV2IN I TTL DVCC1 1/ Frequency-Divided Clock Input. 2 Use this pin for MUX.1A or MUX.2 mode. Leave open for other modes. 17 VREF DGND1 18 DIV2OUT O TTL DVCC1 1/ Frequency-Divided Clock Out2 put. The signal with the 1/2 fre- quency divided clock (DIV2OUT) is output for MUX.1A mode. Leave open for other modes. 18 DGND1 19 CLK/T I TTL DVCC1 Clock Input. Use this pin when the clock is input in the TTL level. At this time, leave Pins 20 and 21 open. VREF 19 DGND1 20 CLKP/E I PECL DVCC1 Clock Input. Use this pin when the clock is input in PECL level. At this time, leave Pin 19 open. CLKP/E Complementary Input. When left open, this pin goes to the threshold potential. Operation is possible only with CLKP/E, but complementary input is recommended to attain fast and stable operation. 21 CLKN/E I PECL 20 21 DGND1 3 HI3197 Pin Descriptions and I/O Pin Equivalent Circuits PIN NO 22 SYMBOL RESET/T I/O I TYPICAL VOLTAGE LEVEL TTL DVCC1 (Continued) EQUIVALENT CIRCUIT DESCRIPTION Reset signal input. When the multiple HI3197 are operated at a time for MUX.1A or MUX.1B mode, the start timing of the internal 1/2 frequency divider circuits should be matched. At this time, the reset signal is used; when the reset signal is the TTL level, Pin 22 is used and Pins 23 and 24 are left open. When the reset signal is the PECL level, Pins 23 and 24 are used and Pin 22 is left open. For the PECL level, operation is possible only with RESETP/E as with the case for the clock. The reset signal polarity can be set by Pin 39 (RPOLARITY). Leave the reset pin open when the other modes are used. 22 VREF DGND1 23 24 RESETP/E RESETN/E I I PECL PECL DVCC1 23 24 DGND1 25 DGND2 Single Power Supply: GND Dual Power Supplies: -5V I I I TTL TTL TTL 26 27 28 DGND1 VREF DVCC1 Digital Power Supply. 26 27 28 C1 C2 C3 Function setting. 29 DVCC2 Single Power Supply: +5V Dual Power Supplies: GND AVCC0 RO RO 31 32 Digital Power Supply. 30 31 AVCC0 OUTN O AVCC0 - VFS Analog Output Power Supply. D/A Negative Output. The inversion of the D/A positive output pin is output. Terminate the inversion without pin with 50Ω when the inversion output is not used and the positive output is terminated with 50Ω. D/A positive output. 32 AOUTP O AVCC0 - VFS AGND2 33 AGND2 Single Power Supply: GND Dual Power Supplies: -5V Analog Ground. 4 HI3197 Pin Descriptions and I/O Pin Equivalent Circuits PIN NO 34 SYMBOL VREF I/O O TYPICAL VOLTAGE LEVEL AGND +1.2V (Continued) EQUIVALENT CIRCUIT AVCC2 DESCRIPTION Analog Reference Voltage Output. 34 AGND2 35 VSET I AGND2 + 0.7V to AGND2 + 1.03V AVCC2 Full scale adjustment. 35 36 AVCC2 Single Power Supply: +5V Dual Power Supplies: GND Single Power Supply: GND Dual Power Supplies: -5V I Clamp Voltage DVCC1 Analog Power Supply. 37 AGND2 Analog Power Supply 38 VOCLP 38 TTL Output High Level Clamp. The TTL level signal is output from the DIV2OUT pin for MUX.1A mode. The TTL high level voltage is clamped to the value approximately equivalent to the voltage supplied to this pin. Leave the VOCLP pin open for other modes. DGND1 39 P Polarity I TTL DVCC1 Reset signal polarity switching. At high level, the reset polarity is active high; at low level, active low. 39 VREF DGND1 5 HI3197 Pin Descriptions and I/O Pin Equivalent Circuits PIN NO 40 SYMBOL INV I/O I TYPICAL VOLTAGE LEVEL TTL DVCC1 (Continued) EQUIVALENT CIRCUIT DESCRIPTION Analog Output polarity inversion. The analog output is inverted at low level. 40 VREF DGND1 41 PS I TTL DVCC1 Power saving. Power saving at low level. Normally pull up the PS pin to high level as this pin is open low. 41 DGND1 42 43 44 DVCC1 NC DGND1 5V Digital Power Supply. No connection. 0V Digital Ground. 6 HI3197 Absolute Maximum Ratings TA = 25oC Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . .1.4W (When mounted on a glass fabric base epoxy board with 76mm x 114mm, 1.6mm thick) Maximum Junction Temperature (Hermetic Package or Die) . . .175oC Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range, TSTG . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC Supply Voltage (AVCC0 , AVCC2 , DVCC2) . . . . . . . . . . -0.5 to +7.0V AGND2, DGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . -7.0 to +0.5V DVCC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7.0V AVCC2 - AGND2. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7.0V AVCC0 - AGND2. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7.0V DVCC2 - DGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7.0V Input Voltage VSET, . . . . . . . . . . . . . . . . . . . . . . . . AGND2 -05 to AVCC2 + 0.5V TTL Pin . . . . . . . . . . . . . . . . . . . . . DGND1 -0.5 to DVCC1 + 0.5V PECL Pin, . . . . . . . . . . . . . . . . . . . DGND1 -0.5 to DVCC1 + 0.5V PS. . . . . . . . . . . . . . . . . . . . . . . . . . DGND1 -0.5 to DVCC1 + 0.5V (Others), VOCLP . . . . . . . . . . . . . . . . . DGND1 -0.5 to DVCC1 + 5V Recommended Operating Conditions WITH A SINGLE POWER SUPPLY Supply Voltage AVCC0 , AVCC2 . . . . . . . . . . . . . . . . . . . . . AGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . DVCC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND1. . . . . . . . . . . . . . . . . . . . . . . . . . . DVCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND2. . . . . . . . . . . . . . . . . . . . . . . . . . . MIN +4.75 -0.05 +4.75 -0.05 -4.75 -0.05 TYP +5.0 0 +5.0 0 +5.0 0 MAX +5.25V +0.05V +5.25V +0.05V +5.25V +0.05V WITH DUAL POWER SUPPLIES Supply Voltage AVCC0 , AVCC2 . . . . . . . . . . . . . . . . . . . . . AGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . DVCC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND1. . . . . . . . . . . . . . . . . . . . . . . . . . . DVCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND2. . . . . . . . . . . . . . . . . . . . . . . . . . . MIN -0.05 -5.50 4.75 -0.05 -0.05 -5.50 TYP 0 -5.0 5.0 0 0 -5.0 MAX +0.05V -4.75V +5.25V +0.05V +0.05V -4.75V Recommended Operating Conditions (Applying to Single and Dual Power Supplies) Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC Clock Pulse Width tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4ns (Min) tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4ns (Min) Load Resistance, RL . . . . . . . . . . . . . . . . . . Analog Output Full Scale Voltage RL ≥ 10kΩ, VFS . . . . . . . . . . . . . . . . . . . . . RL = 50Ω, VFS . . . . . . . . . . . . . . . . . . . . . . MIN 50 1.5 0.75 TYP 50 2.0 1.0 MAX ≥10kΩ 2.2V 1.2V MIN TYP MAX AGND2 + 1.03V Analog Input Voltage, VSET . . .AGND2 + 0.7 Digital Input Voltage PECL, VIH . . . . . . . . . . . . . . .DGND1 + 2.6 DVCC1 PECL, VIL . . . . . . . . . . . . . . . VIH - 0.8 VIH - 0.4V TTL, VIH . . . . . . . . . . . . . . . . .DGND1 + 2.0 TTL, VIL . . . . . . . . . . . . . . . . . DGND1 + 0.8V PS, VIH. . . . . . . . . . . . . . . . . .DGND1 + 2.0 PS, VIL . . . . . . . . . . . . . . . . . . DGND1 + 0.8V Other, VOCLP . . . . . . . . . . . .DGND1 + 2.7 DVCC1 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER Resolution Maximum Conversion Rate VSUPPLY = ±5V, AV = +1, RL = 100Ω SYMBOL n fCECL fCTTL INL DNL DNL DNL AOUTP Transitions from 0000111111 - 0001000000 AOUTN Transitions from 1111000000 - 1110111111 RL = 50Ω RL ≥ 10kΩ Measured to DVCC2 PECL Operation TTL Operation VFS = 1V TEST CONDITIONS MIN TYP 10 MAX 125 100 ±1.2 -0.85 to 0.5 -1.2 to 0.5 -1.2 to 0.5 UNITS Bit MSPS MSPS LSB LSB LSB LSB Integral Linearity Error Differential Linearity Error ANALOG OUTPUT Output Full-Scale Voltage VFS VOC 0.75 1.5 -2.1 1 2.0 1.05 2.2 1.5 V V V Compliance Voltage VOC(MIN): (AVCC0-VFS - DVCC2) ≥ -2.V, VOC(MAX): (AVCC0-VOF - DVCC2) ≥ 1.5 7 HI3197 Electrical Specifications PARAMETER Output Zero Offset Voltage VSUPPLY = ±5V, AV = +1, RL = 100Ω (Continued) SYMBOL VOF TEST CONDITIONS RL ≥ 10kΩ , VSET = AGND2 + 0.9375V RL = 50Ω, VSET = AGND2 + 0.9375V Output Resistance Output Capacitance Absolute Amplitude Error Absolute Amplitude Error Temperature Characteristics Analog Output Rise Time Analog Output Fall Time Settling Time Glitch Energy REFERENCE VREF Pin Voltage VREF Temperature Drift VREF Multiplying Bandwidth Digital Input (TTL Pin) VIH VIL VTH IIH IIL Digital Output (DIV2OUT TTL Pin) VOH VOL IOZ IOZ tr tf Digital Input (PECL Pin) VIH VIL IIH IIL Digital Input Current (PS) VIH VIL IIH IIL Clamp Pin Input Current (VOCLP) Digital Input Capacitance CURRENT CONSUMPTION Supply Current (Operating) ICC DICC1 DICC2 AICC2 AICC0 Total Operating 63 7 13 6 37 96 15.5 19 8.5 53 129 24 25 11 68 mA mA mA mA mA ICCLP ICCLP CIN VIH = 3.5V VIL = 0.2V VCCLP = DVCC1 VCCLP = 2.4V VIH = DVCC1 - 0.8V VIL = DVCC1 - 1.5V VIH = 3.5V VIL = 0.2V IOH = -2mA IOL = 1mA VO = 5V VO = 0V 0.8 to 2.4V (CL = 10pF) 2.4 to 0.8V (CL = 10pF) 100mVP-P Sinewave at -3dB VREF IREF = 1mA AGND2+1.18 AGND2+1.25 AGND2+1.32 50 2 -1 -2 2.4 10 -1 1.0 0.6 DVCC1 - 1.5 DVCC1 - 3.2 0 -30 2 -1 -1 -60 1.5 3 250 0.8 1 0 0.5 100 1 1.5 1.2 DVCC1 - 0.5 DVCC1 - 1.4 20 0 0.8 100 0 5 -10 5 V ppm/ oC MHz V V V µA µA V V µA µA ns ns V V µA µA V V µA µA µA µA pF RO CO EG TCG tr tf tSET GE VSET = AGND2 + 0.9375V VFS = 1V at 25oC RL = 50Ω , VFS = 1V, 10 - 90% MIN 0 0 -4 0.85 0.75 TYP 50 10 1.5 MAX 20 10 4 60 1.05 0.85 3.5 5.0 UNITS mV mV Ω pF % of FS ppm/ oC ns ns ns pVS 8 HI3197 Electrical Specifications PARAMETER Supply Current (PS Mode) NOTE: The current consumption in power saving mode does not include the voltage reference (VREF) current. When using the internal reference the additional current IREF = VREF / RREF should be added to the table values for an accurate estimate of total standby current. VSUPPLY = ±5V, AV = +1, RL = 100Ω (Continued) SYMBOL ICC DICC1 DICC2 AICC2 AICC0 TEST CONDITIONS Power Saving Mode Power Saving Mode Power Saving Mode Power Saving Mode Power Saving Mode MIN TYP 0.432 0.38 0.001 0.05 0.001 MAX 4 1.5 0.2 0.3 2 UNITS mA mA mA mA mA AC Specifications MUX.1A and MUX.1B Modes CLK SIGNAL LEVEL RESET SIGNAL LEVEL PECL PECL MIN TYP MAX MIN TTL TTL TYP MAX MIN PECL TTL TYP MAX UNITS PARAMETER MUX.1A MODE Maximum Conversion Rate Clock High Pulse Width Clock Low Pulse Width Reset Signal Setup Time Reset Signal Hold Time DIV2OUT Output Delay DIV2OUT to DIV2IN Maximum Delay Time Data Input Setup Time Data Input Hold Time Analog Output Pipeline Delay SYMBOL CONDITIONS fC tPW1 tPW0 tS-RST tH-RST tD-DIV 2T-tm tS tH tPD (A) tPD (B) tDO fC tPW1 tPW0 tS-RST tH-RST tS tH tPD (A) tPD (B) tDO CL = 10pF 125 3.5 3.5 0 1.0 5.5 1.0 5.0 5.0 6.5 4 5 5.5 8 2T - 7 6.0 100 4.5 3.0 1.0 3.0 8.0 1.0 5.0 6.5 9.5 4 5 7.5 12.0 2T - 7 8.5 125 3.5 3.5 4.0 0 5.5 1.0 5.0 5.0 6.5 4 5 5.5 8 2T - 7 6.0 MSPS ns ns ns ns ns ns ns ns CLK CLK ns Analog Output Delay MUX.1B MODE Maximum Conversion Rate Clock High Pulse Width Clock Low Pulse Width Reset Signal Setup Time Reset Signal Hold Time Data Input Setup Time Data Input Hold Time Analog Output Pipeline Delay 125 3.5 3.5 0 1.0 1.0 4.0 5.0 2 3 5.5 6.0 100 4.5 3.0 1.0 3.0 1.0 6.0 6.5 2 3 7.5 8.5 125 3.5 3.5 4.0 0 1.0 4.0 5.0 2 3 5.5 6.0 MSPS ns ns ns ns ns ns CLK CLK ns Analog Output Delay AC Specifications MUX.2, SEL.A, and SEL.B Modes CLK SIGNAL LEVEL RESET SIGNAL LEVEL PECL (NOTE 2) MIN TYP MAX MIN TTL (NOTE 2) TYP MAX UNITS PARAMETER MUX.2 MODE Maximum Conversion Rate Clock High Pulse Width Clock Low Pulse Width DIV2IN Signal Setup Time SYMBOL CONDITIONS fC tPW1 tPW0 tS-DIV 125 3.5 3.5 4.5 - - 100 4.5 3.0 2.0 - - MSPS ns ns ns 9 HI3197 AC Specifications MUX.2, SEL.A, and SEL.B Modes CLK SIGNAL LEVEL RESET SIGNAL LEVEL PARAMETER DIV2IN Signal Hold Time Data Input Setup Time Data Input Hold Time Analog Output Pipeline Delay SYMBOL tH-DIV tS tH tPD (A) tPD (B) Analog Output Delay SEL. A, SEL. B MODES Maximum Conversion Rate Clock High Pulse Width Clock Low Pulse Width C2 Signal Setup Time C2 Signal Hold Time Data Input Setup Time Data Input Hold Time Analog Output Pipeline Delay fC tPW1 tPW0 tS-C2 tH-C2 tS tH tPD (A) tPD (B) Analog Output Delay NOTE: 2. The RESET signal is not input in MUX.2, SEL. A, or SEL. B modes. tDO 125 3.5 3.5 1.0 2.5 1.0 2.0 5.0 1 1 5.5 6.0 100 4.5 3.0 1.0 3.5 1.5 3.5 6.5 1 1 7.5 8.5 MSPS ns ns ns ns ns ns CLK CLK ns tDO CONDITIONS MIN 0 1.0 5.0 5.0 PECL (NOTE 2) TYP 2 3 5.5 MAX 6.0 MIN 3.5 1.0 5.0 6.5 TTL (NOTE 2) TYP 2 3 7.5 MAX 8.5 UNITS ns ns ns CLK CLK ns Electrical Characteristics Measurement Circuits +5V DVCC1 DGND1 DVCC2 AVCC2 AVCC0 10 DA0 TO DA9 DB0 TO DB9 AOUTP 50Ω DVM (DIGITAL VOLTMETER) AOUTN 50Ω VSET 937.5mV 10-BIT DATA INPUT HI3197 10 CLK/T 1MHz TTL CLK C1 DGND2 AGND2 PC -5V C2 C3 -5V +5V FIGURE 1. DIFFERENTIAL LINEARITY ERROR, INTEGRAL LINEARITY ERROR 10 HI3197 Electrical Characteristics Measurement Circuits (Continued) +5V I1 I2 I3 I4 DVCC1 DVCC2 AVCC2 AVCC0 HIGH FOR ALL SIDE A DATA 10 DA0 TO DA9 DB0 TO DB9 HI3197 CLK/T 1MHz TTL CLK +5V DIV2IN DIV2OUT PS C1 C2 C3 DGND1 DGND2 AGND2 VSET AOUTP ICC = I1 + I2 + I3 + I4 DICC1 = I1 DICC2 = I2 ALCC2 = I3 ALCC0 = I4 10 LOW FOR ALL SIDE B DATA AOUTN 937.5mV FIGURE 2. CURRENT CONSUMPTION +5V DVCC1 DGND1 DVCC2 AVCC2 AVCC0 AOUTP V HIGH FOR ALL SIDE A DATA 10 DA0 TO DA9 DB0 TO DB9 HI3197 CLK/T 10 LOW FOR ALL SIDE B DATA 50Ω AOUTN V 1MHz TTL CLK +5V PS C1 C2 C3 DGND2 AGND2 VSET 937.5mV -5V -5V +5V 50Ω FIGURE 3. ANALOG OUTPUT CHARACTERISITCS, OUTPUT FULL-SCALE ABSOLUTE AMPLITUDE ERROR, OUTPUT ZERO OFFSET VOLTAGE 11 HI3197 Electrical Characteristics Measurement Circuits (Continued) OSCILLOSCOPE +5V DVCC1 10 DPG (DIGITAL PATTERN GENERATOR) 10 DA0 TO DA9 DB0 TO DB9 CLKP/E CLKN/E DGND1 DVCC2 AVCC2 AVCC0 AOUTP 50Ω 50Ω AOUTN HI3197 VREF VSET 100MHz PECL CLK DGND2 AGND2 C1 C2 C3 +5V -5V -5V FIGURE 4. ANALOG OUTPUT RISE TIME, ANALOG OUTPUT FALL TIME, SETTLING TIME AND GLITCH ENERGY +5V OSCILLOSCOPE DVCC1 DGND1 DVCC2 AVCC2 AVCC0 AOUTP 50Ω HIGH FOR ALL SIDE A DATA 10 DA0 TO DA9 DB0 TO DB9 HIGH FOR ALL SIDE B DATA 10 AVCC0 (= 0V) AOUTN HI3197 CLKP/E CLKN/E 20MHz PECL CLK +5V PS C1 C2 C3 DGND2 AGND2 VSET VREF 1mA 50Ω V 0.1µF 50Ω -5V VFS AOUTP OUTPUT VSET PIN OUTPUT 100mVP-P AGND2 +937.5mV +5V -5V FIGURE 5. REFERENCE/CONTROL AMPLIFIER CHARACTERISITCS, VREF PIN OUTPUT VOLTAGE, VREF PIN OUTPUT VOLTAGE IN POWER SAVING MODE, MULTIPLYING BANDWIDTH 12 HI3197 Electrical Characteristics Measurement Circuits (Continued) AVCC0 AVCC0 - VOF AOUTP OUTPUT (INV = 1) AVCC0 - VFS (AVCC0 - VOF) - (AVCC0 - VFS) 1023 V(n + 1) - V(n) = 1 LSB D.L.E. = 1 LSB (V(n) - n x 1 LSB 1 LSB -1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 I.L.E. = V (n + 1) V (n) 0 0 0 0 0 D9 (MSB) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 D0 (LSB) DATA INPUT CODE FIGURE 6. TABLE 1. I/O CORRESPONDENCE TABLE DATA INPUT CODE INV = 1 (MSB) D9 1111111111 • • • 0000000000 (LSB) D0 (MSB) D9 0000000000 • • • 1111111111 INV = 0 (LSB) D0 ANALOG OUTPUT LEVEL AOUTP AVCC0 - VOF • • • AVCC0 - VFS AOUTN AVCC0 - VFS • • • AVCC0 - VOF 13 HI3197 Description of Operation The HI3197 has four types of operation modes to support various applications. The operation mode is set by switching the function setting pins (C1, C2 and C3). The HI3197 can input data divided into two systems: A (DA0 to DA9) and B (DB0 to DB9), internally multiplex the data, and output it as an analog signal, making it possible to halve the data rate. This lets the HI3197 support the TTL data input level in contrast to the ECL data input level for conventional high-speed D/A converters. The clock signal and reset signal input levels can be selected from either TTL or PECL according to the application. (However, setting both signals to either TTL or PECL input level is recommended.) timing at which the data output delay of the HI3197 front-end system matches with the hold time during HI3197 data input can be easily set by inputting this synchronized data to the data input pins and the DlV2OUT signal to the DlV2lN pin. The data can be divided and input to two systems: A (DA0 to DA9) and B (DB0 to DB9), internally multiplexed, and extracted as analog output. When using the multiple HI3197 in MUX.1A mode, the start timing of the 1/2 frequency-divided clocks becomes out of phase, producing operation such as that shown in Figure 7. As a countermeasure, the MUX.1A mode has a function that matches the start timing of the 1/2 frequency-divided clocks with the reset signal. When using a PECL level reset signal, input the reset signal to Pins 23 and 24 (RESETP/E, RESETN/E) and leave Pin 22 (RESET/T) open. When using a TTL level reset signal, input the reset signal to Pin 22 (RESET/T) and leave Pins 23 and 24 (RESETP/E, RESETN/E) open. The reset polarity can be switched by the R POLARITY pin (Pin 39). When the R POLARITY pin is High or open, reset is active Low; when Low, reset is active High. See Figure 7 for the detailed timing. MUX.1A Mode Set C1, C2 and C3 all Low for this mode. In MUX.1A mode, the frequency of the clock input from the clock input pin is halved internally, and the 1/2 frequencydivided signal is output at TTL level from the DlV2OUT pin. Data synchronized with the DlV2OUT signal (the signal output from the DlV2OUT pin) can be obtained by operating the HI3197 front-end system with the DlV2OUT signal. The TABLE 2. OPERATING MODES MODE MUX.1A MUX.1B MUX.2 SELE.A SELE.B C1 0 C2 0 0 1 0 1 C3 0 1 0 0 0 CLK IN (MSPS) 125 125 125 125 125 DATA IN (Mbps) 62.5 62.5 62.5 125 125 AOUT (Mbps) 125 125 125 125 125 DIV2OUT PIN Outputs CLK/2 at TTL Level High Impedance High Impedance High Impedance High Impedance DESCRIPTION OF OPERATION MUX Operation by the Internal CLK/2 MUX Operation by the Internal CLK/2 MUX Operation by DIV2IN D/A Conversion of Side A Data Input D/A Conversion of Side B Data Input 0 0 1 1 CLOCK INPUT PIN CLOCK INPUT 1/2 DIV2OUT PIN (DIV2OUT SIGNAL) DIV2IN PIN HI3197 (MUX.1A MODE) tD - DIV 10-BIT DATA A HI3197 FRONT-END SYSTEM 10-BIT 10-BIT DATA B 10-BIT DA0 TO DA9 DB0 TO DB9 DATA INPUT PINS FRONT-END SYSTEM DATA OUTPUT DELAY II HI3197 DATA INPUT HOLD TIME FIGURE 7A. MUX.1A 14 HI3197 CLK HI3197 CLK CLK DIV2OUT DIV2OUT HI3197 CLKDIV2OUT DIV2OUT FIGURE 7B. MUX.1A EXAMPLE WHEN NOT USING THE RESET SIGNAL CLK RESET SIGNAL (WHEN ACTIVE LOW) HI3197 CLK CLK DIV2OUT RESET DIV2OUT HI3197 CLKDIV2OUT RESET SIGNAL RESET DIV2OUT FIGURE 7C. MUX.1A EXAMPLE WHEN USING THE RESET SIGNAL FIGURE 7. MUX.1A MODE MUX.1B Mode Set C1 and C2 Low and C3 High for this mode. In MUX.1B mode, the frequency of the clock input from the clock input pin is halved internally, and the data is loaded by this 1/2 frequency-divided signal. The 1/2 frequency-divided signal cannot be observed at this time, so the data is actually loaded by observing the clock and reset signals to estimate the rising edge of the internally 1/2 frequency-divided signal. The data can be divided and input to two systems: A (DA0 to DA9) and B (DB0 to DB9). The data is internally multiplexed, then the system A data is output as an analog signal with a 2-clock pipeline delay, and the system B data as an analog signal with a 3-clock pipeline delay after loading by the clock. Like MUX.1A mode, when using the multiple HI3197 in MUX.1B mode, the start timing of the 1/2 frequency-divided clocks becomes out of phase, producing operation such as that shown in the example below. As a countermeasure, the MUX.1B mode also has a function that matches the start timing of the 1/2 frequency-divided clocks with the reset signal. When using a PECL level reset signal, input the reset signal to Pins 23 and 24 (RESETP/E, RESETN/E) and leave Pin 22 (RESET/T) open. When using a TTL level reset signal, input the reset signal to Pin 22 (RESET/T) and leave Pins 23 and 24 (RESETP/E, RESETN/E) open. The reset polarity can be switched by the R POLARITY pin (Pin 39). When the R POLARITY pin is High or open, reset is active Low; when Low, reset is active High. See Figure 8 for the detailed timing. 15 HI3197 HI3197 (MUX. 1B MODE) CLOCK INPUT PIN CLOCK RESET SIGNAL (WHEN ACTIVE LOW) INTERNALLY 1/2 FREQUENCY-DIVIDED SIGNAL (THIS SIGNAL CANNOT BE OBSERVED) tS tH DA0 TO DA9 DB0 TO DB9 DATA INPUT SIGNAL tH-RST tS-RST RESET INPUT PIN 1/2 AFTER THE RESET IS RELEASED, THE INTERNAL 1/2 FREQUENCY-DIVIDED SIGNAL COMMENCES AT THE FIRST CLOCK EDGE, SO BE SURE TO INPUT THE DATA IN A MANNER THAT SATISFIES THE SETUP TIME (TS) AND HOLD TIME (TH) WITH RESPECT TO THIS CLOCK EDGE. FIGURE 8A. CLK HI3197 CLK CLK INTERNALLY 1/2 FREQUENCY-DIVIDED SIGNAL HI3197 CLK INTERNALLY 1/2 FREQUENCY-DIVIDED SIGNAL FIGURE 8B. EXAMPLE WHEN NOT USING THE RESET SIGNAL CLK RESET SIGNAL (WHEN ACTIVE LOW) INTERNALLY 1/2 FREQUENCY-DIVIDED SIGNAL HI3197 CLK CLK RESET HI3197 CLK RESET SIGNAL RESET INTERNALLY 1/2 FREQUENCY-DIVIDED SIGNAL FIGURE 8C. EXAMPLE WHEN USING THE RESET SIGNAL FIGURE 8. MUX.1B MODE 16 HI3197 MUX.2 Mode Set C1 and C3 Low and C2 High for this mode. In MUX.2 mode, the clock is input to the clock input pin, and the signal with a cycle half that of the clock (hereafter, DlV2lN signal) is input to the DlV2IN pin at TTL level. The DlV2lN signal is internally latched by the clock, so consideration must be given to the setup time (tS_DIV) and hold time (tH_DIV) with respect to the clock. In addition, the data is loaded by the DlV2lN signal, so consideration must also be given to the setup time (tS) and hold time (tH) with respect to the DlV2IN signal. The data can be divided and input to two systems: A (DA0 to DA9) and B (DB0 to DB9). The data `is internally multiplexed, then the system A data is output as an analog signal with a 2-clock pipeline delay, and the system B data as an analog signal with a 3-clock pipeline delay from the clock that loads the DIV2IN signal. See Figure 9 for the detailed timing. SELECT.A Mode and SELE.B Mode Set C1 High and C2 and C3 Low for SELE.A mode. In SELE.A mode, the clock is input to the clock input pin, and the data is input to the system A (DA0 to DA9) data input pins. Set C1 and C2 High and C3 Low for SELE.B mode. In SELE.B mode, the clock is input to the clock input pin, and the data is input to the system B (DB0 to DB9) data input pins. In either mode, consideration must be given to the setup time, (tS) and hold time (tH) with respect to the clock. Also, the data is output as an analog signal with a 1-clock pipeline delay after loading by the clock. Switching between SELE.A mode and SELE.B mode is done by switching the C2 pin between High and Low levels. Also, the mode can be switched at high speed in sync with the clock by inputting the switching signal (02 signal) to the C2 pin. The C2 signal is internally latched by the clock, so consideration must be given to the setup time (tS_C2) and hold time (tH_C2) with respect to the clock. See Figure 10 for the detailed timing. tPD (B) tPD (A) 0 CLOCK tS_DIV DIV2IN SIGNAL SYSTEM A DATA A0 tS A1 tH A2 DA0 TO DA9 tH_DIV DIV2IN INPUT PIN 1 2 3 CXA3197 (MUX.2 MODE) CLOCK INPUT PIN DB0 TO DB9 SYSTEM B DATA B0 B1 B2 ANALOG OUTPUT SIGNAL A0 B0 A1 B1 FIGURE 9. MUX.2 MODE tPD (A) 0 CLOCK 1 tPD (B) 0 1 CLOCK INPUT PIN tA_C2 tS tH DA0 TO DA9 SYSTEM A DATA A0 A1 A2 A6 A8 SELECT SYSTEM B DATA B3 B4 B5 B7 DB0 TO DB9 tH_C2 C2 INPUT PIN CXA3197 (SELE.A MODE/SELE.B MODE) C2 SIGNAL ANALOG OUTPUT SIGNAL A0 A1 A2 B3 B4 B5 A6 FIGURE 10. SELECT A MODE AND SELECT B MODE 17 HI3197 Block Diagram and Timing Charts CLK RESET R D DIV2OUT DIV2IN Q CLK/2 Q (INTERNAL) INPUT DATA A INPUT LATCH A LATCH MUX LATCH DAC ANALOG OUT INPUT DATA B INPUT LATCH B LATCH FIGURE 11A. BLOCK DIAGRAM (MUX.1A MODE) tPD tPW1 tPW0 CLK tS-RST RESET CLK/2 (INTERNAL) DIV2OUT TO DIV2IN INPUT DATA A INPUT DATA B N$ N$ ACTIVE HIGH ACTIVE LOW tD-DIV tM 2t-tM tS N tH N+2 N+4 tH-RST 0 1 2 3 4 5 tPD (A) N$ N$ N+1 N+3 N+5 tDO N$ N N+1 N$ N$ N$ tDO FIGURE 11B. TIMING CHART (MUX.1A MODE) PECL CLK ±1/2 LSB 2.0V TTL 0.8V 2.0V 0.8V ANALOG OUTPUT ±1/2 LSB tDO tSET FIGURE 11C. TIMING JUDGMENT POINTS NOTE: In MUX.1A mode, Data A and Data B are internally multiplexed and then the resulting signal can be analog output. The frequency of the clock is halved by the built-in clock frequency divider circuit and the CLK/2 can be output at TTL level (D1V201.~). CLK/2 can be reset by the reset signal. 18 HI3197 Block Diagram and Timing Charts CLK RESET RQ DQ (Continued) CLK/2 (INTERNAL) INPUT DATA A INPUT LATCH A MUX LATCH DAC ANALOG OUT INPUT DATA B INPUT LATCH B FIGURE 12A. BLOCK DIAGRAM (MUX.1B MODE) tPD (B) tPW1 tPW0 tPD (A) CLK RESET (ACTIVE HIGH) CLK/2 (INTERNAL) tS-RST tH-RST 0 1 2 3 (ACTIVE HIGH) (ACTIVE LOW) D-FF OUT tS INPUT DATA A N-2 N tH N+2 N+4 N+6 N+8 INPUT DATA B N-1 N+1 N+3 N+5 N+7 N+9 tDO N+2 N+3 N+4 N+5 N N+1 tDO FIGURE 12B. TIMING CHART (MUX.1B MODE) NOTE: In MUX.1B mode, Data A and Data B are internally multiplexed and then the resulting signal can be analog output. The frequency of the clock is halved by the built-in clock frequency divider circuit. CLK/2 can be reset by the reset signal. 19 HI3197 Block Diagram and Timing Charts CLK RQ DIV2IN DQ (Continued) CLK/2 (INTERNAL) A INPUT DATA A INPUT LATCH A LATCH MUX LATCH DAC ANALOG OUT B INPUT DATA B INPUT LATCH B LATCH FIGURE 13A. BLOCK DIAGRAM (MUX.2 MODE) tPD (B) tPW1 tPW0 tPD (A) CLK tS-DIV DIV1IN tS M/S DATA A N-2 N tH N+2 N+4 N+6 N+8 tH-DIV 0 1 2 3 M/S DATA B N-1 N+1 N+3 N+5 N+7 N+9 tDO N N+1 tDO N+3 N+2 N+4 N+5 FIGURE 13B. TIMING MODE (MUX.2 MODE) NOTE: In MUX.2 mode, the 1/2 frequency-divided clock signal (DlV2lN) and Data A and Data B, which are synchronized with DlV2lN, are provided simultaneously. These signals are internally multiplexed and the resulting signal can be analog output. 20 HI3197 Block Diagram and Timing Charts CLK (Continued) C2 LATCH INPUT DATA A INPUT LATCH A SELECT LATCH DAC ANALOG OUT INPUT DATA B INPUT LATCH B FIGURE 14A. BLOCK DIAGRAM (SELE.A, SELE.B MODE) tPW1 tPW0 tPD (A) tPD (B) CLK 0 1 tH-C2 0 tS-C2 1 C2 tS INPUT DATA A N - 2 N tH N+2 N+4 N+6 N+8 INPUT DATA B N - 1 N+1 N+3 N+5 SELE. A N+7 N+9 C2 M/S OUT SELE. B tDO tDO N-4 N-2 N+5 N N+2 N+7 FIGURE 14B. TIMING CHART (SELE.A, SELE.B MODE) NOTE: In SELE.A and SELE.B modes, input Data A or Data B is selected and the selected data can be analog output. When C1 = 1 and C3 = 0, Data A is selected for C2 = 0, and Data B is selected for C2 = 1. 21 HI3197 Typical Performance Curves 1100 OUTPUT FULL-SCALE VOLTAGE (mV) RL = 50Ω 1000 OUTPUT FULL-SCALE VOLTAGE (mV) 1100 RL = 50Ω VSET = AGND2 + 937.5mW 1050 900 1000 800 950 700 0.65 0.84 VSET PIN VOLTAGE (V) 1.03 900 -25 25 0 50 AMBIENT TEMPERATURE (oC) 75 FIGURE 15. OUTPUT FULL-SCALE VOLTAGE vs VSET PIN VOLTAGE FIGURE 16. OUTPUT FULL-SCALE VOLTAGE vs AMBIENT TEMPERATURE 1280 OUTPUT ZERO OFFSET VOLTAGE (mV) 7 RL = 50Ω VSET = AGND2 + 937.5mW VREF PIN VOLTAGE (mV) 6 1260 5 1240 4 1220 -25 0 50 25 AMBIENT TEMPERATURE (oC) 75 3 -25 0 50 25 AMBIENT TEMPERATURE (oC) 75 FIGURE 17. VREF PIN VOLTAGE vs AMBIENT TEMPERATURE FIGURE 18. OUTPUT ZERO OFFSET VOLTAGE vs AMBIENT TEMPERATURE ANALOG OUTPUT AMPLITUDE (dB) 0 -3 1 10 VSET PIN INPUT FREQUENCY (MHz) 100 FIGURE 19. MULTIPLYING BANDWIDTH 22 HI3197 Application Circuit The circuit shown below is the basic circuit when the analog output is terminated with the external resistance of 50Ω in the dual ±5V power supplies for MUX.2 mode. The analog output full scale voltage VFS is obtained with the following equation: R = RO //RL V SET 63 V FS = -------------- x  15 + -----  x R  375 64 RO : Output impedance ( = 50Ω) RL : External termination resistance R2 Here, V SET = --------------------- V REF R1 + R2 ( V REF ≈ 1.2V ) ( R1 + R2 ≥ 1.2k Ω ) +5V (A) -5V (A) 0V (D) 0V(A) 48 47 46 45 44 43 42 41 40 39 38 37 DGND1 DVCC1 (MSB) DA9 DA6 DA7 INV NC PS VOCLP POLARITY AGND2 AVCC2 36 VSET 35 VREF 34 AGND2 33 AOUTP 32 AOUTN 31 AVCC0 30 DVCC2 29 C3 28 C2 27 C1 26 DGND2 25 RESETN/E RESETP/E DB0 (LSB) DIV2OUT RESET/T CLKN/E CLKP/E DIV2N CLK/T -5V(D) RL 0V(A) 0V(A) 0V(D) 0V(A) RL -5V(A) 0V(A) R1 DA8 1 DA0 TO DA9 RAM LATCH ETC. DB0 TO DB9 2 3 4 5 6 7 8 9 DA5 DA4 DA3 DA2 DA1 DA0 (LSB) DB9 (MSB) DB8 DB7 0V(A) R2 -5V(A) 10 DB6 11 DB5 12 DB4 DB3 DB2 13 14 15 16 17 18 19 20 21 22 23 24 82 +5V(D) 130 0V(D) 82 VBB 130 TTL CLK/2 PECL CLK NOTE: Application circuits shown are typical examples illustrating the operation of the devices. Intersil Corporation cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 23 DB1 HI3197 Notes on Use • The HI3197 has PECL and TTL input pins for the clock and reset inputs. When the clock is input at PECL level, it is recommended to also input the reset signal at PECL level. Likewise, when the clock is input at TTL level, it is recommended to also input the reset signal at TTL level. • The input signal impedance should be properly matched to ensure the stable HI3197 operation at high speed. Particularly when ringing appears in the input clock in the MUX.1A and MUX.1B modes. If this ringing exceeds the clock input threshold value, the internal 1/2 frequency divider circuit may misoperate. • All TTL input pins of the HI3197 except for the PS pin go to High level when left open, and only the PS pin goes to Low level when left open. Set the PS pin to High level to operate the IC. When the PECL input pins are left open, the P (positive) side goes to High level and the N (negative) side goes to Low level. The PECL input pins are complementary, so be sure to use the P and N sides together. • When the clock and reset input signal level is TTL, ***/T pins should be used and ***/E pins left open. When the clock and reset input signal level is PECL, ***/E pins should be used and ***/T pins left open. • The power supply and grounding have a profound influence on converter characteristics. The power supply and grounding method are particularly important during highspeed operation. General points for caution are as follows: - The ground pattern should be as wide as possible. It is recommended to make the power supply and ground wider at an inner layer using a multi-layer board. To prevent a DC offset from being generated between the analog and digital power supply patterns, it is recommended to connect the patterns at one point via a ferrite-bead filter, etc. - When using the HI3197 with a single power supply, connect DGND1 and DGND2 to a common digital ground, and AGND2 to an analog ground. Also, DVCC1 and DVCC2 should use a common digital power supply, and AVCC2 should be connected to an analog power supply. AVCC0 serves as the analog output reference, so while it does not need to share the analog power supply, it should be used within the range that satisfies the analog output compliance voltage. - When using the HI3197 with dual power supply, connect DGND1 and DVCC2 to the digital ground, and AVCC2 to the analog ground. DVCC1 uses a positive digital power supply (+5V, typ.), DGND2 uses a negative digital power supply (-5V, typ.), and AGND2 uses a negative analog power supply (-5V, typ.). Like when using a single power supply, the AVCC0 pin can be used within the range that satisfies the analog output compliance voltage. However, connecting it to the analog ground and using the analog ground as the reference for the analog output is recommended. • Ground the power supply pins as close to each pin as possible with a 0.1µF or more ceramic chip capacitor. When using a single power supply, connect DVCC1 and DVCC2 to the digital ground, and AVCC2 and AVCC0 to the analog ground. When using dual power supply, connect DVCC1 and DGND2 to the digital ground, and AGND2 to the analog ground. In this case, when using AVCC0 within the range that satisfies the compliance voltage, be sure to also connect the AVCC0 pin to the analog ground using a ceramic chip capacitor. • The HI3197 is designed with an analog output impedance of 50Ω . The analog outputs are wired with a characteristic impedance of 50Ω , and waveforms free of reflection can be obtained by terminating the analog outputs with 50Ω . Even when using only one of either AOUTP or AOUTN, if one analog output is terminated with 50Ω, be sure to also terminate the other analog output with 50Ω . (See Application Circuit Diagram) 24 HI3197 Metric Plastic Quad Flatpack Packages (MQFP/PQFP) D D1 Q48.7x7-S 48 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE INCHES SYMBOL A A1 B D MIN 0.056 0.000 0.006 0.347 0.272 0.347 0.272 0.012 48 0.020 BSC MAX 0.066 0.007 0.010 0.362 0.279 0.362 0.279 0.027 MILLIMETERS MIN 1.40 0.00 0.15 8.80 6.90 8.80 6.90 0.30 48 0.500 BSC MAX 1.70 0.20 0.26 9.20 7.10 9.20 7.10 0.70 NOTES 5 2 3, 4 2 3, 4 6 Rev. 1 4/95 NOTES: A SEATING PLANE E E1 D1 E E1 L e PIN 1 N e -H- 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. Dimensions D and E to be determined at seating plane -C- . 3. Dimensions D1 and E1 to be determined at datum plane -H- . 4. Dimensions D1 and E1 do not include mold protrusion. 5. Dimension B does not include dambar protrusion. 6. “N” is the number of terminal positions. 0.10 0.004 0.24 M B 0o-10o A1 -C- L 0.107/0.177 0.004/0.007 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 25