HI3246

HI3246 Data Sheet March 2000 File Number 4517.1 8-Bit, 120MSPS, Flash A/D Converter The HI3246 is an 8-bit, high-speed, flash analog-to-digital converter optimized for high speed, low power, and ease of use. With a 120MSPS encode rate capability and full-power analog bandwidth of 200MHz, this component is ideal for applications requiring the highest possible dynamic performance. To minimize system cost and power dissipation, only a +5V power supply is required. The HI3246 clock input interfaces directly to TTL, ECL or PECL logic and will operate with singleended inputs. The user may select 16-bit demultiplexed output or 8-bit single channel digital outputs. The demultiplexed mode interleaves the data through two 8-bit channels at 1/2 the clock rate. Operation in demultiplexed mode reduces the speed and cost of external digital interfaces, while allowing the A/D converter to be clocked to the full 120MSPS conversion rate. Fabricated with an advanced Bipolar process, the HI3246 is provided in a space-saving 48-lead MQFP surface mount plastic package and is specified over the -20oC to 75oC temperature range. Features • Differential Linearity Error. . . . . . . . . . . . . . . . . . ±0.5 LSB • Integral Linearity Error . . . . . . . . . . . . . . . . . . . . ±0.5 LSB • Integral Linearity Compensation Circuit • Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . 10pF • Wide Analog Input Bandwidth . . . . . . . . . . . . . . . 250MHz • Low Power Consumption . . . . . . . . . . . . . . . . . . . 500mW • 1:2 Demultiplexed Output Pin • Internal 1/2 Frequency Divider Circuit (w/Reset Function) • CLK/2 Clock Output • Compatible with PECL, ECL and TTL Digital Input Levels • Direct Replacement for Sony CXA3246Q Applications • RGB Video (LCD, PDP) • Digital Oscilloscopes • Digital Communications (QPSK, QAM) Ordering Information PART NUMBER HI3246JCQ TEMP. RANGE (oC) -20 to 75 PACKAGE 48 Ld MQFP PKG. NO. Q48.12x12-S • Magnetic Recording (PRML) Pinout HI3246 (MQFP) TOP VIEW RESETN/E RESET/E RESETN/T SELECT INV CLKOUT DVCC2 DGND2 PBD7 PBD6 PBD5 DVEE3 VRB AGND VRM1 AVCC VIN VRM2 AVCC VRM3 AGND VRT DGND3 1 2 3 4 5 6 7 8 9 10 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 PBD4 PBD3 PBD2 PBD1 PBD0 DGND2 DVCC2 DVCC1 DGND1 PAD7 PAD6 PAD5 PAD4 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 DVCC2 CLK/T NC CLKN/E DGND2 PAD0 PAD1 NC CLK/E NC PAD2 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 PAD3 HI3246 Block Diagram AVCC 5 VRT 11 R1 R/2 R/2 1 R 39 PBD6 2 R 63 VRM3 9 R 64 R 35 PBD2 65 6 BITS R 126 R 127 VRM2 VIN 7 6 R 129 6 BITS R 191 VRM1 4 R LATCHB TTLOUT 192 R 193 R 254 R 255 R/2 VRB CLK/T CLK/E CLKN/E 2 R/2 21 PAD0 (LSB) DELAY 16 17 18 14 D RESETN/T RESETN/E RESET/E 46 48 47 3 10 45 29 20 32 41 1 DVEE3 Q SELECT Q 43 CLKOUT NC 6 BITS 23 PAD2 22 PAD1 26 PAD5 25 PAD4 24 PAD3 27 PAD6 R 128 ENCODER 6-BIT LATCH AND ENCODER 34 PBD1 33 P1D0 (LSB) 8 BITS 6 BITS 38 PBD5 LATCHA TTLOUT 37 PBD4 36 PBD3 (MSB) 40 PBD7 8 INV 44 DVCC1 30 DVCC2 19 31 42 DGND3 12 (8 BITS) (MSB) 28 PAD7 15 13 AGND SELECT DGND1 DGND2 2 HI3246 Absolute Maximum Ratings TA = 25oC Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (Lead Tips Only) Supply Voltage (AVCC , DVCC1, DVCC2) . . . . . . . . . . -0.5V to +7.0V (DGND3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V (DVEE3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7.0V to +0.5V (DGND3 - DVEE3) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Analog Input Voltage (VIN). . . . . . . . . . . . . . . . . VRT - 2.7V to AVCC Reference Input Voltage (VRT). . . . . . . . . . . . . . . . . +2.7V to AVCC (VRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VIN - 2.7V to AVCC (|VRT - VRB|) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.5V Digital Input Voltage PECL/ECL . . . . . . . . . . . . . . . . . . . DVEE3 - 0.5 to DGND3 + 0.5 TTL . . . . . . . . . . . . . . . . . . . . . . . . . DGND3 - 0.5 to DVCC1 + 0.5 VID (|***/E - ***N/E| (Note 2)) . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V Recommended Operating Conditions WITH A SINGLE POWER SUPPLY MIN TYP MAX Supply Voltage DVCC1 , DVCC2 , AVCC . . . . . . . . . . . . . . . +4.75 +5.0 +5.25V DGND1, DGND2, AGND . . . . . . . . . . . . . -0.05 0 +0.05V DGND3. . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75 +5.0 +5.25V DVEE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05 0 +0.05V Analog Input Voltage (VIN). . . . . . . . . . . . . . VRB VRT Reference Input Voltage VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.9 +4.1V VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.4 +2.6V |VRT - VRB|. . . . . . . . . . . . . . . . . . . . . . . . +1.5 +2.1V Digital Input Voltage PECL (***/E) VIH . . . . . . . . . . . . . . DVEE3 + 1.5 DGND3 PECL (***/E) VIL . . . . . . . . . . . . . . . DVEE3 + 1.1 VIH - 0.4V TTL (***/T, INV) VIH . . . . . . . . . . . . . . . . . +2.0V TTL (***/T, INV) VIL . . . . . . . . . . . . . . . . . +0.8V Other (SELECT) VIH . . . . . . . . . . . . . . . . DVCC1 Other (SELECT) VIL . . . . . . . . . . . . . . . . . DGND1 VID (Note 2) (|***/E- ***N/E|) . . . . . . . . . . +0.4 +0.8 Max Conversion Rate (fC, Straight Mode) . . . 100 MSPS Max Conversion Rate (fC, DMUX Mode) . . . . 120 MSPS Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC WITH DUAL POWER SUPPLIES MIN TYP MAX Supply Voltage DVCC1 , DVCC2 , AVCC . . . . . . . . . . . . . . . +4.75 +5.0 +5.25V DGND1, DGND2, AGND . . . . . . . . . . . . . -0.05 0 +0.05V DGND3. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05 0 +0.05V DVEE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5 -5.0 -4.75V Analog Input Voltage (VIN). . . . . . . . . . . . . . VRB VRT Reference Input Voltage VRT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.9 +4.1V VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.4 +2.6V |VRT - VRB|. . . . . . . . . . . . . . . . . . . . . . . . +1.5 +2.1V Digital Input Voltage PECL/ECL VIH . . . . . . . . . . . . . . . . . . . . . . . DVEE3 + 1.5 DGND3 PECL/ECL VIL . . . . . . . . . . . . . . . . . . . . . . . DVEE3 + 1.1 VIH - 0.4 TTL (***/T, INV) VIH . . . . . . . . . . . . . . . . . 2.0 TTL (***/T, INV) VIL . . . . . . . . . . . . . . . . . +0.8V Other (SELECT) VIH . . . . . . . . . . . . . . . . DVCC1 Other (SELECT) VIL . . . . . . . . . . . . . . . . . DGND1 VID (Note 2) (|***/E- ***N/E|) . . . . . . . . . . +0.4 0.8 Max Conversion Rate (fC, Straight Mode) . . . 100 MSPS Max Conversion Rate (fC, DMUX Mode) . . . . 120 MSPS Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on an evaluation PC board in free air. 2. VID : Input Voltage Differential. Electrical Specifications PARAMETER Resolution DC CHARACTERISTICS Integral Linearity Error, INL Differential Linearity Error, DNL ANALOG INPUT Analog Input Capacitance, CIN Analog Input Resistance, RIN Analog Input Current, IIN DVCC1 , 2 , AVCC , DGND3 = +5V, DGND1, 2, AGND, DVEE3 = 0V, VRT = 4V, VRB = 2V, TA = 25oC TEST CONDITIONS MIN TYP 8 MAX ±0.5 ±0.5 40 285 UNITS Bits VIN = 2VP-P , fC = 5MSPS - - LSB LSB VIN = +3.0V, +0.07VRMS 7 0 10 20 100 pF kΩ µA 3 HI3246 Electrical Specifications PARAMETER REFERENCE INPUT Reference Resistance (Note 3), RREF Reference Current (Note 4), IREF Offset Voltage VRT Side, EOT Offset Voltage VRB Side, EOB DIGITAL INPUT (PECL/ECL) Digital Input Voltage: High, VIH Digital Input Voltage: Low, VIL Threshold Voltage, VTH Digital Input Current: High, IIH Digital Input Current: Low, IIL Digital Input Capacitance DIGITAL INPUT (TTL) Digital Input Voltage: High, VIH Digital Input Voltage: Low, VIL Threshold Voltage, VTH Digital Input Current: High, IIH Digital Input Current: Low, IIL Digital Input Capacitance DIGITAL OUTPUT (TTL) Digital Output Voltage: High, VOH Digital Output Voltage: Low, VOL SWITCHING CHARACTERISTICS Maximum Conversion Rate, fC Aperture Jitter, tAJ Sampling Delay, tDS Clock High Pulse Width, tPW1 Clock Low Pulse Width, tPW0 RESET Signal Setup Time, tRS RESET Signal Hold Time, tRH CLKOUT Output Delay, tDCLK Data Output Delay (Note 5), tDO1 tDO2 Output Rise Time, tr Output Fall Time, tf DYNAMIC CHARACTERISTICS Input Bandwidth S/N Ratio VIN = 2VP-P , -3dB fC = 120MSPS, fIN = 1kHz Full Scale, DMUX Mode fC = 120MSPS, fIN = 29.999MHz Full Scale, DMUX Mode Error Rate (Note 6) fC = 120MSPS, fIN = 1kHz Full Scale, DMUX Mode, Error > 16 LSB fC = 120MSPS, fIN = 29.999MHz Full Scale, DMUX Mode, Error > 16 LSB fC = 100MSPS, fIN = 24.999MHz Full Scale, Straight Mode, Error > 16 LSB 250 46 42 10-12 10-9 10-9 MHz dB dB TPS TPS TPS CLK CLK RESETN-CLK RESETN-CLK CL = 5pF DEMUX Mode (CL = 5pF) (CL = 5pF) 0.8 to 2.0V 0.8 to 2.0V (CL = 5pF) (CL = 5pF) DMUX Mode 120 1.2 3.0 4.5 1.0 -0.5 3.0 3.5 10 1.4 4.5 t + 0.5 5.0 1 1 1.6 7.0 7.0 MSPS ps ns ns ns ns ns ns ns ns ns ns IOH = -2mA IOL = 1mA 2.4 0.5 V V VIH = 3.5V VIL = 0.2V 2.0 -10 -20 1.5 0.8 0 0 5 V V V µA µA pF VIH = DGND3 - 0.8V VIL = DGND3 - 1.6V DVEE3 + 1.5 DVEE3 + 1.1 -50 -75 DGND3 - 1.2 DGND3 VIH - 0.4 +50 0 5 V V V µA µA pF 400 2.7 6 0 600 3.3 8 1.5 740 5.0 10 3 Ω mA mV mV DVCC1 , 2 , AVCC , DGND3 = +5V, DGND1, 2, AGND, DVEE3 = 0V, VRT = 4V, VRB = 2V, TA = 25oC (Continued) TEST CONDITIONS MIN TYP MAX UNITS 4 HI3246 Electrical Specifications PARAMETER POWER SUPPLY Supply Current, ICC + IEE AVCC Pin Supply Current, AICC DVCC1 Pin Supply Current, DICC1 DVCC2 Pin Supply Current, DICC2 DGND3 Pin Supply Current, IEE Power Consumption, PD*6 NOTES: 3. RREF: Resistance value between VRT and VRB . V RT – V RB 4. I REF = ---------------------------- . R REF DVCC1 , 2 , AVCC , DGND3 = +5V, DGND1, 2, AGND, DVEE3 = 0V, VRT = 4V, VRB = 2V, TA = 25oC (Continued) TEST CONDITIONS MIN TYP MAX UNITS 70 45 20 5 0.5 400 98 500 140 87 36 15 1.5 700 mA mA mA mA mA mW 1 5. t = ---- . fC 6. The unit of measure TPS: Times Per Sample. ( V RT – V RB ) 2 7. P D = ( I CC + I EE ) • V CC + ------------------------------------ . V REF Timing Diagrams N-1 VIN N+2 tDS N t N+1 N+3 CLK tPW1 tPW0 tD02 2V N 0.8V N+2 PAD0 TO D7 N-2 PBD0 TO D7 tDCLK 2V CLK OUT 0.8V N-1 tD01 t + 1ns 2V 0.8V 2V 0.8V N+1 N+3 RESET PULSE tPWR FIGURE 1. DEMUX MODE TIMING CHART (SELECT = VCC) 5 HI3246 Timing Diagrams N+2 N+1 N+3 N-1 VIN tDS N t CLK tPW1 tPW0 2.0V 0.8V 2.0V 0.8V PAD0 TO D7 N-4 N-3 N-2 N-1 N PBD0 TO D7 N-5 N-4 N-3 N-2 N-1 tD02 CLK OUT (CLK IS INVERTED AND OUTPUT) 8ns 2.0V 0.8V tDCLK RESET PULSE FIGURE 2. STRAIGHT MODE TIMING CHART (SELECT = GND) DGND3 VIH (MAX) VIL VTH (DGND3 - 1.2V) VID VIH VIL (MIN) FIGURE 3. PECL SWITCHING LEVEL Pin Descriptions PIN NO 3, 10 5, 8 20, 29 32, 41 19, 30 31, 42 12 SYMBOL AGND AVCC DGND1 DGND2 DVCC1 DVCC2 DGND3 I/O GND +5V (Typ) GND +5V (Typ) +5V (Typ) (With a Single Power Supply) GND (With Dual Power Supplies) TYPICAL VOLTAGE LEVEL EQUIVALENT CIRCUIT DESCRIPTION Analog Ground. Separated from the digital ground. Analog Power Supply. Separated from the digital power supply. Digital Ground. Digital Power Supply. Digital Power Supply. Apply -5V for PECL and TTL input. 6 HI3246 Pin Descriptions PIN NO 1 SYMBOL DVEE3 I/O (Continued) TYPICAL VOLTAGE LEVEL GND (With a Single Power Supply) +5V (Typ) (With Dual Power Supplies) 16, 17, 18 13 14 NC CLK/E CLK/NE I I PECL/ECL DGND3 EQUIVALENT CIRCUIT DESCRIPTION Digital Power Supply. Apply -5V for PECL and TTL input. No Connect pin. Not connected with the internal circuits. Clock Input. CLK/E Complementary Input. When left open, this pin goes to the threshold potential. Only CLK/E can be used for operation, but complementary input is recommended to attain fast and stable operation. Reset Input. When the input is set to low level, the built-in CLK frequency divider circuit can be reset. RESETN/E Complementary Input. When left open, this pin goes to the threshold voltage. Only RESETN/E can be used for operation. Clock input. Reset Input. When left open, this input goes to high level. When the input is set to low level, the built-in CLK frequency divider circuit can be reset. 1.5V 13 48 48 RESETN/E I 14 47 47 RESET/E I DVEE3 15 46 CLK/T RESETN/T I I TTL DVCC1 15 46 OR 44 , 45 DGND1 DVEE3 44 INV I TTL DVCC1 Data Output Polarity Inversion Input. When left open, this input goes to high level. (See Table 1; I/O Correspondence Table). 44 DGND1 DVEE3 45 SELECT VCC or Ground DVCC1 Data Output Mode Selection. (See Table 2; Operating Mode Table). 45 DGND1 DVEE3 7 HI3246 Pin Descriptions PIN NO 11 SYMBOL VRT I/O I (Continued) TYPICAL VOLTAGE LEVEL 4.0V (Typ) R1 11 EQUIVALENT CIRCUIT DESCRIPTION Top Reference Voltage. Bypass to AGND with a 1µF tantal capacitor and a 0.1µF chip capacitor. 9 7 4 2 VRM3 VRM2 VRM1 VRB I 3 VRB + -- (VRT - VRB) 4 2 VRB + -- (VRT - VRB) 4 1 VRB + -- (VRT - VRB) 4 9 R/2 R COMPARATOR 1 R COMPARATOR 63 R COMPARATOR 64 COMPARATOR 127 7 R COMPARATOR 128 COMPARATOR 191 4 R COMPARATOR 192 R COMPARATOR 255 R/2 2 R2 Reference Voltage Mid Point. Bypass to AGND with a 0.1µF chip capacitor. Reference Voltage Mid Point. Bypass to AGND with a 0.1µF chip capacitor. Reference Voltage Mid Point. Bypass to AGND with a 0.1µF chip capacitor. Bottom Reference Voltage. Bypass to AGND with a 1µF tantal capacitor and a 0.1µF chip capacitor. 2.0V (Typ) 6 VIN I VRT to VRB COMPARATOR AVCC AVCC Analog Input. 6 VREF AGND DVEE3 33 to 40 21 to 28 43 PBD0 to PBD7 PAD0 to PAD7 CLKOUT O O O TTL DVCC1 DVCC2 Port 1 Side Data Output. Port 2 Side Data Output. Clock Output. (See Table 2; Operating Mode Table). 21 TO 28 33 TO 40 43 DGND2 DGND1 DVEE3 8 HI3246 TABLE 1. A/D CODE INV 1 VIN VRT STEP 255 254 • • • VRM2 128 127 • • • 1 VRB 0 D7 D0 D7 0 D0 1111111100000000 1111111000000001 • • • • • • 1000000001111111 0111111110000000 • • • • • • 0000000111111110 0000000011111111 Notes on Operation • The HI3246 is a high-speed A/D converter which is capable of TTL, ECL and PECL level clock input. Characteristic impedance should be properly matched to ensure optimum performance during high-speed operation. • The power supply and grounding have a profound influence on converter performance. The power supply and grounding method are particularly important during highspeed operation. General points for caution are as follows: - The ground pattern should be as large as possible. It is recommended to make the power supply and ground patterns wider at an inner layer using a multi-layer board. - To prevent interference between AGND and DGND and between AVCC and DVCC , make sure the respective patterns are separated. To prevent a DC offset in the power supply pattern, connect the AVCC and DVCC lines at one point each, via a ferrite-bead filter. Shorting the AGND and DGND patterns in one place immediately under the A/D converter improves A/D converter performance. - Ground the power supply pins (AVCC , DVCC1 , DVCC2 , DVEE3) as close to each pin as possible with a 0.1µF or larger ceramic chip capacitor. (Connect the AVCC pin to the AGND pattern and the DVCC1 , DVCC2 , DVEE3 pins to the DGND pattern). - The digital output wiring should be as short as possible. If the digital output wiring is long, the wiring capacitance will increase, deteriorating the output slew rate and resulting in reflection to the output waveform since the original output slew rate is quite fast. • The analog input pin VIN has an input capacitance of approximately 21pF. To drive the A/D converter with proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance or parasitic inductance by using a large capacity drive circuit; keeping wiring as short as possible, and using chip parts for resistors and capacitors, etc. • The VRT and VRB pins must have adequate bypass to protect them from high-frequency noise. Bypass them to AGND with approximately 1µF tantal capacitor and, 0.1µF capacitor. At this time, approximately DGND3 - 1.2V voltage is generated. However, this is not recommended for use as threshold voltage VBB as it is too weak. When the digital input level is PECL level, ***/E pins should be used and ***/T pins left open. When the digital input level is TTL, ***/T pins should be used and III/E pins left open. Test Circuits +V 5V A ICC 4V VRT AVCC DVCC1 DVCC2 5V A IEE S2 + - S1 S1: ON WHEN A < B S2: ON WHEN A > B DGND3 -V CLK/E 5MHz PECL VIN 8 AB COMPARATOR HI3246 A8 TO A1 A0 B8 TO B1 B0 “1” CONTROLLER 000...00 TO 111..10 8 BUFFER 1.95V VIN 2V VRB DGND2 DGND1 AGND DVEE3 DVM “0” FIGURE 4. CURRENT CONSUMPTION MEASUREMENT CIRCUIT FIGURE 5. INTEGRAL LINEARITY ERROR/DIFFERENTIAL LINEARITY ERROR MEASUREMENT CIRCUIT 9 HI3246 Test Circuits SIGNAL SOURCE fC 4 -1kHz (Continued) A HI3246 VIN CLK CLK 8 LATCH B COMPARATOR A>B PULSE COUNTER + LATCH 2VP-P SINE WAVE SIGNAL SOURCE 1/ 16 LSB 8 fC FIGURE 6. ERROR RATE MEASUREMENT CIRCUIT VRT 100MHz VIN AMP OSC1 φ: VARIABLE CLK ∆υ fR VIN HI3246 CLK 1024 SAMPLES OSC2 PECL BUFFER 100MHz 8 ∆t LOGIC ANALYZER VIN 129 128 127 126 125 CLK SAMPLING TIMING FLUCTUATION (= APERTURE JITTER) VRM2 VRB σ (LSB) NOTE: Where σ (LSB) is the deviation of the output codes when the largest slew rate point is sampled at the clock which has exactly the same frequency as the analog input signal, the aperture jitter tAJ is: ∆υ 256 t AJ =  σ / ------  = σ /  --------- x 2 π f .  2  ∆t  FIGURE 8. APERTURE JITTER MEASUREMENT METHOD FIGURE 7. SAMPLING DELAY/APERTURE JITTER MEASUREMENT CIRCUIT Operating Modes The HI3246 has two types of operating modes which are selected with Pin 45 (SELECT). TABLE 2. OPERATING MODE OPERATING MODE DMUX Mode Straight Mode SELECT VCC GND MAXIMUM CONVERSION RATE 120MSPS 100MSPS DATA OUTPUT Demultiplexed Output 60 MBPS Straight Output 100 MBPS 60MHz. The input clock is inverted and output at 100MHz. CLOCK OUTPUT The input clock is 1/2 frequency divided and output at DMUX Mode (See Application Circuits, Figures 18, 19) Set the SELECT pin to VCC for this mode. In this mode, the clock frequency is divided by 2 in the IC, and the data is output after being demultiplexed by this 1/2 frequency divided clock. The 1/2 frequency divided clock, which has adequate setup time and hold time for the output data, is output from the CLKOUT pin. When using multiple HI3246 units in parallel in this mode, differences in the start timing of the 1/2 frequency divided clock may cause operation as shown in Figure 9. As a countermeasure, the HI3246 is equipped with a function which resets the 1/2 frequency divided clock. When resetting this clock, the RESET pulse must be input to the RESET pin. See the Timing Charts for the RESET pulse input timing. The A/D converter can operate at fC (Min) = 120MSPS in this mode. 10 Straight Mode (See Application Circuits, Figures 20, 21) Set the SELECT pin to GND for this mode. In this mode, data output can be obtained in accordance with the clock frequency applied to the A/D converter for applications which use the clock applied to the A/D converter as the system clock. The A/D converter can operate at fC (Min) = 100MSPS in this mode. Digital Input Level and Supply Voltage Settings The logic input level for the HI3246 supports PECL and TTL levels. The power supplies (DVEE3 , DGND3) for the logic input block must be set to match the logic input (CLK and RESET signals) level. HI3246 TABLE 3. LOGIC INPUT LEVEL AND POWER SUPPLY SETTINGS DIGITAL INPUT LEVEL PECL TTL DVEE3 0V 0V DGND3 +5V +5V SUPPLY VOLTAGE +5V +5V APPLICATION CIRCUITS Figures 18, 20 Figures 19, 21 CLK HI3246 CLK CLK A 8 BITS DATA CLKOUT RESETN HI3246 CLK B 8 BITS CLKOUT DATA RESETN FIGURE 9. WHEN THE RESET PULSE IS NOT USED CLK RESET PULSE HI3246 CLK CLK A 8 BITS DATA CLKOUT RESETN HI3246 CLK RESET PULSE B 8 BITS CLKOUT DATA RESETN FIGURE 10. WHEN THE RESET PULSE IS USED Typical Performance Curves 110 CURRENT CONSUMPTION (mA) CURRENT CONSUMPTION (mA) 110 105 105 100 100 95 95 f fIN = CLK -1kHz 4 DMUX MODE CL = 5pF 0 60 fC , CONVERSION RATE (MSPS) 120 90 -25 25 TA , AMBIENT TEMPERATURE (oC) 75 90 FIGURE 11. CURRENT CONSUMPTION vs AMBIENT TEMPERATURE CHARACTERISTICS FIGURE 12. CURRENT CONSUMPTION vs CONVERSION RATE CHARACTERISTICS RESPONSE 11 HI3246 Typical Performance Curves VRT = 4V VRB = 2V 100 (Continued) 4 REFERENCE CURRENT (mA) ANALOG INPUT CURRENT (µA) 3 50 2 0 2 3 ANALOG INPUT VOLTAGE (V) 4 -25 25 TA , AMBIENT TEMPERATURE (oC) 75 FIGURE 13. ANALOG INPUT CURRENT vs ANALOG INPUT VOLTAGE CHARACTERISTICS FIGURE 14. REFERENCE CURRENT vs AMBIENT TEMPERATURE CHARACTERISTICS 50 fC = 120MSPS 10-6 fIN = -1kHz 4 ERROR > 16 LSB fCLK ERROR RATE (TPS) 40 SNR (dB) 10-7 10-8 30 10-9 20 1 3 5 10 30 50 10-10 120 140 fC , CONVERSION RATE (MSPS) 160 INPUT FREQUENCY (MHz) FIGURE 15. SNR vs INPUT FREQUENCY RESPONSE FIGURE 16. ERROR RATE vs CONVERSION RATE CHARACTERISTICS fC , MAXIMUM CONVERSION (MSPS) 170 fIN = -1kHz 4 ERROR > 16 LSB ERROR RATE: 10-9 TPS fCLK 160 150 140 130 -25 25 TA , AMBIENT TEMPERATURE (Co) 75 FIGURE 17. MAXIMUM CONVERSION RATE vs AMBIENT TEMPERATURE CHARACTERISTICS 12 HI3246 Application Circuits +5V (D) DG PECL RESET PULSE 48 47 46 45 44 43 42 41 40 39 38 37 1 2 2V 3 4 +5V (A) AG +5V (A) 5 6 7 8 9 AG AG +5V (D) 4V 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PECL - CLK DG +5V (D) 36 P1D0 TO P1D7 35 8-BIT DIGITAL DATA 34 33 32 31 30 29 28 27 26 P2D0 TO P2D7 8-BIT DIGITAL DATA 25 LATCH 8-BIT DIGITAL DATA DG +5V (D) DG LATCH DG DG AG 8-BIT DIGITAL DATA FIGURE 18. DMUX PECL INPUT +5V (D) DG TTL RESET PULSE 48 47 46 45 44 43 42 41 40 39 38 37 1 2 2V 3 4 +5V (A) AG 5 6 7 +5V (A) AG AG +5V (D) 4V 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 P1D0 TO P1D7 35 8-BIT DIGITAL DATA 34 33 32 31 30 29 28 27 26 P2D0 TO P2D7 8-BIT DIGITAL DATA 25 LATCH 8-BIT DIGITAL DATA DG +5V (D) DG LATCH DG AG AG 8-BIT DIGITAL DATA TTL - CLK DG +5V (D) FIGURE 19. DMUX TTL INPUT 13 HI3246 Application Circuits (Continued) DG +5V (D) DG 48 47 46 45 44 43 42 41 40 39 38 37 DG AG AG +5V (A) AG +5V (A) AG AG +5V(D) 4V 2V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PECL - CLK PECL - TTL DG +5V (D) 36 P1D0 TO P1D7 35 8-BIT DIGITAL DATA 34 33 32 31 30 29 28 27 26 25 +5V (D) DG DG LATCH 8-BIT DIGITAL DATA FIGURE 20. STRAIGHT PECL INPUT DG +5V (D) DG 48 47 46 45 44 43 42 41 40 39 38 37 DG AG AG +5V (A) AG +5V (A) 2V 1 2 3 4 5 6 7 8 9 AG AG +5V(D) 4V 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TTL - CLK 36 P1D0 TO P1D7 35 8-BIT DIGITAL DATA 34 33 32 31 30 29 28 27 26 25 DG DG +5V (D) LATCH 8-BIT DIGITAL DATA DG +5V (D) FIGURE 21. STRAIGHT TTL INPUT 14 HI3246 Application Circuits (Continued) AG ANALOG INPUT 4V +5V (D) DG AG + AG - 1µF + AG +5V (A) + + 2V 1µF + AG - + 10µF SHORT SHORT + 10µF 12 DGND3 11 VRT 10 AGND 9 VRM3 8 AVCC 7 VRM2 6 VIN 5 AVCC 4 VRM1 3 AGND 2 VRB 1 DVEE3 RESETN/E 48 RESET/E 47 RESETN/T 46 SELECT 45 INV 44 CLKOUT 43 DVCC2 42 DGND2 41 P1D7 40 P1D6 39 P1D5 38 P1D4 37 36 P1D3 P1D3 13 14 TTL CLK 15 16 17 18 19 20 21 22 23 24 CLK/E CLKN/E CLK/T NC NC NC DVCC2 DGND2 P2D0 P2D1 P2D2 DGND1 DGND2 DVCC1 DVCC2 P2D3 P2D4 P2D5 P2D6 P2D7 P1D0 P1D1 34 P1D1 25 26 27 28 29 30 31 32 33 35 P1D2 P1D2 P1D4 P1D5 SHORT THE ANALOG SYSTEM AND DIGITAL SYSTEM AT ONE POINT IMMEDIATELY UNDER THE A/D CONVERTER. SEE THE NOTES ON OPERATION IS THE CHIP CAPACITOR OF 0.1µF. FIGURE 22. STRAIGHT MODE TTL I/O (WHEN A SINGLE POWER SUPPLY IS USED) 15 (MSB) P2D7 P1D6 (MSB) P1D7 (LSB) P2D0 P2D1 P2D2 P2D3 P2D4 P2D5 P2D6 (LSB) P1D0 HI3246 Metric Plastic Quad Flatpack Packages (MQFP/PQFP) D D1 Q48.12x12-S 48 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE INCHES SYMBOL A A1 B D MIN 0.081 0.000 0.008 0.587 0.469 0.587 0.469 0.028 48 0.032 BSC MAX 0.100 0.011 0.017 0.618 0.488 0.618 0.488 0.043 MILLIMETERS MIN 2.05 0.00 0.20 14.90 11.90 14.90 11.90 0.70 48 0.80 BSC MAX 2.55 0.30 0.45 15.70 12.40 15.70 12.40 1.10 NOTES 5 2 3, 4 2 3, 4 6 Rev. 0 2/96 E E1 D1 E E1 L N e PIN 1 SEATING PLANE e NOTES: -H- A 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. Dimensions D and E to be determined at seating plane -C- . 3. Dimensions D1 and E1 to be determined at datum plane -H- . 4. Dimensions D1 and E1 do not include mold protrusion. 5. Dimension B does not include dambar protrusion. 6. “N” is the number of terminal positions. 0.15 0.006 0.24 M B 0o-10o A1 -C- L 0.10/0.25 0.004/0.010 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 16