HI5628

® HI5628 Data Sheet September 2000 FN4520.5 8-Bit, 125/60MSPS, Dual High Speed CMOS D/A Converter The HI5628 is an 8-bit, dual 125MSPS D/A converter which is implemented in an advanced CMOS process. Operating from a single +5V to +3V supply, the converter provides 20.48mA of full scale output current and includes an input data register. Low glitch energy and excellent frequency domain performance are achieved using a segmented architecture. The single DAC version is the HI5660 while 10-bit versions exist in the HI5760 and HI5728. Features • Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . 125MSPS • Low Power . . . . . . . . . . . . . 330mW at 5V, 170mW at 3V • Integral Linearity Error . . . . . . . . . . . . . . . . . . . ±0.25 LSB • Differential Linearity . . . . . . . . . . . . . . . . . . . . . ±0.25 LSB • Channel Isolation (Typ) . . . . . . . . . . . . . . . . . . . . . . 80dB • SFDR to Nyquist at 10MHz Output . . . . . . . . . . . . 60dBc • Internal 1.2V Bandgap Voltage Reference • Single Power Supply from +5V to +3V Ordering Information PART NUMBER HI5628IN HI5628/6IN HI5628EVAL1 TEMP. RANGE (oC) MAX CLOCK SPEED • CMOS Compatible Inputs • Excellent Spurious Free Dynamic Range PACKAGE PKG. NO. -40 to 85 48 Ld LQFP -40 to 85 48 Ld LQFP 25 Q48.7x7A 125MHz Q48.7x7A 60MHz 125MHz Applications • Direct Digital Frequency Synthesis • Wireless Communications • Signal Reconstruction • Arbitrary Waveform Generators • Test Equipment • High Resolution Imaging Systems Evaluation Platform Pinout HI5628 (LQFP) TOP VIEW QD7 (MSB) QD6 ID7 (MSB) QCLK DGND DVDD DGND ICLK DVDD ID4 ID3 ID2 ID1 ID0 (LSB) DGND DGND SLEEP DVDD DGND NC AVDD 48 47 46 45 44 43 42 41 40 39 38 37 36 35 2 34 3 33 4 32 5 31 6 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 1 QD5 ID5 ID6 QD4 QD3 QD2 QD1 QD0 (LSB) DGND DGND DVDD DGND NC AVDD AGND REFLO AGND QOUTB QOUTA FSADJ 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. QCOMP1 ICOMP1 IOUTB REFIO IOUTA AGND AGND HI5628 Typical Applications Circuit ICLK/QCLK 50Ω DVDD 0.1µF DVDD 0.1µF ANALOG GROUND PLANE DIGITAL GROUND PLANE ID4 ID3 ID2 ID1 ID0 (LSB) SLEEP AGND DVDD 0.1µF AVDD 0.1µF 48 47 46 45 44 43 42 41 40 39 38 37 36 1 35 2 34 3 33 4 32 5 DGND 31 6 DGND DGND 30 7 DGND DVDD 29 8 DGND 28 9 DVDD 27 NC (GND) 10 DGND AVDD 26 11 NC (GROUND) 25 12 13 14 15 16 17 18 19 20 21 22 23 24 AGND QD7 (MSB) QD6 QD5 ID5 ID6 ID7 (MSB) QD4 QD3 QD2 QD1 QD0 (LSB) DVDD PLANE 0.1µF AVDD 0.1µF AGND QCOMP1 REFIO RSET 1.91kΩ 0.1µF 0.1µF AVDD ICOMP1 AVDD 0.1µF 50Ω 50Ω 50Ω 50Ω NOTE: ICOMP1 AND QCOMP1 PINS (24, 14) MUST BE TIED TOGETHER EXTERNALLY IOUTA IOUTB QOUTB QOUTA +5V TO +3V POWER SUPPLY FERRITE BEAD 10µH 10µF 0.1µF DV DD (POWER PLANE) AVDD (POWER PLANE) FERRITE BEAD 10µH 0.1µF +5V TO +3V (SUPPLY) + 10µF NOTE: Recommended separate analog and digital ground planes, connected at a single point near the device. See AN9827. 2 HI5628 Functional Block Diagram IOUTA IOUTB (LSB) ID0 ID1 ID2 ID3 ID4 ID5 ID6 (MSB) ID7 LATCH UPPER 5-BIT DECODER 31 LATCH 34 34 CASCODE CURRENT SOURCE SWITCH MATRIX 3 LSBs + 31 MSB SEGMENTS ICLK ICOMP1 INT/EXT VOLTAGE REFERENCE INT/EXT REFERENCE SELECT BIAS GENERATION REFLO REFIO FSADJ SLEEP QCOMP1 (LSB) QD0 QD1 QD2 QD3 QD4 QD5 QD6 (MSB) QD7 LATCH UPPER 5-BIT DECODER 31 LATCH 34 SWITCH MATRIX 34 CASCODE CURRENT SOURCE 3 LSBs + 31 MSB SEGMENTS QCLK AVDD AGND DVDD DGND QOUTA QOUTB 3 HI5628 Absolute Maximum Ratings Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . . +5.5V Analog Supply Voltage AVDD to ACOM . . . . . . . . . . . . . . . . . . +5.5V Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V Digital Input Voltages (D7-D0, CLK, SLEEP). . . . . . . . DVDD + 0.3V Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . . ±50µA Reference Input Voltage Range . . . . . . . . . . . . . . . . . . AVDD + 0.3V Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA Thermal Information Thermal Resistance (Typical, Note 1) θJA(oC/W) LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications AVDD = +5V, DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values. Data given is per channel except for ‘Power Supply Characteristics.’ HI5628IN TA = -40oC TO 85oC PARAMETER SYSTEM PERFORMANCE (Per Channel) Resolution Integral Linearity Error, INL Differential Linearity Error, DNL Offset Error, IOS Offset Drift Coefficient Full Scale Gain Error, FSE TEST CONDITIONS MIN TYP MAX UNITS 8 “Best Fit” Straight Line (Note 7) (Note 7) (Note 7) (Note 7) With External Reference (Notes 2, 7) With Internal Reference (Notes 2, 7) -0.5 -0.5 -0.025 ±0.25 ±0.25 0.1 ±2 ±1 ±50 ±100 0.1 80 - +0.5 +0.5 +0.025 Bits LSB LSB % FSR ppm FSR/oC -10 -10 -0.5 +10 +10 0.5 1.25 20 % FSR % FSR ppm FSR/oC ppm FSR/oC Full Scale Gain Drifta With External Reference (Note 7) With Internal Reference (Note 7) Gain Matching Between Channels I/Q Channel Isolation Output Voltage Compliance Range Full Scale Output Current, IFS DYNAMIC CHARACTERISTICS (Per Channel) Clock Rate, fCLK Output Settling Time, (tSETT) Singlet Glitch Area (Peak Glitch) Output Rise Time Output Fall Time Output Capacitance Output Noise IOUTFS = 20mA IOUTFS = 2mA (Note 3, 9) 0.8% (±1 LSB, equivalent to 7 Bits) (Note 7) 0.4% (±1/2 LSB, equivalent to 8 Bits) (Note 7) RL = 25Ω (Note 7) Full Scale Step Full Scale Step FOUT = 10MHz (Note 3) dB dB V mA -0.3 2 125 - 5 15 5 1.5 1.5 10 50 30 - MHz ns ns pV•s ns ns pF pA/ √Hz pA/ √Hz 4 HI5628 Electrical Specifications AVDD = +5V, DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values. Data given is per channel except for ‘Power Supply Characteristics.’ (Continued) HI5628IN TA = -40oC TO 85oC PARAMETER AC CHARACTERISTICS - HI5628IN - 125MHz (Per Channel) Spurious Free Dynamic Range, SFDR Within a Window fCLK = 125MSPS, fOUT = 32.9MHz, 10MHz Span (Notes 4, 7) fCLK = 100MSPS, fOUT = 5.04MHz, 4MHz Span (Notes 4, 7) fCLK = 125MSPS, fOUT = 32.9MHz, 62.5MHz Span (Notes 4, 7) fCLK = 125MSPS, fOUT = 10.1MHz, 62.5MHz Span (Notes 4, 7) fCLK = 100MSPS, fOUT = 40.4MHz, 50MHz Span (Notes 4, 7) fCLK = 100MSPS, fOUT = 20.2MHz, 50MHz Span (Notes 4, 7) fCLK = 100MSPS, fOUT = 5.04MHz, 50MHz Span (Notes 4, 7) fCLK = 100MSPS, fOUT = 2.51MHz, 50MHz Span (Notes 4, 7) AC CHARACTERISTICS - HI5628/6IN - 60MHz (Per Channel) Spurious Free Dynamic Range, SFDR Within a Window fCLK = 60MSPS, fOUT = 10.1MHz, 10MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 5.02MHz, 2MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 1.00MHz, 2MHz Span (Notes 4, 7) Total Harmonic Distortion (THD) to Nyquist fCLK = 50MSPS, fOUT = 2.00MHz (Notes 4, 7) fCLK = 50MSPS, fOUT = 1.00MHz (Notes 4, 7) Spurious Free Dynamic Range, SFDR to Nyquist fCLK = 60MSPS, fOUT = 20.2MHz, 30MHz Span (Notes 4, 7) fCLK = 60MSPS, fOUT = 10.1MHz, 30MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 20.2MHz, 25MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 5.02MHz, 25MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 2.51MHz, 25MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 1.00MHz, 25MHz Span (Notes 4, 7) fCLK = 25MSPS, fOUT = 5.02MHz, 25MHz Span (Notes 4, 7) VOLTAGE REFERENCE Internal Reference Voltage, VFSADJ Internal Reference Voltage Drift Internal Reference Output Current Sink/Source Capability Reference Input Impedance Reference Input Multiplying Bandwidth DIGITAL INPUTS (Note 7) Voltage at Pin 22 with Internal Reference 1.04 1.16 ±60 0.1 1 1.4 1.28 V ppm/oC TEST CONDITIONS MIN TYP MAX UNITS - 70 73 67 51 61 48 56 68 68 - dBc dBc dBc dBc dBc dBc dBc dBc dBc Total Harmonic Distortion (THD) to Nyquist fCLK = 100MSPS, fOUT = 2.00MHz (Notes 4, 7) Spurious Free Dynamic Range, SFDR to Nyquist - 70 73 74 67 68 54 60 53 67 68 68 71 - dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc µA MΩ MHz D7-D0, CLK (Per Channel) (Note 3) (Note 3) (Note 3) (Note 3) 3.5 2.1 -10 -10 5 3 0 0 5 1.3 0.9 +10 +10 V V V V µA µA pF Input Logic High Voltage with 5V Supply, VIH Input Logic High Voltage with 3V Supply, VIH Input Logic Low Voltage with 5V Supply, VIL Input Logic Low Voltage with 3V Supply, VIL Input Logic Current, IIH Input Logic Current, IIL Digital Input Capacitance, CIN TIMING CHARACTERISTICS (Per Channel) 5 HI5628 Electrical Specifications AVDD = +5V, DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values. Data given is per channel except for ‘Power Supply Characteristics.’ (Continued) HI5628IN TA = -40oC TO 85oC PARAMETER Data Setup Time, tSU Data Hold Time, tHLD Propagation Delay Time, tPD CLK Pulse Width, tPW1 , tPW2 POWER SUPPLY CHARACTERISTICS AVDD Power Supply DVDD Power Supply Analog Supply Current (IAVDD) Digital Supply Current (IDVDD) Supply Current (IAVDD) Sleep Mode Power Dissipation (Both Channels) (Note 8, 9) (Note 8, 9) 5V or 3V, IOUTFS = 20mA 5V or 3V, IOUTFS = 2mA 5V, IOUTFS = Don’t Care (Note 5) 3V, IOUTFS = Don’t Care (Note 5) 5V or 3V, IOUTFS = Don’t Care) 5V, IOUTFS = 20mA (Note 6) 5V, IOUTFS = 2mA (Notes 6) 3V, IOUTFS = 20mA (Note 6) 3V, IOUTFS = 2mA (Note 6) 5V, IOUTFS = 20mA (Note 10) 3.3V, IOUTFS = 20mA (Note 10) 3V, IOUTFS = 20mA (Note 10) Power Supply Rejection NOTES: 2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625µA). Ideally the ratio should be 32. 3. Parameter guaranteed by design or characterization and not production tested. 4. Spectral measurements made with differential transformer coupled output and no filtering. 5. Measured with the clock at 50MSPS and the output frequency at 1MHz, both channels. 6. Measured with the clock at 100MSPS and the output frequency at 40MHz, both channels. 7. See ‘Definition of Specifications’. 8. For operation below 3V, it is recommended that the output current be reduced to 12mA or less to maintain optimum performance. DVDD and AVDD do not have to be equal. 9. For operation above 125MHz, it is recommended that the power supply be 3.3V or greater. The part is functional with the clock above 125MSPS and the power supply below 3.3V, but performance is degraded. 10. Measured with the clock at 60MSPS and the output frequency at 10MHz, both channels. Single Supply (Note 7) 2.7 2.7 -0.2 5.0 5.0 46 8 6 3 3.2 330 140 170 54 300 150 135 5.5 5.5 60 10 6 +0.2 V V mA mA mA mA mA mW mW mW mW mW mW mW % FSR/V See Figure 3 (Note 3) See Figure 3 (Note 3) See Figure 3 See Figure 3 (Note 3) TEST CONDITIONS MIN 3 3 4 TYP 1 MAX UNITS ns ns ns ns 6 HI5628 Timing Diagrams CLK 50% D7-D0 1/ LSB ERROR BAND 2 V GLITCH AREA = 1/2 (H x W) IOUT HEIGHT (H) tSETT tPD WIDTH (W) t(ps) FIGURE 1. OUTPUT SETTLING TIME DIAGRAM FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT METHOD tPW1 tPW2 CLK tSU tHLD D7-D0 tSU tHLD tSU tHLD 50% tPD tSETT IOUT tPD tSETT tPD tSETT FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM 7 HI5628 Definition of Specifications Integral Linearity Error, INL, is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve. Differential Linearity Error, DNL, is the measure of the step size output deviation from code to code. Ideally the step size should be 1 LSB. A DNL specification of 1 LSB or less guarantees monotonicity. Output Settling Time, is the time required for the output voltage to settle to within a specified error band measured from the beginning of the output transition. The measurement was done by switching from code 0 to 64, or quarter scale. Termination impedance was 25Ω due to the parallel resistance of the output 50Ω and the oscilloscope’s 50Ω input. This also aids the ability to resolve the specified error band without overdriving the oscilloscope. Singlet Glitch Area, is the switching transient appearing on the output during a code transition. It is measured as the area under the overshoot portion of the curve and is expressed as a Volt-Time specification. Full Scale Gain Error , is the error from an ideal ratio of 32 between the output current and the full scale adjust current (through RSET). Full Scale Gain Drift, is measured by setting the data inputs to all ones and measuring the output voltage through a known resistance as the temperature is varied from TMIN to TMAX . It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm of FSR (Full Scale Range) per degree C. Total Harmonic Distortion, THD, is the ratio of the DAC output fundamental to the RMS sum of the first five harmonics. Spurious Free Dynamic Range, SFDR, is the amplitude difference from the fundamental to the largest harmonically or non-harmonically related spur within the specified window. Output Voltage Compliance Range, is the voltage limit imposed on the output. The output impedance load should be chosen such that the voltage developed does not violate the compliance range. Offset Error, is measured by setting the data inputs to all zeros and measuring the output voltage through a known resistance. Offset error is defined as the maximum deviation of the output current from a value of 0mA. Offset Drift, is measured by setting the data inputs to all zeros and measuring the output voltage through a known resistance as the temperature is varied from TMIN to TMAX . It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm of FSR (Full Scale Range) per degree C. Power Supply Rejection, is measured using a single power supply. Its nominal +5V is varied ±10% and the change in the DAC full scale output is noted. Reference Input Multiplying Bandwidth, is defined as the 3dB bandwidth of the voltage reference input. It is measured by using a sinusoidal waveform as the external reference with the digital inputs set to all 1s. The frequency is increased until the amplitude of the output waveform is 0.707 of its original value. Internal Reference Voltage Drift, is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm per degree C. Detailed Description The HI5628 is a dual, 8-bit, current out, CMOS, digital to analog converter. Its maximum update rate is 125MSPS and can be powered by either single or dual power supplies in the recommended range of +3V to +5V. It consumes less than 330mW of power when using a +5V supply with the data switching at 100MSPS. The architecture is based on a segmented current source arrangement that reduces glitch by reducing the amount of current switching at any one time. The five MSBs are represented by 31 major current sources of equivalent current. The three LSBs are comprised of binary weighted current sources. Consider an input pattern to the converter which ramps through all the codes from 0 to 255. The three LSB current sources would begin to count up. When they reached the all high state (decimal value of 7) and needed to count to the next code, they would all turn off and the first major current source would turn on. To continue counting upward, the 3 LSBs would count up another 7 codes, and then the next major current source would turn on and the three LSBs would all turn off. The process of the single, equivalent, major current source turning on and the three LSBs turning off each time the converter reaches another 7 codes greatly reduces the glitch at any one switching point. In previous architectures that contained all binary weighted current sources or a binary weighted resistor ladder, the converter might have a substantially larger amount of current turning on and off at certain, worstcase transition points such as midscale and quarter scale transitions. By greatly reducing the amount of current switching at certain ‘major’ transitions, the overall glitch of the converter is dramatically reduced, improving settling times and transient problems. 8 HI5628 Digital Inputs and Termination The HI5628 digital inputs are guaranteed to CMOS levels. However, TTL compatibility can be achieved by lowering the supply voltage to 3V due to the digital threshold of the input buffer being approximately half of the supply voltage. The internal register is updated on the rising edge of the clock. To minimize reflections, proper termination should be implemented. If the lines driving the clock and the digital inputs are 50Ω lines, then 50Ω termination resistors should be placed as close to the converter inputs as possible, connected to the digital ground plane (if separate grounds are used). TABLE 1. INPUT CODING vs OUTPUT CURRENT INPUT CODE (D7-D0) 1111 1111 1000 0000 0000 0000 IOUTA (mA) 20 10 0 IOUTB (mA) 0 10 20 Outputs IOUTA and IOUTB (or QOUTA and QOUTB) are complementary current outputs. The sum of the two currents is always equal to the full scale output current minus one LSB. If single ended use is desired, a load resistor can be used to convert the output current to a voltage. It is recommended that the unused output be either grounded or equally terminated. The voltage developed at the output must not violate the output voltage compliance range of -0.3V to 1.25V. RLOAD should be chosen so that the desired output voltage is produced in conjunction with the output full scale current, which is described above in the ‘Reference’ section. If a known line impedance is to be driven, then the output load resistor should be chosen to match this impedance. The output voltage equation is: VOUT = IOUT X RLOAD . These outputs can be used in a differential-to-single-ended arrangement to achieve better harmonic rejection. The SFDR measurements in this data sheet were performed with a 1:1 transformer on the output of the DAC (see Figure 1). With the center tap grounded, the output swing of pins 16 and 17 will be biased at zero volts. It is important to note here that the negative voltage output compliance range limit is -300mV, imposing a maximum of 600mVP-P amplitude with this configuration. The loading as shown in Figure 1 will result in a 500mV signal at the output of the transformer if the full scale output current of the DAC is set to 20mA. Ground Plane(s) If separate digital and analog ground planes are used, then all of the digital functions of the device and their corresponding components should be over the digital ground plane and terminated to the digital ground plane. The same is true for the analog components and the analog ground plane. The converter will function properly with a single ground plane, as the Evaluation Board is configured in this matter. Noise Reduction To minimize power supply noise, 0.1µF capacitors should be placed as close as possible to the converter’s power supply pins, AVDD and DVDD . Also, should the layout be designed using separate digital and analog ground planes, these capacitors should be terminated to the digital ground for DVDD and to the analog ground for AVDD . Additional filtering of the power supplies on the board is recommended. Voltage Reference The internal voltage reference of the device has a nominal value of +1.2V with a ± 60 ppm / oC drift coefficient over the full temperature range of the converter. It is recommended that a 0.1µF capacitor be placed as close as possible to the REFIO pin, connected to the analog ground. The REFLO pin (15) selects the reference. The internal reference can be selected if pin 15 is tied low (ground). If an external reference is desired, then pin 15 should be tied high (to the analog supply voltage) and the external reference driven into REFIO, pin 23. The full scale output current of the converter is a function of the voltage reference used and the value of RSET. IOUT should be within the 2mA to 20mA range, through operation below 2mA is possible, with performance degradation. If the internal reference is used, VFSADJ will equal approximately 1.16V (pin 22). If an external reference is used, VFSADJ will equal the external reference. The calculation for IOUT (Full Scale) is: IOUT (Full Scale) = (VFSADJ/RSET) x 32. If the full scale output current is set to 20mA by using the internal voltage reference (1.16V) and a 1.86kΩ RSET resistor, then the input coding to output current will resemble the following: 50Ω PIN 17 (20) PIN 16 (21) IOUTB (QOUTB) 100Ω IOUTA (QOUTA) 50Ω VOUT = (2 x IOUT x REQ)V 50Ω FIGURE 4. VOUT = 2 x IOUT x REQ ,where REQ is ~12.5Ω. Allowing the center tap to float will result in identical transformer output, however the output pins of the DAC will have positive DC offset. The 50Ω load on the output of the transformer represents the spectrum analyzer’s input impedance. 9 HI5628 Pin Descriptions PIN NO. 39-32 1-5, 48-46 8 15 23 22 14, 24 13, 18, 19, 25 17 16 20 21 11, 27 12, 26 6, 7, 10, 28, 30, 31, 41, 44 9, 29, 40, 45 43 42 PIN NAME PIN DESCRIPTION QD7 (MSB) Through Digital Data Bit 7, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the Q QD0 (LSB) channel. ID7 (MSB) Through ID0 (LSB) SLEEP REFLO REFIO FSADJ ICOMP1, QCOMP1 AGND IOUTB IOUTA QOUTB QOUTA NC AVDD DGND DVDD ICLK QCLK Digital Data Bit 7, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the I channel. Control Pin for Power-Down Mode. Sleep Mode is active high; connect to ground for Normal Mode. Sleep pin has internal 20µA active pulldown current. Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable. Reference voltage input if internal reference is disabled and reference voltage output if internal reference is enabled. Use 0.1µF cap to ground when internal reference is enabled. Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output Current Per Channel = 32 x IFSADJ . Reduces noise. Connect each to AVDD with 0.1µF capacitor. The ICOMP1 and QCOMP1 pins MUST be tied together externally. Analog Ground Connections. The complementary current output of the I channel. Bits set to all 0s gives full scale current. Current output of the I channel. Bits set to all 1s gives full scale current. The complementary current output of the Q channel. Bits set to all 0s gives full scale current. Current output of the Q channel. Bits set to all 1s gives full scale current. No Connect. Recommended: Connect to ground. Analog Supply (+2.7V to +5.5V). Digital Ground. Supply voltage for digital circuitry (+2.7V to +5.5V). Clock input for I channel. Positive edge of clock latches data. Clock input for Q channel. Positive edge of clock latches data. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 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