HI5703EVAL

DS MMEN RECO RSIL , INTE 6KCB SIGNS B OR HI574 DE Sheet Data November 1998 C EW FOR N HE HI5767/4 T TM HI5703 File Number 3950.7 10-Bit, 40 MSPS A/D Converter [ /Title converter fabricated in Intersil’s BiCMOS process. It is (HI5703 designed for high speed applications where wide bandwidth and low power consumption are essential. Its 40 MSPS ) speed is made possible by a fully differential pipeline /Subarchitecture with an internal sample and hold. ject (10Bit, 40 The HI5703 has excellent dynamic performance while MSPS consuming only 400mW power at 40 MSPS. Data output latches are provided which present valid data to the output A/D bus with a latency of 7 clock cycles. It is pin-to-pin Concompatible with the HI5702. verter) For lower power consumption or internal reference, please /Author refer to the HI5746 or HI5767. () /KeyOrdering Information words (Intersil TEMP. PKG. PART NUMBER RANGE (oC) PACKAGE NO. Semi0 to 70 28 Ld SOIC (W) M28.3 conduc- HI5703KCB tor, HI5703EVAL 25 Evaluation Board A/D, Pinout Analog HI5703 to Digi(SOIC) tal ConTOP VIEW verter, 28 D0 DVCC1 1 Narrow 27 D1 DGND 2 Band, 26 D2 DVCC1 3 Com25 D3 4 DGND munica24 D4 5 AVCC tions, 23 DVCC2 AGND 6 High 22 CLK VREF + 7 Speed 21 DGND VREF - 8 Convert20 D5 VIN+ 9 19 D6 ers, VIN- 10 18 D7 11 VDC High 17 D8 12 AGND Resolu16 D9 AVCC 13 tion 15 DFS OE 14 Converters, Basestation, The HI5703 is a monolithic, 10-bit, analog-to-digital Features • Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 40 MSPS • 8.55 Bits Guaranteed at fIN = 10MHz • Low Power • Wide Full Power Input Bandwidth. . . . . . . . . . . . . 250MHz • On Chip Sample and Hold • Fully Differential or Single-Ended Analog Input • Single Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . +5V • TTL Compatible Interface • 3.3V Digital Outputs Available Applications • Professional Video Digitizing • Medical Imaging • Digital Communication Systems • High Speed Data Acquisition • Additional Reference Documents - AN9534 Using the HI5703 Evaluation Board - AN9413 Driving the Analog Input of the HI5702 - AN9214 Using Intersil High Speed A/D Converters 4-1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-7143 | Copyright © Intersil Corporation 1998 Typical Application Schematic HI5703 3.25V 2.0V VREF+ (7) VREF - (8) (LSB) (28) D0 (27) D1 AGND (12) AGND (6) DGND (2) DGND (21) DGND (4) (26) D2 (25) D3 (24) D4 (20) D5 (19) D6 (18) D7 (17) D8 (MSB) (16) D9 VIN + VIN + (9) VDC (11) VIN VIN - (10) (1) DVCC1 (3) DVCC1 (23) DVCC2 0.1µF CLOCK CLK (22) DFS (15) OE (14) (13) AVCC (5) AVCC 0.1µF + 10µF +5V D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 10µF AND 0.1µF CAPS ARE PLACED AS CLOSE TO PART AS POSSIBLE + 10µF +5V DGND AGND BNC 4-2 Functional Block Diagram VDC VINVIN+ S/H BIAS CLOCK CLK STAGE 1 DFS 2-BIT FLASH 2-BIT DAC OE + ∑ - X2 D9 (MSB) D8 D7 D6 STAGE 9 DIGITAL DELAY AND DIGITAL ERROR CORRECTION D5 D4 D3 2-BIT FLASH 2-BIT DAC D2 D1 + D0 (LSB) ∑ - X2 STAGE 10 1-BIT FLASH AVCC AGND DVCC1 DVCC2 DGND VREF + VREF - 4-3 Absolute Maximum Ratings TA = 25oC Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . +6V DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVCC Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC Operating Conditions Temperature Range, HI5703KCB . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER ACCURACY Resolution Integral Linearity Error, INL Differential Linearity Error, DNL (Guaranteed No Missing Codes) Offset Error, VOS Full Scale Error, FSE DYNAMIC CHARACTERISTICS Minimum Conversion Rate Maximum Conversion Rate Effective Number of Bits, ENOB AVCC = DVCC1 = DVCC2 = +5.0V; VREF+ = 3.25V; VREF - = 2.0V; fS = 36 MSPS at 50% Duty Cycle; CL = 20pF; TA = 25oC; Differential Analog Input; Unless Otherwise Specified TEST CONDITION MIN TYP MAX UNITS 10 fIN = DC fIN = DC fIN = DC fIN = DC - ±1 ±0.5 4 1 ±2.0 ±1 - Bits LSB LSB LSB LSB No Missing Codes No Missing Codes fIN = 1MHz fIN = 5MHz fIN = 10MHz 40 8.55 53.2 53.2 - 0.5 9.2 9.2 8.9 57 57 55 58 58 57 -64 -63 -60 -75 -75 -73 -66 -64 -63 1 - MSPS MSPS Bits Bits Bits dB dB dB dB dB dB dBc dBc dBc dBc dBc dBc dBc dBc dBc Signal to Noise and Distortion Ratio, SINAD RMS Signal = ------------------------------------------------------------RMS Noise + Distortion Signal to Noise Ratio, SNR RMS Signal = -------------------------------RMS Noise Total Harmonic Distortion, THD fIN = 1MHz fIN = 5MHz fIN = 10MHz fIN = 1MHz fIN = 5MHz fIN = 10MHz fIN = 1MHz fIN = 5MHz fIN = 10MHz 2nd Harmonic Distortion fIN = 1MHz fIN = 5MHz fIN = 10MHz 3rd Harmonic Distortion fIN = 1MHz fIN = 5MHz fIN = 10MHz 4-4 Electrical Specifications PARAMETER AVCC = DVCC1 = DVCC2 = +5.0V; VREF+ = 3.25V; VREF - = 2.0V; fS = 36 MSPS at 50% Duty Cycle; CL = 20pF; TA = 25oC; Differential Analog Input; Unless Otherwise Specified (Continued) TEST CONDITION fIN = 1MHz fIN = 5MHz fIN = 10MHz MIN 54 0.2V Overdrive TYP 66 64 63 -59 0.5 0.1 1 1 MAX UNITS dBc dBc dBc dBc % Degree Cycle Cycle Spurious Free Dynamic Range, SFDR Intermodulation Distortion, IMD Differential Gain Error Differential Phase Error Transient Response Over-Voltage Recovery ANALOG INPUT Maximum Peak-to-Peak Differential Analog Input Range (VIN+ - VIN-) Maximum Peak-to-Peak Single-Ended Analog Input Range Analog Input Resistance, RIN Analog Input Capacitance, CIN Analog Input Bias Current, IB+ or IBDifferential Analog Input Bias Current IB DIFF = (IB+ - IB-) Analog Input Common Mode Voltage Range (VIN+ + VIN-) / 2 Full Power Input Bandwidth (FPBW) REFERENCE INPUT Total Reference Resistance, RL Reference Current Positive Reference Voltage Input, VREF+ Negative Reference Voltage Input, VREF Reference Common Mode Voltage (VREF+ + VREF -) / 2 DC BIAS VOLTAGE DC Bias Voltage Output, VDC Max Output Current DIGITAL INPUTS Input Logic High Voltage, VIH Input Logic Low Voltage, VIL Input Logic High Current, IIH Input Logic Low Current, IIL Input Capacitance, CIN DIGITAL OUTPUTS Output Logic Sink Current, IOL Output Logic Source Current, IOH Output Three-State Leakage Current, IOZ Output Logic Sink Current, IOL Output Logic Source Current, IOH Output Three-State Leakage Current, IOZ Output Capacitance, COUT f1 = 1MHz, f2 = 1.02MHz fS = 17.72MHz, 6 Step, Mod Ramp fS = 17.72MHz, 6 Step, Mod Ramp (Note 3) (Note 3) -10 Differential Mode (Note 1) 0.625 - ±1.25 2.5 1 7 ±0.5 250 - V V MΩ pF µA µA V MHz Ω mA V V V +10 4.375 - 300 2.5 (Note 2) (Note 2) (Note 2) 1.95 2.575 400 3.125 3.25 2.0 2.625 500 4.2 3.3 2.675 - 2.8 - 1 V mA 2.0 VIH = 5V VIL = 0V - 7 0.8 10.0 10.0 - V V µA µA pF VO = 0.4V; DVCC2 = 5V VO = 2.4V; DVCC2 = 5V VO = 0/5V; DVCC2 = 5V VO = 0.4V; DVCC2 = 3.3V VO = 2.4V; DVCC2 = 3.3V VO = 0/3.3V; DVCC2 = 3.3V 1.6 -0.2 1.6 -0.2 - ±1 ±1 5 ±10 ±10 - mA mA µA mA mA µA pF 4-5 Electrical Specifications PARAMETER TIMING CHARACTERISTICS Aperture Delay, tAP Aperture Jitter, tAJ Data Output Delay, tOD AVCC = DVCC1 = DVCC2 = +5.0V; VREF+ = 3.25V; VREF - = 2.0V; fS = 36 MSPS at 50% Duty Cycle; CL = 20pF; TA = 25oC; Differential Analog Input; Unless Otherwise Specified (Continued) TEST CONDITION MIN TYP MAX UNITS AVCC = DVCC1 = 5V ±10%, DVCC2 = 3.3V ±5%, 0oC ≤ TA ≤ 70oC 5 5 5 7 7 18 ns ps ns ns Data Output Hold, tH Data Output Enable Time, tEN Data Output Enable Time, tDIS Clock Pulse Width (Low) Clock Pulse Width (High) Data Latency, tLAT Power-Up Initialization POWER SUPPLY CHARACTERISTICS Analog Supply Voltage, AVCC Digital Supply Voltage, DVCC1 Digital Output Supply Voltage, DVCC2 Total Supply Current, ICC Analog Supply Current, AICC Digital Supply Current, DICC1 Digital Output Supply Current, DICC2 Power Dissipation Offset Error Sensitivity, ∆VOS Full Scale Error Sensitivity, ∆FSE NOTES: 2. Parameter guaranteed by design or characterization and not production tested. 3. With the clock low and DC input. At 3.30V At 5.0V VIN+ - VIN- = +1.25V and DFS = “0” VIN+ - VIN- = +1.25V and DFS = “0” VIN+ - VIN- = +1.25V and DFS = “0” VIN+ - VIN- = +1.25V and DFS = “0” VIN+ - VIN- = +1.25V and DFS = “0” AVCC or DVCC = 5V ±5% AVCC or DVCC = 5V ±5% 40 MSPS Clock 40 MSPS Clock For a Valid Sample (Note 2) Data Invalid Time (Note 2) 11.875 11.875 - 4 7 7 12.5 12.5 - 13.125 13.125 7 20 ns ns ns ns ns Cycles Cycles 4.75 4.75 3.135 4.75 - 5.0 5.0 3.3 5.0 80 48 30 2 400 ±1.5 ±0.2 5.25 5.25 3.465 5.25 - V V V V mA mA mA mA mW LSB LSB 4-6 Timing Waveforms ANALOG INPUT CLOCK INPUT SN - 1 HN - 1 SN HN SN + 1 H N + 1 SN + 2 SN + 5 HN + 5 SN + 6 H N + 6 SN + 7 HN + 7 SN + 8 HN + 8 INPUT S/H 1ST STAGE B1, N - 1 B1, N B1, N + 1 B1, N + 4 B1, N + 5 B1, N + 6 B1, N + 7 2ND STAGE B2, N - 2 B2, N - 1 B2, N B2, N + 4 B2, N + 5 B2, N + 6 10TH STAGE B10, N - 5 B10, N - 4 B10, N B10, N + 1 B10, N + 2 B10, N + 3 DATA OUTPUT DN - 7 DN - 6 tLAT DN - 2 DN - 1 DN DN + 1 NOTES: 4. SN : N-th sampling period. 5. HN : N-th holding period. 6. BM , N : M-th stage digital output corresponding to N-th sampled input. 7. DN : Final data output corresponding to N-th sampled input. FIGURE 1. HI5703 INTERNAL CIRCUIT TIMING ANALOG INPUT tAP tAJ CLOCK INPUT 1.5V 1.5V tOD tH DATA OUTPUT 2.0V DATA N - 1 DATA N 0.8V FIGURE 2. INPUT-TO-OUTPUT TIMING 4-7 Typical Performance Curves -35 EFFECTIVE NUMBER OF BITS (ENOB) 9.0 -40 fS = 40 MSPS TEMPERATURE = 25oC 8.0 dBc -45 THD -50 -55 -60 -65 -70 6.0 1 2 4 6 8 10 20 40 60 80 100 -75 1 2 4 6 8 10 20 40 60 80 100 INPUT FREQUENCY (MHz) SFDR fS = 40 MSPS TEMPERATURE = 25oC 7.0 INPUT FREQUENCY (MHz) NOTE: SFDR depicted here does not include any harmonic distortion. FIGURE 3. EFFECTIVE NUMBER OF BITS (ENOB) vs INPUT FREQUENCY FIGURE 4. TOTAL HARMONIC DISTORTION (THD) AND SPURIOUS FREE DYNAMIC RANGE (SFDR) vs INPUT FREQUENCY 65 SNR POWER DISSIPATION (mW) 60 55 dB SINAD fS = 40 MSPS TEMPERATURE = 25oC -THD 450 430 410 390 370 350 330 310 290 270 VIN + - VIN- = +1.25V AND DFS = “0” TEMPERATURE = 25oC 50 45 40 35 1 2 4 6 8 10 20 INPUT FREQUENCY (MHz) 40 60 80 100 250 0 5 10 15 20 25 30 fS (MSPS) 35 40 45 50 FIGURE 5. SINAD, SNR, AND -THD vs INPUT FREQUENCY FIGURE 6. POWER DISSIPATION vs SAMPLE FREQUENCY 4-8 Typical Performance Curves 9.0 EFFECTIVE NUMBER OF BITS (ENOB) (Continued) 10.0 40 MSPS 8.5 8.0 45 MSPS 7.5 7.0 6.5 fIN = 10MHz 6.0 50 MSPS 5.5 5.0 -40 5.0 -40 -30 -20 -10 OUTPUT DELAY TIME (ns) 9.0 8.0 7.0 tOD 6.0 -20 0 20 40 60 80 100 0 10 20 30 40 50 60 70 80 85 TEMPERATURE (oC) TEMPERATURE (oC) FIGURE 7. EFFECTIVE NUMBER OF BITS (ENOB) vs TEMPERATURE AND SAMPLE FREQUENCY FIGURE 8. OUTPUT DELAY TIME (TOD) vs TEMPERATURE 450 440 POWER DISSIPATION (mW) 430 420 410 400 390 380 -40 fS = 40 MSPS VIN+ - VIN- = 1.25V, DFS = 0 EFFECTIVE NUMBER OF BITS (ENOB) 9.0 8.5 fS = 40 MSPS fIN = 10MHz TEMPERATURE = 25oC 8.0 7.5 -20 0 20 40 60 80 85 45 46 47 48 TEMPERATURE (oC) 49 50 51 52 DUTY CYCLE (%) 53 54 55 FIGURE 9. POWER DISSIPATION vs TEMPERATURE FIGURE 10. EFFECTIVE NUMBER OF BITS (ENOB) vs DUTY CYCLE (TH/TTOTAL) 4-9 Typical Performance Curves 9.5 EFFECTIVE NUMBER OF BITS (ENOB) (Continued) INTERMODULATION DISTORTION (dBc) 9.0 58.0 12.5ns 8.5 50% IMD 1MHz 56.0 8.0 fIN = fS/ 4 TEMPERATURE = 25oC 7.5 54.0 IMD 10MHz 7.0 0 10 20 30 fS (MSPS) 40 50 -40 -30 -20 -10 0 10 20 30 40 TEMPERATURE 50 60 70 80 85 FIGURE 11. EFFECTIVE NUMBER OF BITS (ENOB) vs SAMPLE FREQUENCY 0dB -10dB -20dB OUTPUT LEVEL (dB) -30dB -40dB -50dB -60dB -70dB -80dB -90dB -100dB 0 200 400 600 800 1000 FIGURE 12. INTERMODULATION DISTORTION (IMD) vs TEMPERATURE fIN = 10MHz fS = 40 MSPS 1200 1400 1600 1800 2047 FREQUENCY BIN FIGURE 13. 4096 POINT FFT SPECTRAL PLOT 4-10 Typical Performance Curves (Continued) 0dB -10dB -20dB OUTPUT LEVEL (dB) -30dB -40dB -50dB -60dB -70dB -80dB -90dB -100dB 0 200 400 600 800 1000 1200 1400 1600 1800 2047 FREQUENCY BIN fIN = 1MHz fS = 40 MSPS FIGURE 14. 4096 POINT FFT SPECTRAL PLOT 4-11 TABLE 1. PIN DESCRIPTION PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME DVCC1 DGND DVCC1 DGND AVCC AGND VREF+ VREF VIN+ VINVDC AGND AVCC OE DFS D9 D8 D7 D6 D5 DGND CLK DVCC2 D4 D3 D2 D1 D0 DESCRIPTION Digital Supply (+5.0V) Digital Ground Digital Supply (+5.0V) Digital Ground Analog Supply (+5.0V) Analog Ground Positive Reference Voltage Input Negative Reference Voltage Input Positive Analog Input Negative Analog Input DC Bias Voltage Output Analog Ground Analog Supply (+5.0V) Digital Output Enable Control Input Data Format Select Input Data Bit 9 Output (MSB) Data Bit 8 Output Data Bit 7 Output Data Bit 6 Output Data Bit 5 Output Digital Ground Sample Clock Input Digital Output Supply (+3.3V to +5V) Data Bit 4 Output Data Bit 3 Output Data Bit 2 Output Data Bit 1 Output Data Bit 0 Output (LSB) together and the holding capacitors are switched to the opamp output nodes. The charge then redistributes between CS and CH completing one sample-and-hold cycle. The output is a fully-differential, sampled-data representation of the analog input. The circuit not only performs the sampleand-hold function but will also convert a single-ended input to a fully-differential output for the converter core. During the sampling phase, the VIN pins see only the on-resistance of a switch and CS . The relatively small values of these components result in a typical full power input bandwidth of 250MHz for the converter. φ1 VIN+ CH φ1 φ1 φ2 CS -+ +CS VOUT+ VOUT- VIN- φ1 φ1 CH φ1 FIGURE 15. ANALOG INPUT SAMPLE-AND-HOLD As illustrated in the functional block diagram and the timing diagram in Figure 1, nine identical pipeline subconverter stages, each containing a two-bit flash converter and a twobit multiplying digital-to-analog converter, follow the S/H circuit with the tenth stage being a one bit flash converter. Each converter stage in the pipeline will be sampling in one phase and amplifying in the other clock phase. Each individual subconverter clock signal is offset by 180 degrees from the previous stage clock signal resulting in alternate stages in the pipeline performing the same operation. The two-bit digital output of each stage is fed to a digital delay line controlled by the internal clock. The purpose of the delay line is to align the digital output data to the corresponding sampled analog input signal. This delayed data is fed to the digital error correction circuit which corrects the error in the output data with the information contained in the redundant bits to form the final ten bit output for the converter. Because of the pipeline nature of this converter, the data on the bus is output at the 7th cycle of the clock after the analog sample is taken. This delay is specified as the data latency. After the data latency time, the data representing each succeeding sample is output at the following clock pulse. The output data is synchronized to the external clock by a double buffered latching technique. The digital output bits are available in offset binary or two’s complement format, the format being set by the Data Format Select (DFS) input. Detailed Description Theory of Operation The HI5703 is a 10-bit fully differential sampling pipeline A/D converter with digital error correction. Figure 15 depicts the circuit for the front end differential-in-differential-out sampleand-hold (S/H). The switches are controlled by an internal clock which is a non-overlapping two phase signal, φ1 and φ2 , derived from the master clock. During the sampling phase, φ1 , the input signal is applied to the sampling capacitors, CS . At the same time the holding capacitors, CH , are discharged to analog ground. At the falling edge of φ1 the input signal is sampled on the bottom plates of the sampling capacitors. In the next clock phase, φ2 , the two bottom plates of the sampling capacitors are connected 4-12 Reference Voltage Inputs, VREF - and VREF+ The HI5703 requires two reference voltages connected to the VREF pins. The HI5703 is tested with VREF - equal to 2V and VREF+ equal to 3.25V for a fully differential input voltage range of ±1.25V. VREF+ and VREF - can differ from the above voltages as long as the reference common mode voltage, ((VREF+ + VREF -)/2), does not exceed 2.625V ±50mV and the limits on VREF+ and VREF - are not exceeded. In order to minimize overall converter noise it is recommended that adequate high frequency decoupling be provided at the reference voltage input pins, VREF+ and VREF -. The analog input can be DC coupled (Figure 17) as long as the inputs are within the analog input common mode voltage range (0.625V ≤ VDC ≤ 4.375V). VIN VDC R C VIN+ HI5703 VDC -VIN VDC R VIN- Analog Input, Differential Connection The analog input to the HI5703 is a differential input that can be configured in various ways depending on the signal source and the required level of performance. A fully differential connection (Figure 16 and Figure 17) will give the best performance for the converter. VIN R VIN+ HI5703 VDC R -VIN VIN- FIGURE 17. DC COUPLED DIFFERENTIAL INPUT The resistors, R, in Figure 17 are not absolutely necessary but may be used as load setting resistors. A capacitor, C, connected from VIN+ to VIN- will help filter any high frequency noise on the inputs, also improving performance. Values around 20pF are sufficient and can be used on AC coupled inputs as well. Note, however, that the value of capacitor C chosen must take into account the highest frequency component of the analog input signal. Analog Input, Single-Ended Connection The configuration shown in Figure 18 may be used with a single ended AC coupled input. FIGURE 16. AC COUPLED DIFFERENTIAL INPUT VIN R VDC VIN+ HI5703 VIN- Since the HI5703 is powered by a single +5V analog supply, the analog input is limited to be between ground and +5V. For the differential input connection this implies the analog input common mode voltage can range from 0.625V to 4.375V. The performance of the ADC does not change significantly with the value of the analog input common mode voltage. A DC voltage source, VDC , equal to 2.8V (typical), is made available to the user to help simplify circuit design when using an AC coupled differential input. This low output impedance voltage source is not designed to be a reference but makes an excellent bias source and stays within the analog input common mode voltage range over temperature. It has a temperature coefficient of approximately +200ppm/oC. For the AC coupled differential input (Figure 16) assume the difference between VREF+, typically 3.25V, and VREF-, typically 2V, is 1.25V. Fullscale is achieved when the VIN+ and VIN- inputs are 1.25VP-P, with VIN- being 180 degrees out of phase with VIN+. The converter will be at positive fullscale when the VIN+ input is at VDC + 0.625V and VIN- is at VDC - 0.625V (VIN+ - VIN- = 1.25V). Conversely, the converter will be at negative full scale when the VIN+ input is equal to VDC - 0.625V and VIN- is at VDC + 0.625V (VIN+ VIN- = -1.25V). FIGURE 18. AC COUPLED SINGLE ENDED INPUT Again, assume the difference between VREF+, typically 3.25V, and VREF-, typically 2V, is 1.25V. If VIN is a 2.5VP-P sinewave, then VIN+ is a 2.5VP-P sinewave riding on a positive voltage equal to VDC. The converter will be at positive fullscale when VIN+ is at VDC + 1.25V and will be at negative fullscale when VIN+ is equal to VDC - 1.25V. Sufficient headroom must be provided such that the input voltage never goes above +5V or below AGND. In this case, VDC could range between 1.25V and 3.75V without a significant change in ADC performance. The simplest way to produce VDC is to use the VDC output of the HI5703. 4-13 The single ended analog input can be DC coupled (Figure 19) as long as the input is within the analog input common mode voltage range. VIN VDC R C HI5703 VIN+ OE INPUT 0 1 DIGITAL DATA OUTPUTS Active High Impedance Supply and Ground Considerations The HI5703 has separate analog and digital supply and ground pins to keep digital noise out of the analog signal path. The digital data outputs also have a separate supply pin, DVCC2 , which can be powered from a 3.3V to 5.0V supply. This allows the outputs to interface with 3.3V logic if so desired. The part should be mounted on a board that provides separate low impedance connections for the analog and digital supplies and grounds. For best performance, the supplies to the HI5703 should be driven by clean, linear regulated supplies. The board should also have good high frequency decoupling capacitors mounted as close as possible to the converter. If the part is powered off a single supply then the analog supply and ground pins should be isolated by ferrite beads from the digital supply and ground pins. Refer to the application notes “Using Intersil High Speed A/D Converters” (AN9214) for additional considerations when using high speed converters. VDC VIN- FIGURE 19. DC COUPLED SINGLE ENDED INPUT The resistor, R, in Figure 19 is not absolutely necessary but may be used as a load setting resistor. A capacitor, C, connected from VIN+ to VIN- will help filter any high frequency noise on the inputs, also improving performance. Values around 20pF are sufficient and can be used on AC coupled inputs as well. Note, however, that the value of capacitor C chosen must take into account the highest frequency component of the analog input signal. A single ended source may give better overall system performance if it is first converted to differential before driving the HI5703. Refer to the application notes AN9534, “Using the HI5703 Evaluation Board”, and AN9413, “Driving the Analog Input of the HI5702”. Application note AN9413 applies to the HI5703 as well as the HI5702 and describes several different ways of driving the analog differential inputs. Static Performance Definitions Offset Error (VOS) The midscale code transition should occur at a level 1/4 LSB above half-scale. Offset is defined as the deviation of the actual code transition from this point. Digital Output Control and Clock Requirements The HI5703 provides a standard high-speed interface to external TTL logic families. In order to ensure rated performance of the HI5703, the duty cycle of the clock should be held at 50% ±5%. It must also have low jitter and operate at standard TTL levels. Performance of the HI5703 will only be guaranteed at conversion rates above 1 MSPS. This ensures proper performance of the internal dynamic circuits. Similarly, when power is first applied to the converter, a maximum of 20 cycles at a sample rate above 1 MSPS will have to be performed before valid data is available. A Data Format Select (DFS) pin is provided which will determine the format of the digital data outputs. When at logic low, the data will be output in offset binary format. When at logic high, the data will be output in two’s complement format. Refer to Table 2 for further information. The output enable pin, OE, when pulled high will three-state the digital outputs to a high impedance state. Set the OE input to logic low for normal operation. Full-Scale Error (FSE) The last code transition should occur for an analog input that is 3/4 LSB below positive Fullscale (+FS) with the offset error removed. Full-scale error is defined as the deviation of the actual code transition from this point. Differential Linearity Error (DNL) DNL is the worst case deviation of a code width from the ideal value of 1 LSB. Integral Linearity Error (INL) INL is the worst case deviation of a code center from a best fit straight line calculated from the measured data. Power Supply Sensitivity Each of the power supplies are moved plus and minus 5% and the shift in the offset and full scale error (in LSBs) is noted. 4-14 TABLE 2. A/D CODE TABLE OFFSET BINARY OUTPUT CODE (DFS LOW) M S B L S B D8 1 1 0 1 0 0 D7 1 1 0 1 0 0 D6 1 1 0 1 0 0 D5 1 1 0 1 0 0 D4 1 1 0 1 0 0 D3 1 1 0 1 0 0 D2 1 1 0 1 0 0 D1 1 1 0 1 0 0 D0 1 0 0 1 1 0 M S B D9 0 0 0 1 1 1 D8 1 1 0 1 0 0 D7 1 1 0 1 0 0 D6 1 1 0 1 0 0 D5 1 1 0 1 0 0 D4 1 1 0 1 0 0 D3 1 1 0 1 0 0 D2 1 1 0 1 0 0 D1 1 1 0 1 0 0 TWO’S COMPLEMENT OUTPUT CODE (DFS HIGH) L S B D0 1 0 0 1 1 0 CODE CENTER DESCRIPTION 1/ LSB 4 DIFFERENTIAL INPUT VOLTAGE (VIN+ - VIN-) D9 1.24939V 1.24695V 1.83mV -0.610mV -1.24573V -1.24817V 1 1 1 0 0 0 +Full Scale (+FS) - +FS - 11/4 LSB +3/4 LSB -1/4 LSB -FS + 13/4 LSB -Full Scale (-FS) + 3/4 LSB NOTES: 8. The voltages listed above represent the ideal center of each output code shown as a function of the reference voltage. 9. VREF+ = 3.25V and VREF - = 2.0V. Dynamic Performance Definitions Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the HI5703. A low distortion sine wave is applied to the input, it is coherently sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with an FFT and analyzed to evaluate the dynamic performance of the A/D. The sine wave input to the part is -0.5dB down from full scale for all these tests. SNR and SINAD are quoted in dB. The distortion numbers are quoted in dBc (decibels with respect to carrier) and DO NOT include any correction factors for normalizing to full scale. Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first 5 harmonic components to the RMS value of the fundamental input signal. 2nd and 3rd Harmonic Distortion This is the ratio of the RMS value of the applicable harmonic component to the RMS value of the fundamental input signal. Spurious Free Dynamic Range (SFDR) SFDR is the ratio of the fundamental RMS amplitude to the RMS amplitude of the next largest spectral component in the spectrum below fS /2. Effective Number Of Bits (ENOB) The effective number of bits (ENOB) is calculated from the SINAD data by: ENOB = (SINAD - 1.76 + VCORR) / 6.02 where: VCORR = 0.5 dB Intermodulation Distortion (IMD) Nonlinearities in the signal path will tend to generate intermodulation products when two tones, f1 and f2 , are present at the inputs. The ratio of the measured signal to the distortion terms is calculated. The terms included in the calculation are (f1+f2), (f1-f2), (2f1), (2f2), (2f1+f2), (2f1-f2), (f1+2f2), (f1-2f2). The ADC is tested with each tone 6dB below full scale. VCORR adjusts the ENOB for the amount the input is below fullscale. Signal To Noise and Distortion Ratio (SINAD) SINAD is the ratio of the measured RMS signal to RMS sum of all the other spectral components below the Nyquist frequency, fS /2, excluding DC. Transient Response Transient response is measured by providing a full scale transition to the analog input of the ADC and measuring the number of cycles it takes for the output code to settle within 10-bit accuracy. Signal To Noise Ratio (SNR) SNR is the ratio of the measured RMS signal to RMS noise at a specified input and sampling frequency. The noise is the RMS sum of all of the spectral components below fS /2 excluding the fundamental, the first five harmonics and DC. Over-Voltage Recovery Over-Voltage Recovery is measured by providing a full scale transition to the analog input of the ADC which overdrives the input by 200mV, and measuring the number of cycles it takes for the output code to settle within 10-bit accuracy. 4-15 Full Power Input Bandwidth (FPBW) Full power input bandwidth is the analog input frequency at which the amplitude of the digitally reconstructed output has decreased 3dB below the amplitude of the input sine wave. The input sine wave has an amplitude which swings from -FS to +FS. The bandwidth given is measured at the specified sampling frequency. at which the signal is actually sampled. This delay is due to internal clock path propagation delays. Aperture Jitter (tAJ) Aperture jitter is the RMS variation in the aperture delay due to variation of internal clock path delays. Data Hold Time (tH) Data hold time is the time to where the previous data (N - 1) is no longer valid. Video Definitions Differential Gain and Differential Phase are two commonly found video specifications for characterizing the distortion of a chrominance signal as it is offset through the input voltage range of an ADC. Data Output Delay Time (tOD) Data output delay time is the time to where the new data (N) is valid. Differential Gain (DG) Differential Gain is the peak difference in chrominance amplitude (in percent) relative to the reference burst. Data Latency (tLAT) After the analog sample is taken, the digital data is output on the bus at the 7th cycle of the clock. This is due to the pipeline nature of the converter where the data has to ripple through the stages. This delay is specified as the data latency. After the data latency time, the data representing each succeeding sample is output at the following clock pulse. The digital data lags the analog input sample by 7 cycles. Differential Phase (DP) Differential Phase is the peak difference in chrominance phase (in degrees) relative to the reference burst. Timing Definitions Refer to Figure 1 and Figure 2 for these definitions. Power-Up initialization This time is defined as the maximum number of clock cycles that are required to initialize the converter at power-up. The requirement arises from the need to initialize the dynamic circuits within the converter. Aperture Delay (tAP) Aperture delay is the time delay between the external sample command (the falling edge of the clock) and the time AMP A/D DSP/µP D/A AMP HFA1100 HFA1105 HFA1106 HFA1135 HFA1145 HFA1245 HI5702 HI5703 HSP9501 HSP48410 HSP48908 HSP48212 HSP43891 HSP43168 HSP43216 HI5780 HI1171 CA3338 HA5020 HA2842 HFA1115 HFA1212 HFA1412 HFA1100: HFA1105: HFA1106: HFA1135: HFA1145: HFA1245: HI5702: HI5703: HSP9501: HSP48410: 850MHz Video Op Amp 300MHz Video Op Amp 250MHz Video Op Amp with Bandwidth Limit Control 350MHz Video Op Amp with Output Limiting 300MHz Video Op Amp with Output Disable Dual 350MHz Video Op Amp with Output Disable 10-Bit, 40 MSPS, A/D Converter 10-Bit, 40 MSPS, Low Power A/D Converter Programmable Data Buffer Histogrammer/Accumulating Buffer, 10-Bit Pixel Resolution HSP48908: 2-D Convolver, 3 x 3 Kernal Convolution, 8-Bit HSP48212: HSP43891: HSP43168: HSP43216: HI5780: HI1171: CA3338: HA5020: HA2842: HFA1115: HFA1212: HFA1412: Digital Video Mixer Digital Filter, 30MHz, 9-Bit Dual FIR Filter, 10-Bit, 33MHz/45MHz Digital Half Band Filter 10-Bit, 80 MSPS, Video D/A Converter 8-Bit, 40 MSPS, Video D/A Converter 8-Bit, 50 MSPS, Video D/A Converter 100MHz Video Op Amp High Output Current, Video Op Amp 225MHz Programmable Gain Video Buffer with Output Limiting 350MHz, Dual Programmable Gain Video Buffer 350MHz, Quad Programmable Gain Video Buffer In addition, CMOS Logic Families in HC/HCT, AC/ACT, FCT and CD4000 are available. FIGURE 20. 10-BIT VIDEO IMAGING COMPONENTS 4-16 AMP A/D DSP/µP D/A AMP HFA1100 HFA1110 HFA3101 HFA3102 HFA3600 HI5702 HI5703 HSP43168 HSP43216 HSP43220 HSP43891 HSP50016 HSP50110 HSP50210 HI5721 HI5780 HI20201 HI20203 HFA1112 HFA1113 HFA1100: 850MHz Op Amp HFA1110: 750MHz Unity Gain Video Buffer HFA3101: Gilbert Cell Transistor Array HFA3102: Dual Long-Tailed Pair Transistor Array HFA3600: Low Noise Amplifier/Mixer HI5702: 10-Bit, 40 MSPS, A/D Converter HI5703: 10-Bit, 40 MSPS, Low Power A/D Converter HSP43168: Dual FIR Filter, 10-Bit, 33MHz/45MHz HSP43216: Digital Half Band Filter HSP43220: Decimating Digital Filter HSP43891: Digital Filter, 30MHz, 9-Bit HSP50016: Digital Down Converter HSP50110: Digital Quadrature Tuner HSP50210: Digital Costas Loop HI5721: 10-Bit, 100 MSPS, Communications D/A Converter HI5780: 10-Bit, 80 MSPS, D/A Converter HI20201: 10-Bit, 160 MSPS, High Speed D/A Converter HI20203: 8-Bit, 160 MSPS, High Speed D/A Converter HFA1112: 850MHz Programmable Gain Video Buffer HFA1113: 850MHz Programmable Gain Video Buffer with Output Limiting In addition, CMOS Logic Families in HC/HCT, AC/ACT, FCT and CD4000 are available. FIGURE 21. 10-BIT COMMUNICATIONS COMPONENTS 4-17 HI5703 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M28.3 (JEDEC MS-013-AE ISSUE C) 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 L MILLIMETERS MIN 2.35 0.10 0.33 0.23 17.70 7.40 MAX 2.65 0.30 0.51 0.32 18.10 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0926 0.0040 0.013 0.0091 0.6969 0.2914 MAX 0.1043 0.0118 0.0200 0.0125 0.7125 0.2992 B C D E α A1 0.10(0.004) C e H h L N 0.05 BSC 0.394 0.01 0.016 28 0o 8o 0.419 0.029 0.050 1.27 BSC 10.00 0.25 0.40 28 0o 10.65 0.75 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369 4-18