HI5714

® HI5714 Data Sheet July 2004 FN3973.6 8-Bit, 40/60/75/80 MSPS A/D Converter The HI5714 is a high precision, monolithic, 8-bit, Analog-toDigital Converter fabricated in Intersil’ advanced HBC10 BiCMOS process. The HI5714 is optimized for a wide range of applications such as ultrasound imaging, mass storage, instrumentation, and video digitizing, where accuracy and low power consumption are essential. The HI5714 is offered in 40 MSPS, 60 MSPS, and 75 MSPS sample rates. The HI5714 delivers ±0.4 LSB differential nonlinearity while consuming only 325mW power (Typical) at 75 MSPS. The digital inputs and outputs are TTL compatible, as well as allowing for a low-level sine wave clock input. Features • Sampling Rate . . . . . . . . . . . . . . . . . . . 40/60/75/80 MSPS • Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325mW • 7.65 ENOB at 4.43MHz • Overflow/Underflow Three-State TTL Output • Operates with Low Level AC Clock • Very Low Analog Input Capacitance • No Buffer Amplifier Required • No Sample and Hold Required • TTL Compatible I/O • Pin-Compatible to Philips TDA8714 Ordering Information PART NUMBER HI5714/4CB HI5714/4CBZ (Note) HI5714/7CB-T TEMP. RANGE (°C) 0 to 70 0 to 70 SAMPLING FREQUENCY PKG. DWG. # (MHz) 40 40 M24.3 M24.3 • Pb-free Available Applications • Video Digitizing • QAM Demodulator • Digital Cable Setup Box • Tape Drive/Mass Storage • Medical Ultrasound Imaging PACKAGE 24 Ld SOIC 24 Ld SOIC (Pb-free) 24 Ld SOIC Tape & Reel 24 Ld SOIC Tape & Reel (Pb-free) 0 to 70 75 M24.3 HI5714/7CBZ-T (Note) 0 to 70 75 M24.3 • Communication Systems Pinout HI5714 (SOIC) TOP VIEW D1 D0 NC VRB NC AGND VCCA VIN VRT 1 2 3 4 5 6 7 8 9 24 D2 23 D3 22 OE 21 VCCO2 20 OGND 19 VCCO1 18 VCCD 17 DGND 16 CLK 15 D4 14 D5 13 D6 HI5714EVAL 25 Evaluation Board NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. NC 10 O/UF 11 D7 12 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Harris Corporation 1998. Copyright Intersil Americas Inc. 2003, 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HI5714 Functional Block Diagram VCCA 7 16 CLOCK DRIVER VRT 9 CLK VCCD 18 OE 22 12 13 14 15 D7 D6 D5 D4 D3 D2 D1 D0 VCCO1 VCCO2 O/UF VIN 8 ANALOG TO DIGITAL CONVERTER LATCHES TTL OUTPUTS 23 24 1 2 19 21 VRB 4 OGND 20 OVERFLOW/UNDERFLOW LATCH 6 AGND 17 DGND 11 TTL OUTPUT Typical Application Schematic +5VA 16 0.1 1.3V 0.1 9 4 22 D0 CLK VRT VRB OE D1 D2 D3 D4 D5 D6 2 1 24 23 15 14 13 CLOCK + 3.6V - + - HI5714 VIN + 8 - VIN 12 D7 11 O/UF 19 VCCO 21 VCCO 18 VCCD 20 OGND 3 NC 17 DGND 10 NC +5VA 7 1nF 0.1µF 5 6 1nF 0.1µF +5VD VCCA NC AGND DGND AGND BNC 1nF and 0.1µF CAPS are placed as close to part as possible. NOTES: 1. Pin 5 should be connected to AGND and pins 3 and 10 to DGND to reduce noise coupling into the device. 2. Analog and Digital supplies should be separated and decoupled to reduce digital noise coupling into the analog supply. 2 HI5714 Absolute Maximum Ratings TA = 25oC VCCA, VCCD, VCCO . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V VCCA - VCCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V VCCO - VCCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V VCCA - VCCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V VIN , VCLK , VRT, VRB , OE. . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V IOUT, Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Input Current, All Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OGND to VCCO Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range HI5714/XCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VCCA = VCCD = VCCO = +5V; VRB = 1.3V; VRT = 3.6V; TA = 25oC, Unless Otherwise Specified TEST CONDITION MIN TYP MAX UNITS PARAMETER CLOCK (Referenced to DGND) (Note 2) Logic Input Voltage Low, VIL Logic Input Voltage High, VIH Logic Input Current Low, IIL Logic Input Current High, IIH Input Impedance, ZIN Input Capacitance, CIN OE (Referenced to DGND) Logic Input Voltage Low, VIL Logic Input Voltage High, VIH Logic Input Current Low, IIL Logic Input Current High, IIH VIN (Referenced to AGND) Input Current Low, IIL Input Current High, IIH Input Impedance, ZIN Input Capacitance, CIN REFERENCE INPUT Bottom Reference Range, VRB Top Reference Range, VRT Reference Range, VREF (VRT - VRB) Reference Current, IREF Reference Ladder Resistance, RLAD RLADTC Bottom Offset Voltage, VOB VOBTC Top Offset Voltage, VOT VOTTC (Note 5) (Note 5) (Note 5) (Note 5) 0 2.0 VCLK = 0.4V VCLK = 2.7V fCLK = 75MHz (Note 9) fCLK = 75MHz (Note 9) -400 - 2 4.5 0.8 VCCD 300 - V V µA µA kΩ pF 0 2.0 VIL = 0.4V VIH = 2.7V -400 - - 0.8 VCCD 20 V V µA µA VIN = 1.2V VIN = 3.5V fIN = 4.43MHz fIN = 4.43MHz - 0 100 10 14 180 - µA µA kΩ pF 1.2 3.5 1.9 - 1.3 3.6 2.3 10 240 0.24 255 136 -300 480 1.6 3.9 2.7 - V V V mA Ω Ω/oC mV µV/oC mV µV/oC 3 HI5714 Electrical Specifications PARAMETER DIGITAL OUTPUTS (D0 to D7 and O/UF Referenced to OGND) Logic Output Voltage Low, VOL Logic Output Voltage High, VOH Output Leakage Current, ID IO = 1mA IO = -0.4mA 0.4V < VOUT < VCCO 0 2.7 -20 0.4 VCCO +20 V V µA VCCA = VCCD = VCCO = +5V; VRB = 1.3V; VRT = 3.6V; TA = 25oC, Unless Otherwise Specified (Continued) TEST CONDITION MIN TYP MAX UNITS SWITCHING CHARACTERISTICS (Notes 4, 5) See Figure 1 Sample Rate, fCLK HI5714/7 HI5714/4 Clock Pulse Width High, tCPH Clock Pulse Width Low, tCPL ANALOG SIGNAL PROCESSING (fCLK = 40MHz) Differential Gain, DG Differential Phase, DP HARMONICS (fCLK = 75MHz) Second Harmonic, H2 Third Harmonic, H3 Total Harmonic Distortion, THD Spurious Free Dynamic Range, SFDR Analog Input Bandwidth (-3dB) TRANSFER FUNCTION Differential Linearity Error, DNL Integral Linearity Error, INL EFFECTIVE NUMBER OF BITS ENOB HI5714/4 (fCLK = 40MHz) fIN = 4.43MHz fIN = 7.5MHz HI5714/7 (fCLK = 75MHz) fIN = 4.43MHz fIN = 7.5MHz fIN = 10MHz Bit Error Rate, BER TIMING (fCLK = 75MHz) See Figures 1, 2 Sampling Delay, tSD Output Hold Time, tHD Output Delay Time, tD Output Enable Delay, tPZH Output Enable Delay, tPZL Output Disable Delay, tPHZ Output Disable Delay, tPLZ Aperture Jitter, tAJ HI5714/4/7 Enable to High Enable to Low Disable from High Disable from Low 5 10 14.6 17.8 5.3 6.7 50 2 13 ns ns ns ns ns ns ns ps (Note 8) 7.65 7.5 7.4 7.15 6.8 10-11 Bits Bits Bits Bits Bits Times/ Sample (Note 7) (Note 7) ± 0.4 ± 0.75 LSB LSB fIN = 4.43MHz fIN = 4.43MHz fIN = 4.43MHz fIN = 4.43MHz -63 -65 -59 62 18 dB dB dB dB MHz (Notes 6, 9) (Notes 6, 9) 1.0 0.05 % degree 75 40 6 6 MHz MHz ns ns 4 HI5714 Electrical Specifications PARAMETER POWER SUPPLY CHARACTERISTICS Analog Power Supply Range, VCCA Digital Power Supply Range, VCCD Output Power Supply Range, VCCO Total Supply Current Supply Current, ICCA Supply Current, ICCD Supply Current, ICCO Power Dissipation NOTES: 2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. 3. The supply voltages VCCA and VCCD may have any value between -0.3V and +6V as long as the difference VCCA - VCCD lies between -0.3V and +0.3V. 4. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock not be less than 1ns. 5. Analog input voltages producing code 00 up to and including FF. VOB (Bottom Offset Voltage) is the difference between the analog input which produces data equal to 00 and the Bottom Reference Voltage (VRB). VOBTC (Bottom Offset Voltage Temperature Coefficient) is the variation of VOB with temperature. VOT (Top Offset Voltage) is the difference between the Top Reference Voltage (VRT) and the analog input which produces data output equal to FF. VOTTC (Top Offset Voltage Temperature Coefficient) is the variation of VOT with temperature. 6. Input is standard 5 step video test signal. A 12-bit R reconstruct DAC and VM700 are used for measurement. 7. Full scale sinewave, fIN = 4.43MHz. 8. fCLK = 75MHz, fIN = 4.43MHz, VIN = ±8 LSB at code 128, 50% Clock duty cycle. 9. Parameter is guaranteed by design, not production tested. 4.75 4.75 4.75 5.0 5.0 5.0 65 30 26 9 325 5.25 5.25 5.25 75 375 V V V mA mA mA mA mW VCCA = VCCD = VCCO = +5V; VRB = 1.3V; VRT = 3.6V; TA = 25oC, Unless Otherwise Specified (Continued) TEST CONDITION MIN TYP MAX UNITS 5 HI5714 Timing Waveforms tCPL tCPH CLOCK INPUT 1.4V SAMPLE N SAMPLE N + 1 SAMPLE N + 2 ANALOG INPUT tDS tHD 2.4V 1.4V 0.4V DATA (D0-D7) OUTPUTS DN - 2 DN - 1 tD DN DN + 1 FIGURE 1. INPUT-TO-OUTPUT TIMING 4V OE INPUT 1.4V 1.4V 0V tPZL DIGITAL OUTPUT VOL tPZH DIGITAL OUTPUT tPHZ 0.3V 0.3V VOH tPLZ 3.5V 0V FIGURE 2. THREE-STATE TIMING CIRCUIT 6 HI5714 Typical Performance Curves 0 70 60 50 LSB mA 40 30 20 10 0 -40 -30 -20 -10 0 10 20 30 40 TEMPERATURE (oC) 50 60 70 80 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 -40 -30 -20 -10 0 10 20 30 40 50 TEMPERATURE (oC) 60 70 80 90 FIGURE 3. TOTAL ICC vs TEMPERATURE FIGURE 4. INTEGRAL LINEARITY ERROR vs TEMPERATURE 0 -0.1 -0.2 280 270 260 -0.3 OHMS -0.4 LSB -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 210 200 -40 -30 -20 250 240 230 220 -10 0 10 20 30 40 50 60 70 80 TEMPERATURE (oC) TEMPERATURE (oC) FIGURE 5. DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE FIGURE 6. REFERENCE RESISTANCE vs TEMPERATURE -220 -230 -240 -250 -260 mV -270 -280 -290 -300 -310 -320 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 mV 260 250 240 230 220 210 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 TEMPERATURE (oC) TEMPERATURE (oC) FIGURE 7. VOT vs TEMPERATURE FIGURE 8. VOB vs TEMPERATURE 7 HI5714 Pin Descriptions PIN NUMBER 1, 2, 12-15, 23, 24 4 6 7 8 9 11 16 17 18 19, 21 20 22 SYMBOL D0 to D7 VRB AGND VCCA VIN VRT O/UF CLK DGND VCCD VCCO1, VCCO2 OGND OE Digital Outputs, D0 (LSB) to D7 (MSB). Bottom Reference Voltage Input. Range: 1.2V to 1.6V. Analog Ground. Analog +5V. Analog Input. Top Reference Voltage Input. Range: 3.5V to 3.9V. Underflow/Overflow Digital Output. Goes high if the analog input goes above or below the reference (VRB , VRT) minus the offset. Clock Input. Digital GND. Digital +5V. Digital +5V for Digital Output Stage. Digital Ground for Digital Output Stage. Output Enable High: Digital outputs are three-stated. Low: Digital outputs are active. DESCRIPTION TABLE 1. A/D CODE TABLE (NOTE 1) INPUT VOLTAGE VRT = 3.6V VRB = 1.3V 3.300V BINARY OUTPUT CODE O/UF 1 0 0 0 0 0 0 1 CODE DESCRIPTION Underflow 0 1 254 255 Overflow NOTE: D7 0 0 1 1 1 D6 0 0 1 1 1 D5 0 0 1 1 1 D4 0 0 1 1 1 D3 0 0 1 1 1 D2 0 0 1 1 1 D1 0 0 1 1 1 D0 0 0 0 1 1 10. The voltages listed above represent the ideal transition of each output code shown as a function of the reference voltage, including the typical reference offset voltages. TABLE 2. MODE SELECTION OE 1 0 D7 to D0 High Impedance Active: Binary O/UF High Impedance Active 8 HI5714 Detailed Description Theory of Operation The HI5714 design utilizes a folding and interpolating architecture. This architecture reduces the number of comparators, reference taps, and latches, thereby reducing power requirements, die size and cost. A folding A/D converter operates basically like a 2 step subranging converter by using 2 lower resolution converters to do a course and subranged fine conversion. A more complete description is given in the application note “Using the HI5714 Evaluation Module” (AN9517). bottom reference voltage, VRB , the digital outputs will remain at all 0s until the analog input goes above VRT. Analog Input The analog input will accept a voltage within the reference voltage levels, VRB and VRT, minus some offset. The offset is specified in the Electrical Specifications table. The analog input is relatively high impedance (10kΩ) but should be driven from a low impedance source. The input capacitance is low (14pF) and there is little kickback from the input, so a series resistance is not necessary but it may help to prevent the driving amplifier from oscillating. The input bandwidth is typically 18MHz. Exceeding 18MHz will result in sparkle at the digital outputs. The bandwidth remains constant at clock rates up to 75MHz. Reference Input, VRT and VRB The HI5714 requires an external reference to be connected to pins 4 and 9, VRB and VRT. It is recommended that adequate high frequency decoupling be provided at the reference input pin in order to minimize overall converter noise. A 0.1µF and a 1nF capacitor as close as possible to the reference pins work well. VRT must be kept within the range of 3.5V to 3.9V and VRB within 1.2V to 1.6V. If the reference voltages go outside their respective ranges, the input folding amplifiers may saturate giving erroneous digital data. The range for (VRT - VRB) is 1.9V to 2.7V, which defines the analog input range. Supply and Ground Considerations In order to keep digital noise out of the analog signal path, the HI5714 has separate analog and digital supply and ground pins. The part should be mounted on a board that provides separate low impedance connections for the analog and digital supplies and grounds. The analog and digital grounds should be tied together at one point near the HI5714. The grounds can be connected directly, through an inductor (ferrite bead), or a low valued resistor. DGND and AGND can be tied together. To help minimize noise, tie pin 5 (NC) to AGND and pins 3 (NC) and 10 (NC) to DGND. For best performance, the supplies to the HI5714 should be driven by clean, linear regulated supplies. The board should also have good high frequency leaded decoupling capacitors mounted as close as possible to the converter. Capacitor leads must be kept as short as possible (less than 1/2 inch total length). A 0.1µF and a 1nF capacitor as close as possible to the pin works well. Chip capacitors will provide better high frequency decoupling but leaded capacitors appear to be adequate. If the part is to be powered by a single supply, then the analog supply pins should be isolated by ferrite beads from the digital supply pins. This should help minimize noise on the analog power pins. Refer to Application Note AN9214, “Using Intersil High Speed A/D Converters”, for additional considerations when using high speed converters. Digital Control and Clock Requirements The HI5714 provides a standard high-speed interface to external TTL logic families. The outputs can be three-stated by setting the OE input (pin 22) high. The clock input operates at standard TTL levels as well as a low level sine wave around the threshold level. The HI5714 can operate with clock frequencies from DC to 75MHz. The clock duty cycle should be 50% ±10% to ensure rated performance. Duty cycle variation, within the specified range, has little effect on performance. Due to the clock speed it is important to remember that clock jitter will affect the quality of the digital output data. The clock can be stopped at any time and restarted at a later time. Once restarted the digital data will be valid at the second rising edge of the clock plus the data delay time. Digital Outputs and O/UF Output The digital outputs are standard TTL type outputs. The HI5714 can drive 1 to 3 TTL inputs depending on the input current requirements. Should the analog input exceed the top or bottom reference the over/underflow output (pin 11) will go high. Should the analog input exceed the top reference voltage, VRT, the digital outputs will remain at all 1s until the analog input goes below VRT. Also, should the analog input go below the Increased Accuracy Further calibration of the ADC can be done to increase absolute level accuracy. First, a precision voltage equal to the ideal VIN-FS + 0.5 LSB is applied at VIN . Adjust VRB until the 0 to 1 transition occurs on the digital output. Next, a voltage equal to the ideal VIN+FS - 1.5 LSB is applied at VIN . VRT is then adjusted until the 254 to 255 transition occurs on the digital output. 9 HI5714 Applications Figures 9 and 10 show two possible circuit configurations, AC coupled with a DC restore circuit and DC coupled with a DC offset amplifier. +5VA 16 0.1 1.3V 0.1 9 4 22 D0 CLK VRT VRB OE HI5714 VIN SAMPLE PULSE +5VA 10 0.1 5 DC RESTORE 8 VIN D1 D2 D3 D4 D5 D6 D7 O/UF VCCO VCCO VCCD OGND NC DGND NC 2 1 24 23 15 14 13 12 11 19 21 18 10 20 3 17 10 0.1 Due to the high clock rate, FCT (TTL/CMOS) or FAST (TTL) glue logic should be used. FCT logic will tend to have large overshoots if not loaded. Long traces (>2 or 3 inches) should be terminated to maintain signal integrity. + 3.6V CLOCK - + - +5VD 7 VCCA NC 6 AGND FIGURE 9. TYPICAL AC COUPLED INPUT WITH DC RESTORE +5VA D0 CLK VRT VRB OE HI5714 VIN +5VA +5VA 7 10 0.1 VCCA + 8 D1 D2 D3 D4 D5 D6 D7 O/UF VCCO VCCO VCCD OGND NC DGND NC 2 1 24 23 15 14 13 12 11 19 21 18 10 20 3 17 10 0.1 CLOCK + 3.6V 0.1 1.3V 0.1 16 9 4 22 - + - - VIN +5VD OFFSET 5 NC 6 AGND FIGURE 10. TYPICAL DC COUPLED INPUT 10 HI5714 ICL8069 REFERENCE AMP A/D DSP/µP D/A AMP HA5020 (Single) HA5022 (Dual) HA5024 (Quad) HA5013 (Triple) HFA1105 (Single) HFA1205 (Dual) HFA1405 (Quad) HI5714 (8-Bit) HSP9501 HSP48410 HSP48908 HSP48901 HSP48212 HSP43881 HSP43168 HI1171 (8-Bit) CA3338 (8-Bit) HI5721 (10-Bit) HI3050 (10-Bit) HA5020 (Single) HA2842 (Single) HFA1115 (Single) HFA1212 (Dual) HFA1412 (Quad) HSP9501: Programmable Data Buffer HSP48410: Histogrammer/accumulating Buffer, 10-Bit Pixel Resolution, 4K x 4K Frame Size HSP48908: 2-D Convolver, 3 x 3 Kernal Convolution, 8-Bit HSP48901: 3 x 3 Image Filter, 30MHz, 8-Bit HSP48212: Video Mixer HSP43881: Digital Filter, 30MHz, 1-D and 2-D Fir Filters HSP43168: Dual Fir Filter, 10-Bit, 33/45MHz CMOS Logic Available in FCT FIGURE 11. 8-BIT VIDEO COMPONENTS Timing Definitions Aperture Delay: Aperture delay is the time delay between the external sample command (the rising edge of the clock) and the time at which the signal is actually sampled. This delay is due to internal clock path propagation delays. Aperture Jitter: This is the RMS variation in the aperture delay due to variation of internal clock path delays. Bottom Offset Voltage (VOB) The first code transition should occur at a level 0.5 LSB above the negative full-scale. Bottom offset voltage is defined as the deviation of the actual code transition from this point. Top Offset Voltage (VOT) The last code transition should occur for a analog input that is 1.5 LSBs below positive full-scale. Top Offset Voltage is defined as the deviation of the actual code transition from this point. Data Latency After the analog sample is taken, the data on the bus is output at the next rising edge of the clock. This is due to the output latch of the converter. This delay is specified as the data latency. After the data latency time, the data representing each succeeding sample is output at the following clock pulse. The digital data lags the analog input by 1 cycle. Differential Linearity Error (DNL) DNL is the worst case deviation of a code width from the ideal value of 1 LSB. The converter is guaranteed to have no missing codes. Integral Linearity Error (INL) INL is the worst case deviation of a code center from a best fit straight line calculated from the measured data. Static Performance Definitions Offset Error and Full-Scale Error use a measured value of the external voltage reference to determine the ideal plus and minus full-scale values. The results are all displayed in LSBs. 11 HI5714 Dynamic Performance Definitions Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the HI5714. A low distortion sine wave is applied to the input, it is sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with a 2048 point FFT and analyzed to evaluate the dynamic performance of the A/D. The sine wave input to the part is 0.5dB down from full scale for these tests. The distortion numbers are quoted in dBc (decibels with respect to carrier) and DO NOT include any correction factors for normalizing to full scale. Signal-to-Noise + Distortion Ratio (SINAD) SINAD is the measured RMS signal to RMS sum of all other spectral components below the Nyquist frequency excluding DC. Effective Number Of Bits (ENOB) The effective number of bits (ENOB) is derived from the SINAD data. ENOB is calculated from: ENOB = (SINAD - 1.76) / 6.02 2nd and 3rd Harmonic Distortion This is the ratio of the RMS value of the 2nd and 3rd harmonic component respectively to the RMS value of the measured input signal. Signal-to-Noise Ratio (SNR) SNR is the measured RMS signal to RMS noise at a specified input and sampling frequency. The noise is the RMS sum of all of the spectral components except the fundamental and the first five harmonics. Full Power Input Bandwidth Full power bandwidth is the frequency at which the amplitude of the digitally reconstructed output has decreased 3dB below the amplitude of the input sine wave. The input sine wave has a peak-to-peak amplitude equal to the difference between the top reference voltage input and the bottom reference voltage input. The bandwidth given is measured at the specified sampling frequency. 12 HI5714 Die Characteristics DIE DIMENSIONS: 134 mils x 134 mils x 19 mils ±1 mil METALLIZATION: Type: AlSiCu Thickness: M1 - 8kÅ, M2 - 17kÅ SUBSTRATE POTENTIAL (POWERED UP): GND (0.0V) PASSIVATION: Type: Sandwich Passivation* Undoped Silicon Glass (USG) + Nitride Thickness: USG - 8kÅ, Nitride - 4.2kÅ Total 12.2kÅ + 2kÅ WORST CASE CURRENT DENSITY: 1.6 x 104 A/cm2 TRANSISTOR COUNT: 3714 DIE ATTACH: Silver Filled Epoxy Metallization Mask Layout HI5714 DO D1 D2 D3 OE VCC02 VRB OGND AGND VCC01 VCCA VCCD VIN DGND VRT CLK O/UF D7 D6 D5 D4 13 HI5714 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M24.3 (JEDEC MS-013-AD ISSUE C) 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 2.35 0.10 0.33 0.23 15.20 7.40 MAX 2.65 0.30 0.51 0.32 15.60 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0926 0.0040 0.013 0.0091 0.5985 0.2914 MAX 0.1043 0.0118 0.020 0.0125 0.6141 0.2992 A1 B C D E α µ A1 0.10(0.004) C e H h L N 0.05 BSC 0.394 0.010 0.016 24 0o 8o 0.419 0.029 0.050 1.27 BSC 10.00 0.25 0.40 24 0o 10.65 0.75 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14