HI5760_05

® HI5760 Data Sheet March 30, 2005 FN4320.8 10-Bit, 125/60MSPS, High Speed D/A Converter The HI5760 is a 10-bit, 125MSPS, high speed, low power, D/A converter which is implemented in an advanced CMOS process. Operating from a single +3V to +5V supply, the converter provides 20mA of full scale output current and includes edge-triggered CMOS input data latches. Low glitch energy and excellent frequency domain performance are achieved using a segmented current source architecture. For an equivalent performance dual version, see the HI5728. This device complements the HI5X60 family of high speed converters offered by Intersil, which includes 8, 10, 12, and 14-bit devices. Features • Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 125MSPS • Low Power . . . . . . . . . . . . . . . 165mW at 5V, 27mW at 3V • Power Down Mode. . . . . . . . . . 23mW at 5V, 10mW at 3V • Integral Linearity Error . . . . . . . . . . . . . . . . . . . . . . ±1 LSB • Adjustable Full Scale Output Current. . . . . 2mA to 20mA • SFDR to Nyquist at 5MHz Output . . . . . . . . . . . . . . 68dBc • Internal 1.2V Temperature Compensated Bandgap Voltage Reference • Single Power Supply from +5V to +3V • CMOS Compatible Inputs Ordering Information PART NUMBER HI5760BIB HI5760BIBZ (See Note) HI5760IA HI5760IAZ (See Note) HI5760/6IB HI5760/6IBZ (See Note) HI5760EVAL1 TEMP. RANGE (oC) -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 25 PACKAGE 28 Ld SOIC 28 Ld SOIC (Pb-free) PKG. NO. M28.3 M28.3 CLOCK SPEED 125MHz 125MHz • Excellent Spurious Free Dynamic Range • Pb-Free Available (RoHS Compliant) Applications • Cable Modems • Set Top Boxes • Wireless Communications • Direct Digital Frequency Synthesis • Signal Reconstruction • Test Instrumentation • High Resolution Imaging Systems • Arbitrary Waveform Generators 28 Ld TSSOP M28.173 125MHz 28 Ld TSSOP M28.173 125MHz (Pb-free) 28 Ld SOIC 28 Ld SOIC (Pb-free) M28.3 M28.3 60MHz 60MHz 125MHz Evaluation Platform * Add “-T” suffix for tape and reel. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinout HI5760 (SOIC, TSSOP) TOP VIEW D9 (MSB) 1 D8 2 D7 3 D6 4 D5 5 D4 6 D3 7 D2 8 D1 9 D0 (LSB) 10 NC 11 NC 12 NC 13 NC 14 28 CLK 27 DVDD 26 DCOM 25 NC 24 AVDD 23 NC 22 IOUTA 21 IOUTB 20 ACOM 19 COMP1 18 FSADJ 17 REFIO 16 REFLO 15 SLEEP 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HI5760 Typical Applications Circuit HI5760 NC D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (11-14, 25) D9 (MSB) (1) D8 (2) D7 (3) D6 (4) D5 (5) D4 (6) D3 (7) D2 (8) D1 (9) D0 (LSB) (10) CLK (28) 50Ω DCOM (26) FERRITE BEAD 10µF + 10µH DVDD (27) 0.1µF (21) IOUTB (23) NC (19) COMP1 (20) ACOM (24) AVDD 0.1µF FERRITE BEAD 10µH 0.1µF + +5V OR +3V (VDD ) 10µF (22) IOUTA 50Ω 50Ω D/A OUT (18) FSADJ RSET D/A OUT 2kΩ (17) REFIO 0.1µF ACOM (15) SLEEP (16) REFLO DCOM Functional Block Diagram IOUTA IOUTB (LSB) D0 D1 D2 D3 D4 D5 D6 D7 D8 (MSB) D9 UPPER 5-BIT DECODER 31 LATCH LATCH 36 SWITCH MATRIX 36 5 LSBs + 31 MSB SEGMENTS CASCODE CURRENT SOURCE CLK INT/EXT VOLTAGE REFERENCE BIAS GENERATION COMP1 INT/EXT REFERENCE SELECT AVDD ACOM DVDD DCOM REFLO REFIO FSADJ SLEEP 2 HI5760 Absolute Maximum Ratings Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . +5.5V Analog Supply Voltage AVDD to ACOM . . . . . . . . . . . . . . . . . +5.5V Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . -0.3V To + 0.3V Digital Input Voltages (D9-D0, CLK, SLEEP) . . . . . . DVDD + 0.3V Internal Reference Output Current . . . . . . . . . . . . . . . . . . . . . . . ±50µA Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD + 0.3V Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA Thermal Information Thermal Resistance (Typical, Note 1) θJA(oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Maximum Junction Temperature HI5760 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values HI5760 TA = -40oC TO 85oC PARAMETER SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL Differential Linearity Error, DNL Offset Error, IOS Offset Drift Coefficient Full Scale Gain Error, FSE TEST CONDITIONS MIN TYP MAX UNITS 10 “Best Fit” Straight Line (Note 7) (Note 7) (Note 7) (Note 7) With External Reference (Notes 2, 7) With Internal Reference (Notes 2, 7) -1 -0.5 -0.025 -10 -10 2 (Note 3) -0.3 ±0.5 ±0.25 +1 +0.5 +0.025 Bits LSB LSB % FSR ppm FSR/oC % FSR % FSR ppm FSR/oC ppm FSR/oC mA V 0.1 ±2 ±1 ±50 ±100 - +10 +10 20 1.25 Full Scale Gain Drift With External Reference (Note 7) With Internal Reference (Note 7) Full Scale Output Current, IFS Output Voltage Compliance Range DYNAMIC CHARACTERISTICS Maximum Clock Rate, fCLK Output Settling Time, (tSETT) (Note 3) 0.2% (±1 LSB, equivalent to 9 Bits) (Note 7) 0.1% (±1/2 LSB, equivalent to 10 Bits) (Note 7) Singlet Glitch Area (Peak Glitch) Output Rise Time Output Fall Time Output Capacitance Output Noise IOUTFS = 20mA IOUTFS = 2mA RL = 25Ω (Note 7) Full Scale Step Full Scale Step 125 - 20 35 5 1.0 1.5 10 50 30 - MHz ns ns pV•s ns ns pF pA/ √Hz pA/ √Hz 3 HI5760 Electrical Specifications AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued) HI5760 TA = -40oC TO 85oC PARAMETER AC CHARACTERISTICS - HI5760BIB, HI5760IA - 125MHz Spurious Free Dynamic Range, SFDR Within a Window fCLK = 125MSPS, fOUT = 32.9MHz, 10MHz Span (Notes 4, 7) fCLK = 100MSPS, fOUT = 5.04MHz, 4MHz Span (Notes 4, 7) fCLK = 60MSPS, fOUT = 10.1MHz, 10MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 5.02MHz, 2MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 1.00MHz, 2MHz Span (Notes 4, 7) Total Harmonic Distortion (THD) to Nyquist fCLK = 100MSPS, fOUT = 2.00MHz (Notes 4, 7) fCLK = 50MSPS, fOUT = 2.00MHz (Notes 4, 7) fCLK = 50MSPS, fOUT = 1.00MHz (Notes 4, 7) Spurious Free Dynamic Range, SFDR to Nyquist fCLK = 125MSPS, fOUT = 32.9MHz, 62.5MHz Span (Notes 4, 7) fCLK = 125MSPS, fOUT = 10.1MHz, 62.5MHz Span (Notes 4, 7) fCLK = 100MSPS, fOUT = 40.4MHz, 50MHz Span (Notes 4, 7) fCLK = 100MSPS, fOUT = 20.2MHz, 50MHz Span (Notes 4, 7) fCLK = 100MSPS, fOUT = 5.04MHz, 50MHz Span (Notes 4, 7) fCLK = 100MSPS, fOUT = 2.51MHz, 50MHz Span (Notes 4, 7) fCLK = 60MSPS, fOUT = 10.1MHz, 30MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 20.2MHz, 25MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 5.02MHz, 25MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 2.51MHz, 25MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 1.00MHz, 25MHz Span (Notes 4, 7) AC CHARACTERISTICS - HI5760/6IB, HI5760/6IA - 60MHz Spurious Free Dynamic Range, SFDR Within a Window fCLK = 60MSPS, fOUT = 10.1MHz, 10MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 5.02MHz, 2MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 1.00MHz, 2MHz Span (Notes 4, 7) Total Harmonic Distortion (THD) to Nyquist Spurious Free Dynamic Range, SFDR to Nyquist fCLK = 50MSPS, fOUT = 2.00MHz (Notes 4, 7) fCLK = 50MSPS, fOUT = 1.00MHz (Notes 4, 7) fCLK = 60MSPS, fOUT = 20.2MHz, 30MHz Span (Notes 4, 7) fCLK = 60MSPS, fOUT = 10.1MHz, 30MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 20.2MHz, 25MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 5.02MHz, 25MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 2.51MHz, 25MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 1.00MHz, 25MHz Span (Notes 4, 7) fCLK = 25MSPS, fOUT = 5.02MHz, 25MHz Span (Notes 4, 7) VOLTAGE REFERENCE Internal Reference Voltage, VFSADJ Internal Reference Voltage Drift Internal Reference Output Current Sink/Source Capability Reference Input Impedance Reference Input Multiplying Bandwidth (Note 7) Pin 18 Voltage with Internal Reference 1.04 1.16 ±60 0.1 1 1.4 1.28 V ppm/oC TEST CONDITIONS MIN TYP MAX UNITS - 75 76 75 76 78 71 71 76 54 64 52 60 68 74 63 55 68 73 73 - dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc - 75 76 78 71 76 56 63 55 68 73 73 71 - dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc µA MΩ MHz 4 HI5760 Electrical Specifications AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued) HI5760 TA = -40oC TO 85oC PARAMETER DIGITAL INPUTS D9-D0, CLK (Note 3) (Note 3) (Note 3) (Note 3) 3.5 2.1 -10 -10 5 3 0 0 5 1.3 0.9 +10 +10 V V V V µA µA pF TEST CONDITIONS MIN TYP MAX UNITS Input Logic High Voltage with 5V Supply, VIH Input Logic High Voltage with 3V Supply, VIH Input Logic Low Voltage with 5V Supply, VIL Input Logic Low Voltage with 3V Supply, VIL Input Logic Current, IIH Input Logic Current, IIL Digital Input Capacitance, CIN TIMING CHARACTERISTICS Data Setup Time, tSU Data Hold Time, tHLD Propagation Delay Time, tPD CLK Pulse Width, tPW1 , tPW2 See Figure 41 (Note 3) See Figure 41 (Note 3) See Figure 41 See Figure 41 (Note 3) 3 3 4 1 - - ns ns ns ns POWER SUPPLY CHARACTERISTICS AVDD Power Supply DVDD Power Supply Analog Supply Current (IAVDD) (Note 8) (Note 8) (5V or 3V, IOUTFS = 20mA) (5V or 3V, IOUTFS = 2mA) Digital Supply Current (IDVDD) (5V, IOUTFS = Don’t Care) (Note 5) (3V, IOUTFS = Don’t Care) (Note 5) Supply Current (IAVDD) Sleep Mode Power Dissipation (5V or 3V, IOUTFS = Don’t Care) (5V, IOUTFS = 20mA) (Note 6) (5V, IOUTFS = 2mA) (Note 6) (5V, IOUTFS = 20mA) (Note 9) (3.3V, IOUTFS = 20mA) (Note 9) (3V, IOUTFS = 20mA) (Note 6) (3V, IOUTFS = 20mA) (Note 9) (3V, IOUTFS = 2mA) (Note 6) Power Supply Rejection NOTES: 2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625µA). Ideally the ratio should be 31.969. 3. Parameter guaranteed by design or characterization and not production tested. 4. Spectral measurements made with differential coupled transformer. 5. Measured with the clock at 50MSPS and the output frequency at 1MHz. 6. Measured with the clock at 100MSPS and the output frequency at 40MHz. 7. See ‘Definition of Specifications’. 8. It is recommended that the output current be reduced to 12mA or less to maintain optimum performance for operation below 3V. DVDD and AVDD do not have to be equal. 9. Measured with the clock at 60MSPS and the output frequency at 10MHz. Single Supply (Note 7) 2.7 2.7 -0.2 5.0 5.0 23 4 3 1.5 1.6 165 70 150 75 85 67 27 5.5 5.5 30 5 3 +0.2 V V mA mA mA mA mA mW mW mW mW mW mW mW % FSR/V 5 HI5760 Typical Performance Curves, 5V Power Supply 80 75 -6dBFS SFDR (dBc) 0dBFS 65 60 64 55 50 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 OUTPUT FREQUENCY (MHz) -12dBFS 62 60 1 2 3 4 5 6 7 8 9 10 OUTPUT FREQUENCY (MHz) 0dBFS SFDR (dBc) 70 76 74 72 -6dBFS 70 68 66 -12dBFS FIGURE 1. SFDR vs fOUT, CLOCK = 5MSPS FIGURE 2. SFDR vs fOUT, CLOCK = 25MSPS 80 0dBFS 75 SFDR (dBc) 75 70 65 60 55 0dBFS -6dBFS SFDR (dBc) 70 -6dBFS -12dBFS 65 -12dBFS 60 50 45 0 2 4 6 8 10 12 14 16 18 20 OUTPUT FREQUENCY (MHz) 55 0 5 10 15 20 25 30 35 40 45 OUTPUT FREQUENCY (MHz) FIGURE 3. SFDR vs fOUT, CLOCK = 50MSPS FIGURE 4. SFDR vs fOUT, CLOCK = 100MSPS 75 80 25MSPS 70 65 SFDR (dBc) 60 55 50 0dBFS 50 45 0 5 10 15 20 25 30 35 40 45 50 45 -25 -12dBFS 6dBFS SFDR (dBc) 75 70 65 125MSPS 60 55 50MSPS 100MSPS -20 -15 -10 -5 0 OUTPUT FREQUENCY (MHz) AMPLITUDE (dBFS) FIGURE 5. SFDR vs fOUT, CLOCK = 125MSPS FIGURE 6. SFDR vs AMPLITUDE, fCLK / fOUT = 10 6 HI5760 Typical Performance Curves, 5V Power Supply 80 25MSPS 75 50MSPS 70 SFDR (dBc) 100MSPS SFDR (dBc) 65 60 125MSPS 55 50 45 40 -25 45 40 -25 125MSPS (16.9/18.1MHz) -20 -15 -10 -5 0 65 60 55 50 100MSPS (13.5/14.5MHz) 50MSPS (6.75/7.25MHz) 70 (Continued) 75 25MSPS (3.38/3.63MHz) -20 -15 -10 -5 0 AMPLITUDE (dBFS) AMPLITUDE (TOTAL PEAK POWER OF COMBINED TONES) (dBFS) FIGURE 7. SFDR vs AMPLITUDE, fCLK / fOUT = 5 FIGURE 8. SFDR vs AMPLITUDE OF TWO TONES, fCLK / fOUT = 7 75 70 65 SFDR (dBc) 60 55 50 45 40 2.5MHz 75 70 10MHz 65 20MHz 40MHz SFDR (dBc) 60 55 50 0dBFS SINGLE 45 2 4 6 8 10 12 IOUT (mA) 14 16 18 20 0 5 10 15 20 25 30 35 40 OUTPUT FREQUENCY (MHz) -6dBFS DIFF 0dBFS DIFF -6dBFS SINGLE FIGURE 9. SFDR vs IOUT, CLOCK = 100MSPS FIGURE 10. DIFFERENTIAL vs SINGLE-ENDED, CLOCK = 100MSPS 80 2.5MHz 75 70 10.1MHz SFDR (dBc) AMP (dB) Amp (dB) 65 60 55 50 45 40 -40 -20 0 20 40 40.4MHz -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 -70 -70 -80 -80 -90 -90 -100 -100 80 -110 -110 0 0 5MHz/DIV.. 5MHz/DIV. Frequency (MHz) FREQUENCY (MHz) 50 fCLK = 100MSPS = 100MSPS = 9.95MHz f Fout =OUT 9.95MHz AMPLITUDE = 0dBFS Amplitude = 0dBFS SFDR = 64dBc SFDR = 64dBc 14dB 14dB External Analyzer Attenuation EXTERNAL ANALYZER ATTENUATION 60 TEMPERATURE (oC) FIGURE 11. SFDR vs TEMPERATURE, CLOCK = 100MSPS FIGURE 12. SINGLE TONE SFDR 7 HI5760 Typical Performance Curves, 5V Power Supply -20 -20 -30 -30 -40 -40 -50 -50 AMP (dB) Amp (dB) -60 -60 -70 -70 -80 -80 -90 -90 -100 -100 -110 -110 0 0 5MHz / DIV. 5MHz/DIV. Frequency (MHz) FREQUENCY (MHz) 50 50 Fclk = 100MSPS fCLK = 100MSPS Fout = 13.5/14.5MHz fOUT = 13.5/14.5MHz Combined Peak Amplitude =PEAK COMBINED 0dBFS MTPR = 62.9dBc AMPLITUDE = 0dBFS 14dB External Analyzer = 62.9dBc SFDR Attenuation 14dB EXTERNAL ANALYZER ATTENUATION (Continued) -10 -20 -30 -40 AMP (dB) -50 -60 -70 -80 -90 -100 0.5 fCLK = 100MSPS fOUT = 3.8,4.4,5.6,6.2MHz COMBINED PEAK AMPLITUDE = 0dBFS SFDR = 71.4dBc (IN A WINDOW) 1.45MHz / DIV. 15 FIGURE 13. TWO TONE, CLOCK = 100MSPS FIGURE 14. FOUR-TONE, CLOCK = 100MSPS -20 -30 -40 -50 AMP (dB) -60 -70 -80 -90 -100 -110 0.5 1.95MHz/DIV. FREQUENCY (MHz) 20 fCLK = 100MSPS fOUT = 2.6,3.2,3.8,4.4,5.6,6.2,6.8MHz COMBINED PEAK AMPLITUDE = 0dBFS SFDR = 67dBc (IN A WINDOW) AMP (dB) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0.5 950kHz/DIV. FREQUENCY (MHz) 10 fCLK = 50MSPS fOUT = 1.9,2.2,2.8,3.1MHz COMBINED PEAK AMPLITUDE = 0dBFS SFDR = 73.6dBc (IN A WINDOW) FIGURE 15. EIGHT-TONE, CLOCK = 100MSPS FIGURE 16. FOUR-TONE, CLOCK = 50MSPS 0.4 0.4 0.2 0.2 LSB LSB 0 0 -0.2 -0.2 -0.4 0 200 400 CODE 600 800 1000 -0.4 0 200 400 CODE 600 800 1000 FIGURE 17. DIFFERENTIAL NONLINEARITY FIGURE 18. INTEGRAL NONLINEARITY 8 HI5760 Typical Performance Curves, 5V Power Supply 160 155 150 145 POWER (mW) 140 135 130 125 120 115 110 105 0 20 40 60 80 100 120 (Continued) CLOCK RATE (MSPS) FIGURE 19. POWER vs CLOCK RATE, fCLK / fOUT = 10, IOUT = 20mA Typical Performance Curves, 3V Power Supply 80 75 70 0dBFS 65 60 -12dBFS 55 60 50 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 1 2 3 4 5 6 7 8 9 10 SFDR (dBc) 70 -12dBFS 65 -6dBFS 75 SFDR (dBc) -6dBFS 80 0dBFS OUTPUT FREQUENCY (MHz) OUTPUT FREQUENCY (MHz) FIGURE 20. SFDR vs fOUT, CLOCK = 5MSPS 80 75 70 SFDR (dBc) 65 60 55 50 0 2 4 6 8 10 12 14 16 18 20 OUTPUT FREQUENCY (MHz) -6dBFS SFDR (dBc) -12dBFS 80 FIGURE 21. SFDR vs fOUT, CLOCK = 25MSPS 0dBFS 75 70 65 -12dBFS 60 55 50 45 -6dBFS 0dBFS 0 5 10 15 20 25 30 35 40 45 OUTPUT FREQUENCY (MHz) FIGURE 22. SFDR vs fOUT, CLOCK = 50MSPS FIGURE 23. SFDR vs fOUT, CLOCK = 100MSPS 9 HI5760 Typical Performance Curves, 3V Power Supply 80 0dBFS 75 70 SFDR (dBc) 65 60 55 50 45 SFDR (dBc) -6dBFS -12dBFS 75 50MSPS 70 100MSPS 65 125MSPS 60 55 50 0 5 10 15 20 25 30 35 40 45 50 45 -25 (Continued) 80 25MSPS -20 -15 -10 -5 0 OUTPUT FREQUENCY (MHz) AMPLITUDE (dBFS) FIGURE 24. SFDR vs fOUT, CLOCK = 125MSPS FIGURE 25. SFDR vs AMPLITUDE, fCLK / fOUT = 10 80 25MSPS 75 70 SFDR (dBc) SFDR (dBc) 65 60 55 50 45 40 -25 -20 -15 -10 -5 0 25 D AN 75 70 65 50MSPS 100MSPS 50 MS PS 25MSPS (3.38/3.63MHz) 60 55 50 45 40 -25 50MSPS (6.75/7.25MHz) 100MSPS (13.5/14.5MHz) 125MSPS (16.9/18.1MHz) -20 -15 -10 -5 0 5MSPS 125MSPS AMPLITUDE (dBFS) AMPLITUDE (dBFS) FIGURE 26. SFDR vs AMPLITUDE, fCLK / fOUT = 5 FIGURE 27. SFDR vs AMPLITUDE OF TWO TONES, fCLK/fOUT = 7 80 2.5MHz 75 70 SFDR (dBc) 65 60 55 50 45 40MHz 10MHz 20MHz SFDR (dBc) 80 75 70 65 60 55 50 0dBFS SINGLE 2 4 6 8 10 12 14 16 18 20 45 0 5 10 15 20 25 30 35 40 -6dBFS SINGLE -6dBFS DIFF 0dBFS DIFF IOUT (MA) OUTPUT FREQUENCY (MHz) FIGURE 28. SFDR vs IOUT, CLOCK = 100MSPS FIGURE 29. DIFFERENTIAL vs SINGLE-ENDED, CLOCK = 100MSPS 10 HI5760 Typical Performance Curves, 3V Power Supply 80 75 70 10.1MHz SFDR (dBc) AMP (dB) 65 60 55 50 40.4MHz 45 40 -40 -20 0 20 40 60 80 -40 -50 -60 -70 -80 -90 -100 -110 0 5MHz/DIV. FREQUENCY (MHz) 50 2.5MHz (Continued) -10 -20 -30 fCLK = 100MSPS fOUT = 9.95MHz AMPLITUDE = 0dBFS SFDR = 63dBc 14dB EXTERNAL ANALYZER ATTENUATION TEMPERATURE (oC) FIGURE 30. SFDR vs TEMPERATURE, CLOCK = 100MSPS FIGURE 31. SINGLE TONE SFDR -20 -30 -40 -50 AMP (dB) -60 -70 -80 -90 -100 -110 0 5MHz/DIV. FREQUENCY (MHz) 50 fCLK = 100MSPS fOUT = 13.5/14.5MHz COMBINED PEAK AMPLITUDE = 0dBFS SFDR = 61.5dBc 14dB EXTERNAL ANALYZER ATTENUATION -10 -20 -30 -40 AMP (dB) -50 -60 -70 -80 -90 -100 0.5 1.45MHz/DIV. FREQUENCY (MHz) 15 fCLK = 100MSPS fOUT = 3.8,4.4,5.6,6.2MHz COMBINED PEAK AMPLITUDE = 0dBFS SFDR = 70.6dBc (IN A WINDOW) FIGURE 32. TWO-TONE, CLOCK = 100MSPS FIGURE 33. FOUR-TONE, CLOCK = 100MSPS -20 -30 -40 -50 AMP (dB) -60 -70 -80 -90 -100 -110 0.5 1.95MHz/DIV. FREQUENCY (MHz) 20 fCLK = 100MSPS fOUT = 2.6, 3.2, 3.8, 4.4, 5.6, 6.2, 6.8MHz COMBINED PEAK AMPLITUDE = 0dBFS SFDR = 67.4dBc (IN A WINDOW) -10 -20 -30 -40 AMP (dB) -50 -60 -70 -80 -90 -100 0 950kHz/DIV. FREQUENCY (MHz) 10 fCLK = 50MSPS fOUT = 1.9, 2.2, 2.8, 3.1MHz COMBINED PEAK AMPLITUDE = 0dBFS SFDR = 74.2dBc (IN A WINDOW) FIGURE 34. EIGHT-TONE, CLOCK = 100MSPS FIGURE 35. FOUR-TONE, CLOCK = 50MSPS 11 HI5760 Typical Performance Curves, 3V Power Supply 0.4 (Continued) 0.4 0.2 LSB 0.2 0 LSB 0 200 400 CODE 600 800 1000 0 -0.2 -0.2 -0.4 -0.4 0 200 400 CODE 600 800 1000 FIGURE 36. DIFFERENTIAL NONLINEARITY FIGURE 37. INTEGRAL NONLINEARITY 76 74 72 POWER (mW) 70 68 66 64 62 60 0 20 40 60 80 100 120 CLOCK RATE (MSPS) FIGURE 38. POWER vs CLOCK RATE, fCLK / fOUT = 10, IOUT = 20mA 12 HI5760 Timing Diagrams CLK 50% D9-D0 V 1/ LSB ERROR BAND 2 GLITCH AREA = 1 / 2 (H x W) HEIGHT (H) IOUT WIDTH (W) tSETT tPD t(ps) FIGURE 39. OUTPUT SETTLING TIME DIAGRAM FIGURE 40. PEAK GLITCH AREA (SINGLET) MEASUREMENT METHOD tPW1 tPW2 CLK 50% tSU tHLD D9-D0 tSU tHLD tSU tHLD tPD tSETT IOUT tPD tSETT tPD tSETT FIGURE 41. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM 13 HI5760 Definition of Specifications Integral Linearity Error, INL, is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve. Differential Linearity Error, DNL, is the measure of the step size output deviation from code to code. Ideally the step size should be 1 LSB. A DNL specification of 1 LSB or less guarantees monotonicity. Output Settling Time, is the time required for the output voltage to settle to within a specified error band measured from the beginning of the output transition. In the case of the HI5760, the measurement was done by switching from code 0 to 256, or quarter scale. Termination impedance was 25Ω due to the parallel resistance of the output 50Ω and the oscilloscope’s 50Ω input. This also aids the ability to resolve the specified error band without overdriving the oscilloscope. Singlet Glitch Area, is the switching transient appearing on the output during a code transition. It is measured as the area under the overshoot portion of the curve and is expressed as a Volt-Time specification. Full Scale Gain Error , is the error from an ideal ratio of 32 between the output current and the full scale adjust current (through RSET). Full Scale Gain Drift, is measured by setting the data inputs to all ones and measuring the output voltage through a known resistance as the temperature is varied from TMIN to TMAX. It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX. The units are ppm of FSR (full scale range) per degree C. Total Harmonic Distortion, THD, is the ratio of the DAC output fundamental to the RMS sum of the first five harmonics. Spurious Free Dynamic Range, SFDR, is the amplitude difference from the fundamental to the largest harmonically or non-harmonically related spur within the specified window. Output Voltage Compliance Range, is the voltage limit imposed on the output. The output impedance load should be chosen such that the voltage developed does not violate the compliance range. Offset Error, is measured by setting the data inputs to all zeros and measuring the output voltage through a known resistance. Offset error is defined as the maximum deviation of the output current from a value of 0mA. Offset Drift, is measured by setting the data inputs to all zeros and measuring the output voltage through a known resistance as the temperature is varied from TMIN to TMAX. It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX. The units are ppm of FSR (full scale range) per degree C. Power Supply Rejection, is measured using a single power supply. Its nominal +5V is varied ±10% and the change in the DAC full scale output is noted. Reference Input Multiplying Bandwidth, is defined as the 3dB bandwidth of the voltage reference input. It is measured by using a sinusoidal waveform as the external reference with the digital inputs set to all 1s. The frequency is increased until the amplitude of the output waveform is 0.707 of its original value. Internal Reference Voltage Drift, is defined as the maximum deviation from the value measured at room temperature to the value measured at either Tmin or Tmax. The units are ppm per degree C. Detailed Description The HI5760 is a 10-bit, current out, CMOS, digital to analog converter. Its maximum update rate is 125MSPS and can be powered by either single or dual power supplies in the recommended range of +3V to +5V. It consumes less than 165mW of power when using a +5V supply with the data switching at 100MSPS. The architecture is based on a segmented current source arrangement that reduces glitch by reducing the amount of current switching at any one time. The five MSBs are represented by 31 major current sources of equivalent current. The five LSBs are comprised of binary weighted current sources. Consider an input waveform to the converter which is ramped through all the codes from 0 to 1023. The five LSB current sources would begin to count up. When they reached the all high state (decimal value of 31) and needed to count to the next code, they would all turn off and the first major current source would turn on. To continue counting upward, the 5 LSBs would count up another 31 codes, and then the next major current source would turn on and the five LSBs would all turn off. The process of the single, equivalent, major current source turning on and the five LSBs turning off each time the converter reaches another 31 codes greatly reduces the glitch at any one switching point. In previous architectures that contained all binary weighted current sources or a binary weighted resistor ladder, the converter might have a substantially larger amount of current turning on and off at certain, worst-case transition points such as mid-scale and quarter scale transitions. By greatly reducing the amount of current switching at certain ‘major’ transitions, the overall glitch of the converter is dramatically reduced, improving settling times and transient problems. 14 HI5760 Digital Inputs and Termination The HI5760 digital inputs are guaranteed to CMOS levels. However, TTL compatibility can be achieved by lowering the supply voltage to 3V due to the digital threshold of the input buffer being approximately half of the supply voltage. The internal register is updated on the rising edge of the clock. To minimize reflections, proper termination should be implemented. If the lines driving the clock and the digital inputs are 50Ω lines, then 50Ω termination resistors should be placed as close to the converter inputs as possible to the digital ground plane (if separate grounds are used). If the full scale output current is set to 20mA by using the internal voltage reference (1.16V) and a 1.86kΩ RSET resistor, then the input coding to output current will resemble the following: TABLE 1. INPUT CODING vs OUTPUT CURRENT INPUT CODE (D9-D0) 11111 11111 10000 00000 00000 00000 IOUTA (mA) 20 10 0 IOUTB (mA) 0 10 20 Ground Plane(s) If separate digital and analog ground planes are used, then all of the digital functions of the device and their corresponding components should be over the digital ground plane and terminated to the digital ground plane. The same is true for the analog components and the analog ground plane. The converter will function properly with a single ground plane, as the Evaluation Board is configured in this matter. Refer to the Application Note on the HI5760 Evaluation Board for further discussion of the ground plane(s) upon availability. Outputs IOUTA and IOUTB are complementary current outputs. The sum of the two currents is always equal to the full scale output current minus one LSB. If single ended use is desired, a load resistor can be used to convert the output current to a voltage. It is recommended that the unused output be either grounded or equally terminated. The voltage developed at the output must not violate the output voltage compliance range of -0.3V to 1.25V. RLOAD should be chosen so that the desired output voltage is produced in conjunction with the output full scale current, which is described above in the ‘Reference’ section. If a known line impedance is to be driven, then the output load resistor should be chosen to match this impedance. The output voltage equation is: VOUT = IOUT X RLOAD These outputs can be used in a differential-to-single-ended arrangement to achieve better harmonic rejection. The SFDR measurements in this data sheet were performed with a 1:1 transformer on the output of the DAC (see Figure 1). With the center tap grounded, the output swing of pins 21 and 22 will be biased at zero volts. It is important to note here that the negative voltage output compliance range limit is -300mV, imposing a maximum of 600mVP-P amplitude with this configuration. The loading as shown in Figure 1 will result in a 500mV signal at the output of the transformer if the full scale output current of the DAC is set to 20mA. Noise Reduction To minimize power supply noise, 0.1µF capacitors should be placed as close as possible to the converter’s power supply pins, AVDD and DVDD . Also, should the layout be designed using separate digital and analog ground planes, these capacitors should be terminated to the digital ground for DVDD and to the analog ground for AVDD. Additional filtering of the power supplies on the board is recommended. See the Application Note on the HI5760 Evaluation Board for more information upon availability. Voltage Reference The internal voltage reference of the device has a nominal value of +1.2V with a ± 60 ppm / oC drift coefficient over the full temperature range of the converter. It is recommended that a 0.1µF capacitor be placed as close as possible to the REFIO pin, connected to the analog ground. The REFLO pin (16) selects the reference. The internal reference can be selected if pin 16 is tied low (ground). If an external reference is desired, then pin 16 should be tied high (to the analog supply voltage) and the external reference driven into REFIO, pin 17. The full scale output current of the converter is a function of the voltage reference used and the value of RSET. IOUT should be within the 2mA to 20mA range, through operation below 2mA is possible, with performance degradation. If the internal reference is used, VFSADJ will equal approximately 1.16V (pin 18). If an external reference is used, VFSADJ will equal the external reference. The calculation for IOUT (Full Scale) is: IOUT (Full Scale) = (VFSADJ/RSET)x 32 50Ω PIN 21 PIN 22 HI5760 IOUTB 100Ω IOUTA 50Ω VOUT = (2 x IOUT x REQ)V 50Ω FIGURE 42. VOUT = 2 x IOUT x REQ, where REQ is ~12.5Ω 15 HI5760 Pin Descriptions PIN NO. 1-10 PIN NAME D9 (MSB) Through D0 (LSB) NC SLEEP PIN DESCRIPTION Digital Data Bit 9 (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit). 11-14 15 No Connect. Recommend ground. Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep pin has internal 20µA active pulldown current. Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal reference. Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is enabled. Use 0.1µF cap to ground when internal reference is enabled. Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output Current = 32 x VFSADJ/RSET. For use in reducing bandwidth/noise. Recommended: connect 0.1µF to AVDD . Analog Ground. The complimentary current output of the device. Full scale output current is achieved when all input bits are set to binary 0. Current output of the device. Full scale output current is achieved when all input bits are set to binary 1. Internally connected to ACOM via a resistor. Recommend leave disconnected. Adding a capacitor to ACOM for upward compatibility is valid. Grounding to ACOM is valid. (For upward compatibility to 12-bit and 14-bit devices, pin 23 needs the ability to have a 0.1µF capacitor to ACOM.) Analog Supply (+3V to +5V). No Connect. (For upward compatibility to 12 and 14b devices, pin 25 needs to be grounded to ACOM.) Digital Ground. Digital Supply (+3V to +5V). Input for clock. Positive edge of clock latches data. 16 REFLO 17 REFIO 18 FSADJ 19 20 21 COMP1 ACOM IOUTB 22 23 IOUTA NC 24 25 26 27 28 AVDD NC DCOM DVDD CLK 16 HI5760 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M28.3 (JEDEC MS-013-AE ISSUE C) 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 L MILLIMETERS MIN 2.35 0.10 0.33 0.23 17.70 7.40 MAX 2.65 0.30 0.51 0.32 18.10 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0926 0.0040 0.013 0.0091 0.6969 0.2914 MAX 0.1043 0.0118 0.0200 0.0125 0.7125 0.2992 B C D E α A1 0.10(0.004) C e H h L N 0.05 BSC 0.394 0.01 0.016 28 0o 8o 0.419 0.029 0.050 1.27 BSC 10.00 0.25 0.40 28 0o 10.65 0.75 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 17 HI5760 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA E E1 -B1 2 3 L 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 GAUGE PLANE 0.25(0.010) M BM M28.173 28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.378 0.169 MAX 0.047 0.006 0.051 0.0118 0.0079 0.386 0.177 MILLIMETERS MIN 0.05 0.80 0.19 0.09 9.60 4.30 MAX 1.20 0.15 1.05 0.30 0.20 9.80 4.50 NOTES 9 3 4 6 7 8o Rev. 0 6/98 α A1 0.10(0.004) A2 c E1 e E L N e b 0.10(0.004) M C AM BS 0.026 BSC 0.246 0.0177 28 0o 8o 0.256 0.0295 0.65 BSC 6.25 0.45 28 0o 6.50 0.75 NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AE, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18