HI5813

HI5813 UCT PROD CT OLETE UTE PRODU OB S BSTIT LE SU I5812 Data Sheet H POSSIB TM May 2001 File Number 3634.3 itle I581 bjec MO .3V, cros nd, -Bit, mpli A/D nver th erna rack d ld) utho ) eyw s tersi rpor on, ico ucto /D, C, sh, nver , bit, le dem sesta CMOS 3.3V, 30 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold The HI5813 is a 3.3V, very low power, 12-bit, successive approximation analog-to-digital converter. It can operate from a single 3V to 6V supply and typically draws a maximum of 1.0mA (at 25oC) when operating at 3.3V. The HI5813 features a built-in track and hold. The conversion time is as low as 25µs with a 3.3V supply. The twelve data outputs feature full high speed CMOS three-state bus driver capability, and are latched and held through a full conversion cycle. The output is user selectable, i.e., 12-bit, 8-bit (MSBs), and/or 4-bit (LSBs). A data ready flag and conversion start input complete the digital interface. Features • Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30µs • Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . . 40 kSPS • Built-In Track and Hold • Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +3.3V • Maximum Power Consumption at 25oC. . . . . . . . . . 3.3mW Applications • Remote Low Power Data Acquisition Systems • Battery Operated Systems • Pen Based PC Handheld Scanners • DSP Modems • General Purpose DSP Front End • µP Controlled Measurement Systems Part Number Information PART NUMBER HI5813KIB INL (LSB) (MAX OVER TEMP.) ±2.5 TEMP. RANGE (oC) PACKAGE PKG. NO. M24.3 • PCMCIA Type II Compliant • PC Based Industrial Controls/DAQ Systems -40 to 85 24 Ld SOIC Pinout HI5813 (SOIC) TOP VIEW DRDY (LSB) D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 VDD 23 OEL 22 CLK 21 STRT 20 VREF 19 VREF+ 18 VIN 17 VAA + 16 VAA15 OEM 14 D11 (MSB) 13 D10 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. | Copyright © Intersil Americas Inc. 2001 HI5813 Functional Block Diagram STRT VDD VSS VIN CONTROL AND TIMING 32C VREF+ OEM 16C D11 (MSB) 50Ω SUBSTRATE 8C D10 4C 2C VAA+ C VAA64C 63 32C D7 16C 8C 4C 2C C D3 C D2 D1 VREF D0 (LSB) OEL 12-BIT SUCCESSIVE APPROXIMATION REGISTER 12-BIT EDGE TRIGGERED “D” LATCHES D8 D9 CLOCK CLK DRDY TO INTERNAL LOGIC D6 D5 D4 P1 2 HI5813 Absolute Maximum Ratings Supply Voltage VDD to VSS . . . . . . . . . . . . . . . . . . . . (VSS -0.5V) < VDD < +6.5V VAA+ to VAA- . . . . . . . . . . . . . . . . . . . (VSS -0.5V) to (VSS +6.5V) VAA+ to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V Analog and Reference Inputs VIN , VREF+, VREF-. . . . . . . . . (VSS -0.3V) < VINA < (VDD +0.3V) Digital I/O Pins . . . . . . . . . . . . . . . (VSS -0.3V) < VI/O < (VDD +0.3V) Thermal Information Thermal Resistance (Typical, Note 1) θJA ( oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65οC to 150oC Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications VDD = VAA+ = VREF+ = 3.3V, VSS = VAA - = VREF - = GND, CLK = 500kHz, Unless Otherwise Specified 25oC -40oC TO 85oC MAX MIN MAX UNITS PARAMETER ACCURACY Resolution Integral Linearity Error, INL (End Point) Differential Linearity Error, DNL Gain Error, FSE (Adjustable to Zero) Offset Error, VOS (Adjustable to Zero) DYNAMIC CHARACTERISTICS Signal to Noise Ratio, SINAD RMS Signal RMS Noise + Distortion Signal to Noise Ratio, SNR RMS Signal RMS Noise Total Harmonic Distortion, THD Spurious Free Dynamic Range, SFDR ANALOG INPUT Input Current, Dynamic Input Current, Static Input Bandwidth -3dB Reference Input Current Input Series Resistance, RS Input Capacitance, C SAMPLE Input Capacitance, C HOLD DIGITAL INPUTS OEL, OEM, STRT High-Level Input Voltage, VIH Low-Level Input Voltage, VIL TEST CONDITIONS MIN TYP 12 - - ±2.5 ±2.0 ±2.0 ±2.5 12 - ±2.5 ±2.0 ±2.0 ±2.5 Bits LSB LSB LSB LSB fS = 500kHz, fIN = 1kHz - 63.9 - - - dB fS = 500kHz, fIN = 1kHz - 65.1 - - - dB fS = 750kHz, fIN = 1kHz fS = 500kHz, fIN = 1kHz - -70.8 71.8 - - - dBc dB At VIN = VREF+, 0V Conversion Stopped - ±50 ±0.4 1 160 420 380 20 ±100 ±10 - - ±100 ±10 - µA µA MHz µA W pF pF In Series with Input CSAMPLE During Sample State During Hold State - 2.4 - - 0.8 2.4 - 0.8 V V 3 HI5813 Electrical Specifications VDD = VAA+ = VREF+ = 3.3V, VSS = VAA - = VREF - = GND, CLK = 500kHz, Unless Otherwise Specified (Continued) 25oC PARAMETER Input Leakage Current, IIL Input Capacitance, C IN DIGITAL OUTPUTS High-Level Output Voltage, VOH Low-Level Output Voltage, VOL Three-State Leakage, IOZ Output Capacitance, COUT TIMING Conversion Time (tCONV + tACQ) (Includes Acquisition Time) Clock Frequency Clock Pulse Width, tLOW, tHIGH Aperture Delay, tDAPR Clock to Data Ready Delay, tD1DRDY Clock to Data Ready Delay, tD2DRDY Start Removal Time, tRSTRT Start Setup Time, tSU STRT Start Pulse Width, tWSTRT Start to Data Ready Delay, tD3 DRDY Output Enable Delay, tEN Output Disabled Delay, tDIS POWER SUPPLY CHARACTERISTICS Supply Current, IDD + IAA NOTE: 2. Parameter guaranteed by design or characterization, not production tested. 0.5 1 2.5 mA (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) 30 0.05 100 75 85 35 180 180 30 60 15 110 65 95 0.75 50 210 220 25 130 75 110 30 0.05 100 75 30 0.75 70 240 250 25 160 80 130 µs MHz ns ns ns ns ns ns ns ns ns ns ISOURCE = -400µ A ISINK = 1.6mA Except DRDY, VOUT = 0V, 3.3V Except DRDY 2.6 20 0.4 ±10 2.6 0.4 ±10 V V µA pF TEST CONDITIONS Except CLK, VIN = 0V, 5V MIN TYP 10 MAX ±10 - -40oC TO 85oC MIN MAX ±10 UNITS µA pF 4 HI5813 Timing Diagrams 1 2 3 4 5 - 14 15 1 2 3 CLK tD1DRDY tLOW tHIGH STRT tD2DRDY DRDY D0 - D11 DATA N - 1 DATA N VIN OEL = OEM = VSS HOLD N TRACK N TRACK N + 1 FIGURE 1. CONTINUOUS CONVERSION MODE 15 CLK tRSTRT tSUSTRT tWSTRT STRT tD3DRDY 1 2 2 2 3 4 5 DRDY HOLD VIN TRACK HOLD FIGURE 2. SINGLE SHOT MODE OEL OR OEM tEN 90% 50% D0 - D3 OR D4 - D11 HIGH IMPEDANCE TO HIGH HIGH IMPEDANCE TO LOW TO OUTPUT PIN 50% 10% -1.6mA +2.1V 50pF tDIS 1.6mA FIGURE 3A. FIGURE 3. OUTPUT ENABLE/DISABLE TIMING DIAGRAM FIGURE 3B. 5 HI5813 Timing Diagrams (Continued) 1.6mA AMPLITUDE (dB) +2.1V 50pF INPUT FREQUENCY = 1kHz SAMPLING RATE = 33kHz SNR = 65.55dB SINAD = 64.18dB EFFECTIVE BITS = 10.37 THD = -70.02dBc PEAK NOISE = -70.9dB SFDR = 71.1dB -400µA FREQUENCY FIGURE 4. GENERAL TIMING LOAD CIRCUIT FIGURE 5. FFT SPECTRUM Typical Performance Curves 4.00 3.60 3.20 2.80 2.40 INL (LSBs) 2.00 CLK = 500kHz 1.60 1.20 0.80 0.40 0.00 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (oC) VDD = VAA+ = VREF+ = 3.3V CLK = 600kHz DNL ERROR (LSBs) 4.00 3.60 3.20 2.80 2.40 2.00 1.60 1.20 0.80 0.40 0.0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 CLK = 500kHz CLK = 600kHz VDD = VAA+ = VREF+ = 3.3V TEMPERATURE (oC) FIGURE 6. INL vs TEMPERATURE 1.20 VDD = VAA+ = VREF+ = 3.3V 1.10 VOS ERROR (LSBs) 1.00 0.90 0.80 CLK = 500kHz 0.70 0.60 0.50 -50 -40 -30 -20 -10 CLK = 600kHz FSE (LSBs) 0.00 -0.10 -0.20 -0.30 FIGURE 7. DNL vs TEMPERATURE VDD = VAA+ = VREF+ = 3.3V CLK = 500kHz CLK = 600kHz -0.40 -0.50 -0.60 -0.70 -0.80 -0.90 0 10 20 30 40 50 60 70 80 90 -1.00 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (oC) TEMPERATURE (oC) FIGURE 8. OFFSET ERROR vs TEMPERATURE FIGURE 9. FULL SCALE ERROR vs TEMPERATURE 6 HI5813 Typical Performance Curves 2.00 SUPPLY CURRENT, IDD (mA) 1.80 1.60 1.40 1.20 1.00 0.80 0.60 CLK = 500kHz 0.5 0 10 20 30 40 50 60 70 80 90 3.0 3.1 3.2 3.3 3.4 3.5 3.6 TEMPERATURE (oC) SUPPLY VOLTAGE (V) VDD = VAA+ = VREF+ = 3.3V 2.5 DNL ERROR (LSBs) (Continued) 3.0 VDD = VAA+ = VREF+ 2.0 1.5 CLK = 600kHz 1.0 CLK = 500kHz 0.40 -50 -40 -30 -20 -10 FIGURE 10. SUPPLY CURRENT vs TEMPERATURE FIGURE 11. DNL vs SUPPLY VOLTAGE Pin Descriptions PIN # 1 NAME DRDY DESCRIPTION Output flag signifying new data is available. Goes high at end of clock period 15. Goes low when new conversion is started. Bit 0 (Least Significant Bit, LSB). Bit 1. Bit 2. Bit 3. Bit 4. Bit 5. Bit 6. Bit 7. Bit 8. Bit 9. Digital Ground, (0V). Bit 10. Pin Descriptions PIN # 14 15 16 17 18 19 20 21 22 23 24 NAME D11 OEM V AAVAA+ VIN (Continued) DESCRIPTION Bit 11 (Most significant bit, MSB). Three-State enable for D4-D11. Active Low Input. Analog Ground, (0V). Analog Positive Supply. (+3.3V) (See text). Analog Input. 2 3 4 5 6 7 8 9 10 11 12 13 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 VSS D10 VREF+ Reference Voltage Positive Input, sets 4095 code end of input range. VREFSTRT CLK OEL VDD Reference Voltage Negative Input, sets 0 code end of input range. Start Conversion Input active low, recognized after end of clock period 15. CLK Input. Conversion functions are synchronized to positive going edge. (See text). Three-State Enable for D0 - D3. Active low input. Digital Positive Supply (+3.3V). 7 HI5813 Theory of Operation HI5813 is a CMOS 12-Bit, Analog-to-Digital Converter that uses capacitor charge balancing to successively approximate the analog input. A binary weighted capacitor network forms the A/D heart of the device. See the block diagram for the HI5813. The capacitor network has a common node which is connected to a comparator. The second terminal of each capacitor is individually switchable to the input, VREF+ or VREF -. During the first three clock periods of a conversion cycle, the switchable end of every capacitor is connected to the input and the comparator is being auto balanced at the capacitor common node. During the fourth period, all capacitors are disconnected from the input; the one representing the MSB (D11) is connected to the VREF+ terminal; and the remaining capacitors to VREF -. The capacitor common node, after the charges balance out, will indicate whether the input was above 1/2 of (VREF+ - VREF -). At the end of the fourth period, the comparator output is stored and the MSB capacitor is either left connected to VREF+ (if the comparator was high) or returned to VREF -. This allows the next comparison to be at either 3/4 or 1/4 of (VREF+ - VREF -). At the end of periods 5 through 14, capacitors representing D10 through D1 are tested, the result stored, and each capacitor either left at VREF+ or at VREF -. At the end of the 15th period, when the LSB (D0) capacitor is tested, (D0) and all the previous results are shifted to the output registers and drivers. The capacitors are reconnected to the input, the comparator returns to the balance state, and the data ready output goes active. The conversion cycle is now complete. or 1.4µs. The maximum source impedance (RSOURCE Max) for a 6µs acquisition time settling to within 0.5 LSB is 1.3kΩ . If the clock frequency was slower, or the converter was not restarted immediately (causing a longer sample time), a higher source impedance could be tolerated. VIN RSW ≈ 420Ω CSAMPLE ≈ 380pF RSOURCE -tACQ - RSW RSOURCE (MAX) = CSAMPLE ln [2-(N + 1)] FIGURE 12. ANALOG INPUT MODEL IN TRACK MODE Reference Input The reference input VREF+ should be driven from a low impedance source and be well decoupled. Current spikes are generated on the reference pin during each bit test of the successive approximation part of the conversion cycle as the charge balancing capacitors are switched between VREF - and VREF+ (clock periods 5 - 14). These current spikes must settle completely during each bit test of the conversion to not degrade the accuracy of the converter. Therefore V REF+ and VREF - should be well bypassed. Reference input VREF - is normally connected directly to the analog ground plane. If V REF - is biased for nulling the converters offset it must be stable during the conversion cycle. Full Scale and Offset Adjustment In many applications the accuracy of the HI5813 would be sufficient without any adjustments. In applications where accuracy is of utmost importance full scale and offset errors may be adjusted to zero. The VREF+ and VREF - pins reference the two ends of the analog input range and may be used for offset and full scale adjustments. In a typical system the VREF - might be returned to a clean ground, and the offset adjustment done on an input amplifier. VREF+ would then be adjusted to null out the full scale error. When this is not possible, the VREF input can be adjusted to null the offset error, however, VREF must be well decoupled. Full scale and offset error can also be adjusted to zero in the signal conditioning amplifier driving the analog input (VIN). Analog Input The analog input pin is a predominately capacitive load that changes between the track and hold periods of the conversion cycle. During hold, clock period 4 through 15, the input loading is leakage and stray capacitance, typically less than 5µA and 20pF. At the start of input tracking, clock period 1, some charge is dumped back to the input pin. The input source must have low enough impedance to dissipate the current spike by the end of the tracking period. The amount of charge is dependent on supply and input voltages. The average current is also proportional to clock frequency. As long as these current spikes settle completely by end of the signal acquisition period, converter accuracy will be preserved. The analog input is tracked for 3 clock cycles. With a clock of 500kHz the track period is 6µs. A simplified analog input model is presented in Figure 12. During tracking, the A/D input (VIN ) typically appears as a 380pF capacitor being charged through a 420Ω internal switch resistance. The time constant is 160ns. To charge this capacitor from an external “zero Ω” source to 0.5 LSB (1/8192), the charging time must be at least 9 time constants Control Signal The HI5813 may be synchronized from an external source by using the STRT (Start Conversion) input to initiate conversion, or if STRT is tied low, may be allowed to free run. Each conversion cycle takes 15 clock periods. The input is tracked from clock period 1 through period 3, then disconnected as the successive approximation takes place. After the start of the next period 1 (specified by tD data), the output is updated. 8 HI5813 The DRDY (Data Ready) status output goes high (specified by tD1DRDY) after the start of clock period 1, and returns low (specified by tD2DRDY) after the start of clock period 2. The 12 data bits are available in parallel on three-state bus driver outputs. When low, the OEM input enables the most significant byte (D4 through D11) while the OEL input enables the four least significant bits (D0 - D3). tEN and tDIS specify the output enable and disable times. If the output data is to be latched externally, either the trailing edge of data ready or the next falling edge of the clock after data ready goes high can be used. Figure 2 shows operation of the HI5813 when the STRT pin is used to initiate a conversion. If STRT is taken high at least tR STRT before clock period 1 and is not reapplied during that period, the converter will stay in the track mode and the DRDY output will remain high. A low signal applied to STRT will bring the DRDY flag low and the conversion will continue with clock period 3 on the first positive going clock edge that meets the tSUSTRT setup time. part of a low pass RC filter to attenuate switching supply noise. A 10µF capacitor from VAA+ to ground would attenuate 30kHz noise by approximately 40dB. Note that back to back diodes should be placed from VDD to VAA+ to handle supply to capacitor turn-on or turn-off current spikes. Dynamic Performance Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the A/D. A low distortion sine wave is applied to the input of the A/D converter. The input is sampled by the A/D and its output stored in RAM. The data is than transformed into the frequency domain with a 4096 point FFT and analyzed to evaluate the converters dynamic performance such as SNR and THD. See typical performance characteristics. Signal-To-Noise Ratio The signal to noise ratio (SNR) is the measured RMS signal to RMS sum of noise at a specified input and sampling frequency. The noise is the RMS sum of all except the fundamental and the first five harmonic signals. The SNR is dependent on the number of quantization levels used in the converter. The theoretical SNR for an N-bit converter with no differential or integral linearity error is: SNR = (6.02N + 1.76)dB. For an ideal 12-bit converter the SNR is 74dB. Differential and integral linearity errors will degrade SNR: SNR = 10 Log Sinewave Signal Power Total Noise Power Clock The clock used to drive the HI5813 can range in frequency from 50kHz up to 750kHz. All converter functions are synchronized with the rising edge of the clock signal. The clock can be shut off only during the sample (track) portion of the conversion cycle. At other times it must be above the minimum frequency shown in the specifications. In the above two cases, a further restriction applies in that the clock should not be shut off during the third sample period for more than 1ms. This might cause an internal charge pump voltage to decay. If the clock is shut off during the conversion time (clock cycles 4 through 15) of the A/D, the output might be invalid due to balancing capacitor droop. The clock must also meet the minimum tLOW and tHIGH times shown in the specifications. A violation may cause an internal miscount and invalidate the results. Signal-To-Noise + Distortion Ratio SINAD is the measured RMS signal to RMS sum of noise plus harmonic power and is expressed by the following: SINAD = 10 Log Sinewave Signal Power Noise + Harmonic Power (2nd - 6th) Effective Number of Bits The effective number of bits (ENOB) is derived from the SINAD data: ENOB = SINAD - 1.76 6.02 Power Supplies and Grounding VDD and VSS are the digital supply pins: they power all internal logic and the output drivers. Because the output drivers can cause fast current spikes in the VDD and VSS lines, VSS should have a low impedance path to digital ground and VDD should be well bypassed. Except for VAA+, which is a substrate connection to VDD , all pins have protection diodes connected to VDD and VSS . Input transients above VDD or below VSS will get steered to the digital supplies. The VAA+ and VAA- terminals supply the charge balancing comparator only. Because the comparator is autobalanced between conversions, it has good low frequency supply rejection. It does not reject well at high frequencies however; VAA- should be returned to a clean analog ground and VAA+ should be RC decoupled from the digital supply as shown in Figure 13. There is approximately 50Ω of substrate impedance between VDD and VAA+. This can be used, for example, as 9 Total Harmonic Distortion The total harmonic distortion (THD) is the ratio of the RMS sum of the second through sixth harmonic components to the fundamental RMS signal for a specified input and sampling frequency. THD = 10 Log Total Harmonic Power (2nd - 6th Harmonic) Sinewave Signal Power Spurious-Free Dynamic Range The spurious-free dynamic range (SFDR) is the ratio of the fundamental RMS amplitude to the rms amplitude of the next largest spur or spectral component. If the harmonics are buried in the noise floor it is the largest peak. SFDR = 10 Log Sinewave Signal Power Highest Spurious Signal Power HI5813 TABLE 1. CODE TABLE INPUT VOLTAGE† VREF+ = 3.3V VREF - = 0.0V (V) 3.2992 3.2984 2.4750 1.6500 0.8250 0.00080566 0 BINARY OUTPUT CODE MSB DECIMAL COUNT 4095 4094 3072 2048 1024 1 0 D11 1 1 1 1 0 0 0 D10 1 1 1 0 1 0 0 D9 1 1 0 0 0 0 0 D8 1 1 0 0 0 0 0 D7 1 1 0 0 0 0 0 D6 1 1 0 0 0 0 0 D5 1 1 0 0 0 0 0 D4 1 1 0 0 0 0 0 D3 1 1 0 0 0 0 0 D2 1 1 0 0 0 0 0 D1 1 1 0 0 0 0 0 LSB D0 1 0 0 0 0 1 0 CODE DESCRIPTION Full Scale (FS) FS - 1 LSB 3/ FS 4 1/ FS 2 1/ FS 4 1 LSB Zero † The voltages listed above represent the ideal lower transition of each output code shown as a function of the reference voltage. +3.3V 0.1µF 10 µF 0.1 µF 0.01 µF VAA+ VDD D11 . . . D0 DRDY OEM ANALOG INPUT VIN OEL STRT CLK VREF VAAVSS 4.7 µF OUTPUT DATA VREF + 500kHz CLOCK FIGURE 13. GROUND AND SUPPLY DECOUPLING 10 HI5813 Die Characteristics DIE DIMENSIONS: 3200µm x 3940µm METALLIZATION: Type: AlSi Thickness: 11kÅ ±1kÅ PASSIVATION: Type: PSG Thickness: 13kÅ ±2.5kÅ WORST CASE CURRENT DENSITY: 1.84 x 105 A/cm 2 Metallization Mask Layout HI5813 D1 D0 (LSB) DRDY VDD OEL CLK D2 STRT D3 VREF - D4 D5 D6 VREF + D7 VIN D8 VAA + VAA - D9 VSS D10 D11 (MSB) OEM 11 HI5813 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M24.3 (JEDEC MS-013-AD ISSUE C) 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 2.35 0.10 0.33 0.23 15.20 7.40 MAX 2.65 0.30 0.51 0.32 15.60 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0926 0.0040 0.013 0.0091 0.5985 0.2914 MAX 0.1043 0.0118 0.020 0.0125 0.6141 0.2992 A1 B C D E α µ A1 0.10(0.004) C e H h L N 0.05 BSC 0.394 0.010 0.016 24 0o 8o 0.419 0.029 0.050 1.27 BSC 10.00 0.25 0.40 24 0o 10.65 0.75 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality/iso.asp. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation 2401 Palm Bay Rd. Palm Bay, FL 32905 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369 12