HI5828EVAL2

HI5828 Data Sheet August 1999 File Number 4658.1 12-Bit, 125+MSPS, CommLink™ Dual High Speed CMOS D/A (2.7V-5.5V) The HI5828 is a Dual 12-bit, 125+MSPS (Mega Samples Per Second), high speed, low power, D/A converter which is implemented in an advanced CMOS process. Operating from a single +3V to +5V supply, the converter provides 20mA of full scale output current and includes edge-triggered CMOS input data latches. Low glitch energy and excellent frequency domain performance is achieved by the HI5828’s segmented current source architecture. This device complements the CommLink HI5x60 and HI5x28 family of high speed converters, which includes 8, 10, 12, and 14-bit devices Features • Throughput Rate . . . . . . . . . . . . . . . . . . . . . . .125+MSPS • Low Power . . . . 312mW at 5V, 46mW at 3V (at 60MSPS) • Integral Linearity Error . . . . . . . . . . . . . . . . . . . ±0.75 LSB (Typ) • Adjustable Full Scale Output Current . . . . . . 2mA to 20mA • Internal 1.2V Bandgap Voltage Reference • Single or Dual Power Supply from +3V to +5V • Power Down Mode • CMOS Compatible Inputs • Excellent Spurious Free Dynamic Range (76dBc, f S = 50MSPS, fOUT = 2.51MHz) • Excellent Multitone Intermodulation Distortion Ordering Information PART NUMBER HI5828IN HI5828EVAL2 TEMP. RANGE (oC) -40 to 85 25 PACKAGE 48 Ld LQFP PKG. NO. CLOCK SPEED Applications • Basestations (Cellular, WLL) • Quadrature Modulation • Wireless Communications Systems Q48.7x7A 125MSPS 125MSPS Evaluation Platform Pinout HI5828 (LQFP) TOP VIEW ID11 (MSB) QD0 (LSB) • Direct Digital Frequency Synthesis • Signal Reconstruction • Medical/Test Instrumentation • High Resolution Imaging Systems QD1 QD2 QD3 ID9 ID10 ID5 ID4 ID3 ID2 ID1 (LSB) ID0 N.C. N.C. SLEEP DVDD AGND ICOMP2 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 ID6 N.C. N.C. ID7 ID8 • Arbitrary Waveform Generators QD4 QD5 QD6 QD7 QD8 QD9 QD10 QD11 (MSB) CLK DGND AGND QCOMP2 AGND FSADJ IOUTA IOUTB ICOMP1 QOUTB QOUTA REFLO REFIO QCOMP1 AVDD 1 AVDD CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 CommLink™ is a trademark of Intersil Corporation. HI5828 Functional Block Diagram (LSB) QD0 QD1 QD2 QD3 QD4 QD5 QD6 QD7 QD8 QD9 QD10 (MSB) QD11 7 38 SWITCH DRIVERS 38 CURRENT CELLS 7 LSBs QOUTA MASTER LATCH 5 THERMOMETER DECODER 31 SLAVE LATCH + QOUTB 31 MSB SEGMENTS QCOMP1 BIAS GENERATION QCOMP2 (LSB) ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 ID10 (MSB) ID11 7 38 MASTER LATCH 5 THERMOMETER DECODER 31 SLAVE LATCH SWITCH DRIVERS 38 CURRENT CELLS 7 LSBs + 31 MSB SEGMENTS IOUTA IOUTB CLK BIAS GENERATION DVDD DGND AVDD AGND ICOMP2 AVDD SLEEP BANDGAP VOLTAGE REFERENCE - + ICOMP1 REFLO REFIO FSADJ 2 HI5828 Typical Applications Circuit ID6 ID7 ID8 ID9 ID10 ID11 (MSB) QD0 (LSB) QD1 QD2 QD3 ID5 ID4 ID3 ID2 ID1 ID0 (LSB) SLEEP DVPP C1 0.1µF ICOMP2 C2 0.1µF AVPP 48 47 46 45 44 43 42 41 40 39 38 37 36 1 35 2 34 3 33 4 32 5 31 6 30 7 N.C. 29 8 N.C. CLK 28 9 DGND 27 10 DVDD AGND 26 11 AGND 25 12 13 14 15 16 17 18 19 20 21 22 23 24 REFIO REFLO AGND FSADJ N.C. N.C. AVDD C4 0.1µF AVDD C5 0.1µF QCOMP1 RSET 1.91kΩ R5 R4 50Ω 50Ω QD4 QD5 QD6 QD7 QD8 QD9 QD10 QD11 (MSB) R1 50Ω C3 0.1µF AVPP QCOMP2 C6 0.1µF ICOMP1 C7 0.1µF AVPP R2 R3 50Ω 50Ω C8 0.1µF AVPP CONN1 (IOUTA) CONN2 (IOUTB) CONN3 (QOUTB) CONN4 (QOUTA) BEAD FERRITE + C11 10µF +5V OR +3V POWER SOURCE FERRITE BEAD + C14 10µF L2 10µH AVPP (ANALOG POWER PLANE) C12 0.1µF C13 1µF L1 10µH DVPP (DIGITAL POWER PLANE) C9 0.1µF C10 1µF NOTE: Separate analog and digital grounds should be used, in which case the grounds should be tied together at a single point near the device. The analog and digital grounds should be connected together by a thin single trace and never connected together by an inductor. 3 HI5828 Pin Descriptions PIN NO. 11, 19, 26 13, 24 28 PIN NAME AGND AVDD CLK Analog Ground. Analog Supply (+2.7V to +5.5V). Clock Input. The master and slave latches shown in the functional block diagram are simple D-latches. Input data to the DAC passes through the “master” latches when the clock is low and is latched into the “master” latches when the clock is high. Data presented to the “slave” latch passes through when the clock is logic high and is latched into the “slave” latches when the clock is logic low. Adequate setup time must be allowed for the MSBs to pass through the thermometer decoder before the clock goes high. This master-slave arrangement comprises an edge-triggered flip-flop, with the DAC being updated on the rising clock edge. It is recommended that the clock edge be skewed such that setup time is larger than hold time for optimum spectral performance. Connect to Digital Ground. Digital Supply (+2.7V to +5.5V). Full Scale Current Adjust. Use a resistor to analog ground to adjust full scale output current. Full Scale Output Current = 32 x VFSADJ/RSET. Where VFSADJ is the voltage at this pin. VFSADJ tracks the voltage on the REFIO pin (refer to the functional block diagram); which is typically 1.2V if the internal reference is used. Compensation Pin for Use in Reducing Bandwidth/Noise. Each pin should be individually decoupled to AVDD with a 0.1µF capacitor. To minimize crosstalk, the part was designed so that these pins must be connected externally, ideally directly under the device packaging. The voltage on these pins is used to drive the gates of the PMOS devices that make up the current cells. Only the ICOMP1 pin is driven and therefore QCOMP1 needs to be connected to ICOMP1, but de-coupled separately to minimize crosstalk. If placed equally close to both pins, then only one decoupling capacitor might be necessary. Compensation Pin for Internal Bias Generation. Each pin should be individually decoupled to AGND with a 0.1µF capacitor. The voltage generated at these pins represents the voltage used to supply power to the switch drivers (refer to the functional block diagram) which is 2.0V nominal. This arrangement helps to minimize clock feedthrough to the current cell transistors for reduced glitch energy and improved spectral performance. PIN DESCRIPTION 27 10 20 DGND DVDD FSADJ 14, 23 ICOMP1, QCOMP1 12, 25 ICOMP2, QCOMP2 43-48, 1-6, 29-40 15, 22 16, 21 ID11-ID0, QD11-QD0 Digital Data Input Ports. Bit 11 is Most Significant Bit (MSB) and bit 0 is the Least Significant Bit (LSB). IOUTA, QOUTA IOUTB, QOUTB Current Outputs of the Device. Full scale output current is achieved when all input bits are set to binary 1. Complementary Current Outputs of the Device. Full scale output current is achieved on the complementary outputs when all input bits are set to binary 0. No Connection. Future LSBs for dual 14-bit DAC. Reference voltage input if Internal reference is disabled. The internal reference is not intended to drive an external load. Use 0.1µF cap to ground when internal reference is enabled. Reference Low Select. When the internal reference is enabled, this pin serves as the precision ground reference point for the internal voltage reference circuitry and therefore needs to have a good connection to analog ground to enable internal 1.2V reference. To disable the internal reference circuitry this pin should be connected to AVDD. Control Pin for Power-Down Mode. Sleep Mode is active high; connect to ground for Normal Mode. The Sleep pin has internal 25µA (nominal) active pulldown current. 7, 8, 41, 42 17 N.C. REFIO 18 REFLO 9 SLEEP 4 HI5828 Absolute Maximum Ratings Digital Supply Voltage DVDD to DGND . . . . . . . . . . . . . . . . . . +5.5V Analog Supply Voltage AVDD to AGND . . . . . . . . . . . . . . . . . . +5.5V Grounds, AGND TO DGND . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V Digital Input Voltages (D11-D0, CLK, SLEEP). . . . . . . DVDD + 0.3V Reference Input Voltage Range . . . . . . . . . . . . . . . . . . .AVDD + 0.3V Analog Output Current (IOUTA/B, QOUTA/B) . . . . . . . . . . . . . 24mA Thermal Information Thermal Resistance (Typical, Note 1) θJA(oC/W) LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (LQFP - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications AVDD = DVDD = +5V (except where otherwise noted), VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values TA = -40oC TO 85oC PARAMETER SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL Differential Linearity Error, DNL Offset Error, IOS Offset Drift Coefficient Full Scale Gain Error, FSE TEST CONDITIONS MIN TYP MAX UNITS 12 “Best Fit” Straight Line (Note 8) (Note 8) (Note 8) (Note 8) With External Reference (Notes 2, 8) With Internal Reference (Notes 2, 8) -2.0 -1.0 -0.025 -10 -10 2 fCLK = 100MSPS, fOUT = 10MHz fCLK = 100MSPS, fOUT = 40MHz -5 -0.445 -0.3 ±0.75 ±0.5 0.1 ±2 ±1 ±50 ±100 85 64 - +2.0 +1.0 +0.025 +10 +10 20 +5 +0.420 1.25 Bits LSB LSB % FSR ppm FSR/oC % FSR % FSR ppm FSR/oC ppm FSR/oC mA dB dB % FSR dB FSR V Full Scale Gain Drift With External Reference (Note 8) With Internal Reference (Note 8) Full Scale Output Current, IFS Crosstalk Gain Matching Between Channels (DC Measurement) Output Voltage Compliance Range DYNAMIC CHARACTERISTICS Maximum Clock Rate, fCLK Output Settling Time, (tSETT) Singlet Glitch Area (Peak Glitch) Output Rise Time Output Fall Time Output Capacitance Output Noise As a percentage of Full Scale Range In dB Full Scale Range (Note 3, 8) (Note 3) ±0.05% (±2 LSB) (Note 8) RL = 25Ω (Note 8) Full Scale Step Full Scale Step 125 - 35 5 2.5 2.5 10 50 30 - MHz ns pV•s ns ns pF pA/ √Hz pA/ √Hz IOUTFS = 20mA IOUTFS = 2mA - 5 HI5828 Electrical Specifications AVDD = DVDD = +5V (except where otherwise noted), VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued) TA = -40oC TO 85oC PARAMETER AC CHARACTERISTICS +5V Power Supply Spurious Free Dynamic Range, SFDR Within a Window +5V Power Supply Total Harmonic Distortion (THD) to Nyquist +5V Power Supply Spurious Free Dynamic Range, SFDR to Nyquist (fCLK/2) fCLK = 100MSPS, fOUT = 20.2MHz, 30MHz Span (Notes 4, 8) fCLK = 100MSPS, fOUT = 5.04MHz, 8MHz Span (Notes 4, 8) fCLK = 50MSPS, fOUT = 5.02MHz, 8MHz Span (Notes 4, 8) fCLK = 100MSPS, fOUT = 4.0MHz (Notes 4, 8) fCLK = 50MSPS, fOUT = 2.0MHz (Notes 4, 8) fCLK = 25MSPS, fOUT = 1.0MHz (Notes 4, 8) fCLK = 125MSPS, fOUT = 40.4MHz (Notes 4, 8) fCLK = 125MSPS, fOUT = 10.1MHz (Notes 4, 8) fCLK = 125MSPS, fOUT = 5.02MHz, T = 25oC (Notes 4, 8) fCLK = 125MSPS, fOUT = 5.02MHz, T = Min to Max (Notes 4, 8) fCLK = 100MSPS, fOUT = 40.4MHz (Notes 4, 8) fCLK = 100MSPS, fOUT = 20.2MHz (Notes 4, 8) fCLK = 100MSPS, fOUT = 5.04MHz, T = 25oC (Notes 4, 8) 66 66 66 66 66 66 77 93 93 -72 -74 -73 55 66 72 54 62 72 75 64 72 76 78 77 76 76 73 91 91 -71 -75 -74 dBc dBc dBc dB dB dB dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dB dB dB TEST CONDITIONS MIN TYP MAX UNITS fCLK = 100MSPS, fOUT = 5.04MHz, T = Min to Max (Notes 4, 8) fCLK = 100MSPS, fOUT = 2.51MHz (Notes 4, 8) fCLK = 50MSPS, fOUT = 20.2MHz (Notes 4, 8) fCLK = 50MSPS, fOUT = 5.02MHz, T = 25oC (Notes 4, 8) fCLK = 50MSPS, fOUT = 5.02MHz, T = Min to Max (Notes 4, 8) fCLK = 50MSPS, fOUT = 2.51MHz (Notes 4, 8) fCLK = 50MSPS, fOUT = 1.00MHz (Notes 4, 8) fCLK = 25MSPS, fOUT = 1.0MHz (Notes 4, 8) +5V Power Supply Multitone Power Ratio fCLK = 20MSPS, fOUT = 2.0MHz to 2.99MHz, 8 Tones at 110kHz Spacing (Notes 4, 8) fCLK = 100MSPS, fOUT = 10MHz to 14.95MHz, 8 Tones at 530kHz Spacing (Notes 4, 8) +3V Power Supply Spurious Free Dynamic Range, SFDR Within a Window +3V Power Supply Total Harmonic Distortion (THD) to Nyquist fCLK = 100MSPS, fOUT = 20.2MHz, 30MHz Span (Notes 4, 8) fCLK = 100MSPS, fOUT = 5.04MHz, 8MHz Span (Notes 4, 8) fCLK = 50MSPS, fOUT = 5.02MHz, 8MHz Span (Notes 4, 8) fCLK = 100MSPS, fOUT = 4.0MHz (Notes 4, 8) fCLK = 50MSPS, fOUT = 2.0MHz (Notes 4, 8) fCLK = 25MSPS, fOUT = 1.0MHz (Notes 4, 8) 6 HI5828 Electrical Specifications AVDD = DVDD = +5V (except where otherwise noted), VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued) TA = -40oC TO 85oC PARAMETER +3V Power Supply Spurious Free Dynamic Range, SFDR to Nyquist (fCLK/2) TEST CONDITIONS fCLK = 125MSPS, fOUT = 40.4MHz (Notes 4, 8) fCLK = 125MSPS, fOUT = 10.1MHz (Notes 4, 8) fCLK = 125MSPS, fOUT = 5.02MHz (Notes 4, 8) fCLK = 100MSPS, fOUT = 40.4MHz (Notes 4, 8) fCLK = 100MSPS, fOUT = 20.2MHz (Notes 4, 8) fCLK = 100MSPS, fOUT = 5.04MHz (Notes 4, 8) fCLK = 100MSPS, fOUT = 2.51MHz (Notes 4, 8) fCLK = 50MSPS, fOUT = 20.2MHz (Notes 4, 8) fCLK = 50MSPS, fOUT = 5.02MHz, T = 25oC (Notes 4, 8) MIN 68 66 TYP 47 66 73 48 58 72 76 53 73 76 76 76 76 76 MAX UNITS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc fCLK = 50MSPS, fOUT = 5.02MHz, T = Min to Max (Notes 4, 8) fCLK = 50MSPS, fOUT = 2.51MHz (Notes 4, 8) fCLK = 50MSPS, fOUT = 1.00MHz(Notes 4, 8) fCLK = 25MSPS, fOUT = 1.0MHz (Notes 4, 8) +3V Power Supply Multitone Power Ratio fCLK = 20MSPS, fOUT = 2.0MHz to 2.99MHz, 8 Tones at 110kHz Spacing (Notes 4, 8) fCLK = 100MSPS, fOUT = 10MHz to 14.95MHz, 8 Tones at 530kHz Spacing (Notes 4, 8) VOLTAGE REFERENCE Internal Reference Voltage, VFSADJ Internal Reference Voltage Drift Internal Reference Output Current Sink/Source Capability Reference Input Impedance Reference Input Multiplying Bandwidth (Note 8) DIGITAL INPUTS D11-D0, CLK Input Logic High Voltage with 5V Supply, VIH Input Logic High Voltage with 3V Supply, VIH Input Logic Low Voltage with 5V Supply, VIL Input Logic Low Voltage with 3V Supply, VIL Input Sleep Current, IIH Input Logic Current, IIH Input Logic Current, IIL Digital Input Capacitance, CIN TIMING CHARACTERISTICS Data Setup Time, tSU Data Hold Time, tHLD Propagation Delay Time, tPD CLK Pulse Width, tPW1 , tPW2 See Figure 4 (Note 3) See Figure 4 (Note 3) See Figure 4 See Figure 4 (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) Pin 18 Voltage with Internal Reference 1.15 - 1.22 ±10 ±100 1 1.4 1.29 - V ppm/oC nA MΩ MHz 3.5 2.1 -25 -10 -10 - 5 3 0 0 5 1.3 0.9 +25 +10 +10 - V V V V µA µA µA pF 4 1.5 1.2 2.5 - - ns ns ns ns 7 HI5828 Electrical Specifications AVDD = DVDD = +5V (except where otherwise noted), VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued) TA = -40oC TO 85oC PARAMETER POWER SUPPLY CHARACTERISTICS AVDD Power Supply DVDD Power Supply Analog Supply Current (IAVDD) (Note 9) (Note 9) 5V or 3V, IOUTFS = 20mA 5V or 3V, IOUTFS = 2mA Digital Supply Current (IDVDD) 5V (Note 5) 5V (Note 6) 5V (Note 7) 3V (Note 5) 3V (Note 6) 3V (Note 7) Supply Current (IAVDD) Sleep Mode Power Dissipation 5V or 3V, IOUTFS = Don’t Care 5V, IOUTFS = 20mA (Note 5) 5V, IOUTFS = 20mA (Note 6) 5V, IOUTFS = 20mA (Note 7) 5V, IOUTFS = 2mA (Note 6) 3V, IOUTFS = 20mA (Note 5) 3V, IOUTFS = 20mA (Note 6) 3V, IOUTFS = 20mA (Note 7) 3V, IOUTFS = 2mA (Note 6) Power Supply Rejection NOTES: 2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625µA). Ideally the ratio should be 32. 3. Parameter guaranteed by design or characterization and not production tested. 4. Spectral measurements made with differential transformer coupled output and no external filtering. 5. Measured with the clock at 60MSPS and the output frequency at 10MHz. 6. Measured with the clock at 100MSPS and the output frequency at 40MHz. 7. Measured with the clock at 125MSPS and the output frequency at 5MHz. 8. See “Definition of Specifications”. 9. It is recommended that the output current be reduced to 12mA or less to maintain optimum performance for operation below 3V. DVDD and AVDD do not have to be equal. Single Supply (Note 8) 2.7 2.7 -0.2 5.0 5.0 44 7 12 17.6 29 4 8.2 9.6 2.7 280 312 365 137 144 158 161 46 177 +0.2 5.5 5.5 47 38 12 425 V V mA mA mA mA mA mA mA mA mA mW mW mW mW mW mW mW mW % FSR/V TEST CONDITIONS MIN TYP MAX UNITS 8 HI5828 Definition of Specifications Differential Linearity Error, DNL, is the measure of the step size output deviation from code to code. Ideally the step size should be 1 LSB. A DNL specification of 1 LSB or less guarantees monotonicity. Full Scale Gain Drift, is measured by setting the data inputs to be all logic high (all 1s) and measuring the output voltage through a known resistance as the temperature is varied from TMIN to TMAX . It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm of FSR (full scale range) per oC. Full Scale Gain Error , is the error from an ideal ratio of 32 between the output current and the full scale adjust current (through RSET). Integral Linearity Error, INL, is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve. Internal Reference Voltage Drift, is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm per oC. Offset Drift, is measured by setting the data inputs to all logic low (all 0s) and measuring the output voltage through a known resistance as the temperature is varied from TMIN to TMAX . It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm of FSR (full scale range) per degree oC. Offset Error, is measured by setting the data inputs to all logic low (all 0s) and measuring the output voltage through a known resistance. Offset error is defined as the maximum deviation of the output current from a value of 0mA. Output Settling Time, is the time required for the output voltage to settle to within a specified error band measured from the beginning of the output transition. The measurement is done by switching quarter scale. Termination impedance was 25Ω due to the parallel resistance of the 50Ω loading on the output and the oscilloscope’s 50Ω input. This also aids the ability to resolve the specified error band without overdriving the oscilloscope. Output Voltage Compliance Range, is the voltage limit imposed on the output. The output impedance should be chosen such that the voltage developed does not violate the compliance range. Power Supply Rejection, is measured using a single power supply. The supply’s nominal +5V is varied ±10% and the change in the DAC full scale output is noted. Reference Input Multiplying Bandwidth, is defined as the 3dB bandwidth of the voltage reference input. It is measured by using a sinusoidal waveform as the external reference with the digital inputs set to all 1s. The frequency is increased until the amplitude of the output waveform is 0.707 (-3dB) of its original value. Singlet Glitch Area, is the switching transient appearing on the output during a code transition. It is measured as the area under the overshoot portion of the curve and is expressed as a Volt-Time specification. This is tested using a single code transition across a major current source. Spurious Free Dynamic Range, SFDR, is the amplitude difference from the fundamental signal to the largest harmonically or non-harmonically related spur within the specified frequency window. Total Harmonic Distortion, THD, is the ratio of the RMS value of the fundamental output signal to the RMS sum of the first five harmonic components. Detailed Description The HI5828 is a dual 12-bit, current out, CMOS, digital to analog converter. Its maximum update rate is 125+MSPS and can be powered by either single or dual power supplies in the recommended range of +3V to +5V. Operation with clock rates higher than 125MSPS is possible; please contact the factory for more information. It consumes 370mW of power when using a +5V supply with the data switching at 125MSPS. The architecture is based on a segmented current source arrangement that reduces glitch by reducing the amount of current switching at any one time. In previous architectures that contained all binary weighted current sources or a binary weighted resistor ladder, the converter might have a substantially larger amount of current turning on and off at certain, worst-case transition points such as midscale and quarter scale transitions. By greatly reducing the amount of current switching at certain ‘major’ transitions, the overall glitch of the converter is dramatically reduced, improving settling time, transient problems, and accuracy. Digital Inputs and Termination The HI5828 digital inputs are guaranteed to CMOS levels. However, TTL compatibility can be achieved by lowering the supply voltage to 3V due to the digital threshold of the input buffer being approximately half of the supply voltage. The internal register is updated on the rising edge of the clock. To minimize reflections, proper termination should be implemented. If the lines driving the clock and the digital inputs are long 50Ω lines, then 50Ω termination resistors should be placed as close to the converter inputs as possible connected to the digital ground plane (if separate grounds are used). These termination resistors are not likely needed as long as the digital waveform source is within a few inches of the DAC. 9 HI5828 Ground Planes Separate digital and analog ground planes should be used. All of the digital functions of the device and their corresponding components should be located over the digital ground plane and terminated to the digital ground plane. The same is true for the analog components and the analog ground plane. Consult Application Note AN9855. Outputs The 5 MSBs for each DAC on the HI5828 drive a thermometer decoder, which is a digital decoder that has an N-bit (5 bits for the HI5828) binary coded input word with 2N-1 (31 for the HI5828) output bits, where the number of output bits that are active correlate directly to the input binary word. The HI5828 uses a thermometer decoder to significantly minimize the output glitch energy for each DAC. I/QOUTA and I/QOUTB are complementary current outputs. The sum of the two currents is always equal to the full scale output current minus one LSB. If single ended use is desired, a load resistor can be used to convert the output current to a voltage. It is recommended that the unused output be either grounded or equally terminated. The voltage developed at the output must not violate the output voltage compliance range of -0.3V to 1.25V. RLOAD (the impedance loading each current output) should be chosen so that the desired output voltage is produced in conjunction with the output full scale current. If a known line impedance is to be driven, then the output load resistor should be chosen to match this impedance. The output voltage equation is: VOUT = IOUT X RLOAD. These outputs can be used in a differential-to-single-ended arrangement to achieve better harmonic rejection. The SFDR measurements in this data sheet were performed with a 1:1 transformer on the output of the DAC (see Figure 1). With the center tap grounded, the output swing of pins 15/22 and 16/23 will be biased at zero volts. The loading as shown in Figure 1 will result in a 500mV signal at the output of the transformer if the full scale output current of the DAC is set to 20mA. VOUT = 2 x IOUT x REQ, where REQ is ~12.5Ω. R EQ IS THE IMPEDANCE LOADING EACH OUTPUT. 50Ω PIN 15/22 PIN 16/23 HI5828 I/QOUTA 100Ω I/QOUTB 50Ω 50Ω REPRESENTS THE SPECTRUM ANALYZER 50Ω V OUT = (2 x I OUT x R EQ)V Noise Reduction To minimize power supply noise, 0.1µF capacitors should be placed as close as possible to the converter’s power supply pins, AVDD and DVDD. Also, the layout should be designed using separate digital and analog ground planes and these capacitors should be terminated to the digital ground for DVDD and to the analog ground for AVDD. Additional filtering of the power supplies on the board is recommended. Voltage Reference The internal voltage reference of the device has a nominal value of + 1.2V with a ± 10ppm/ oC drift coefficient over the full temperature range of the converter. It is recommended that a 0.1µF capacitor be placed as close as possible to the REFIO pin, connected to the analog ground. The REFLO pin (18) selects the reference. The internal reference can be selected if pin 18 is tied low (ground). If an external reference is desired, then pin 18 should be tied high (the analog supply voltage) and the external reference driven into REFIO, pin 17. The full scale output current of the converter is a function of the voltage reference used and the value of RSET. IOUT should be within the 2mA to 20mA range, though operation below 2mA is possible, with performance degradation. VFSADJ and VREFIO will be equivalent except for a small offset voltage. If the internal reference is used, VFSADJ will equal approximately 1.2V on the FSADJ pin (20). If an external reference is used, VFSADJ will equal the external reference. The calculation for IOUT(Full Scale) is: IOUT(Full Scale) = (VFSADJ/RSET) X 32. If the full scale output current is set to 20mA by using the internal voltage reference (1.2V) and a 1.91kΩ RSET resistor, then the input coding to output current will resemble the following: TABLE 1. INPUT CODING vs OUTPUT CURRENT INPUT CODE (D11-D0) 11 11111 11111 10 00000 00000 00 00000 00000 I/QOUTA (mA) 20 10 0 I/QOUTB (mA) 0 10 20 FIGURE 1. Allowing the center tap to float will result in identical transformer output, however the output pins of the DAC will have positive DC offset. Since the DAC’s output voltage compliance range is -0.3V to +1.25V, the center tap may need to be left floating or DC offset in order to increase the amount of signal swing available. The 50Ω load on the output of the transformer represents the spectrum analyzer’s input impedance. 10 HI5828 Timing Diagrams CLK 50% D11-D0 V 1/ LSB ERROR BAND 2 GLITCH AREA = 1/2 (H x W) HEIGHT (H) IOUT WIDTH (W) tSETT tPD t(ps) FIGURE 2. OUTPUT SETTLING TIME DIAGRAM FIGURE 3. PEAK GLITCH AREA (SINGLET) MEASUREMENT METHOD tPW1 tPW2 CLK 50% tSU tHLD D11-D0 tSU tHLD tSU tHLD tPD tSETT IOUT tPD tSETT tPD tSETT FIGURE 4. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM 11 HI5828 Thin Plastic Quad Flatpack Packages (LQFP) D D1 -D- Q48.7x7A (JEDEC MS-026BBC ISSUE B) 48 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE INCHES SYMBOL A A1 A2 MIN 0.002 0.054 0.007 0.007 0.350 0.272 0.350 0.272 0.018 48 0.020 BSC MAX 0.062 0.005 0.057 0.010 0.009 0.358 0.280 0.358 0.280 0.029 MILLIMETERS MIN 0.05 1.35 0.17 0.17 8.90 6.90 8.90 6.90 0.45 48 0.50 BSC MAX 1.60 0.15 1.45 0.27 0.23 9.10 7.10 9.10 7.10 0.75 NOTES 6 3 4, 5 3 4, 5 7 Rev. 2 1/99 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- . 0.08 A-B S 0.003 M C DS b b1 0.09/0.16 0.004/0.006 BASE METAL WITH PLATING -AE E1 -B- b b1 D D1 E e PIN 1 SEATING A PLANE 0.08 0.003 -C- E1 L N e -H- 4. Dimensions D1 and E1 to be determined at datum plane -H- . 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm (0.003 inch). 7. “N” is the number of terminal positions. 11o-13o 0.020 0.008 MIN 0o MIN GAGE PLANE L 0o-7o 0.25 0.010 11o-13o A2 A1 0.09/0.20 0.004/0.008 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 12