HI5860_05

® HI5860 Data Sheet May 4, 2005 FN4654.6 12-Bit, 130MSPS, High Speed D/A Converter The HI5860 is a 12-bit, 130MSPS (Mega Samples Per Second), high speed, low power, D/A converter which is implemented in an advanced CMOS process. Operating from a single +3V to +5V supply, the converter provides 20mA of full scale output current and includes edge-triggered CMOS input data latches. Low glitch energy and excellent frequency domain performance are achieved using a segmented current source architecture. This device complements the HI5x60 and HI5x28 family of high speed converters, which includes 8, 10, 12, and 14-bit devices. Features • Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 130MSPS • Low Power . . . 175mW at 5V, 32mW at 3V (At 100MSPS) • Integral Linearity Error (Typ) . . . . . . . . . . . . . . . ±0.5 LSB • Adjustable Full Scale Output Current . . . . . 2mA to 20mA • Internal 1.2V Bandgap Voltage Reference • Single Power Supply from +5V to +3V • Power Down Mode • CMOS Compatible Inputs • Excellent Spurious Free Dynamic Range (76dBc, f S = 50MSPS, fOUT = 2.51MHz) • Excellent Multitone Intermodulation Distortion • Pb-Free Available (RoHS Compliant) Ordering Information PART NUMBER HI5860IA* HI5860IB HI5860IBZ (See Note) HI5860SOICEVAL1 TEMP. RANGE (°C) PACKAGE PKG. DWG. # CLOCK SPEED 130MHz 130MHz 130MHz 130MHz -40 to 85 28 Ld TSSOP M28.173 -40 to 85 28 Ld SOIC -40 to 85 28 Ld SOIC (PB-free) 25 M28.3 M28.3 Applications • Basestations (Cellular, WLL) • Medical/Test Instrumentation • Wireless Communications Systems • Direct Digital Frequency Synthesis • Signal Reconstruction • High Resolution Imaging Systems • Arbitrary Waveform Generators Evaluation Platform *Add “-T” for tape and reel. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinout HI5860 (SOIC, TSSOP) TOP VIEW D11 (MSB) 1 D10 2 D9 3 D8 4 D7 5 D6 6 D5 7 D4 8 D3 9 D2 10 D1 11 D0 (LSB) 12 NC 13 NC 14 28 CLK 27 DVDD 26 DCOM 25 ACOM 24 AVDD 23 COMP2 22 IOUTA 21 IOUTB 20 ACOM 19 COMP1 18 FSADJ 17 REFIO 16 REFLO 15 SLEEP 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2000, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HI5860 Typical Applications Circuit HI5860 NC (13, 14) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 50Ω DCOM (26) BEAD + 10µF 10µH 0.1µF DVDD (27) (24) AVDD 0.1µF D11 (1) D10 (2) D9 (3) D8 (4) D7 (5) D6 (6) D5 (7) D4 (8) D3 (9) D2 (10) D1 (11) D0 (LSB) (12) CLK (28) (21) IOUTB (23) COMP2 (19) COMP1 (20) ACOM 0.1µF 0.1µF FERRITE BEAD 10µH 10µF + +5V OR +3V (VDD) 50Ω D/A OUT (22) IOUTA 50Ω (18) FSADJ RSET D/A OUT 1.91kΩ (25) ACOM (15) SLEEP (16) REFLO (17) REFIO 0.1µF ACOM DCOM Functional Block Diagram IOUTA IOUTB (LSB) D0 D1 D2 D3 D4 D5 LATCH D6 D7 D8 D9 D10 (MSB) D11 COMP2 COMP1 CLK INT/EXT SELECT REFERENCE INT/EXT VOLTAGE REFERENCE BIAS GENERATION UPPER 5-BIT DECODER 31 LATCH 38 SWITCH MATRIX 38 7 LSBs + 31 MSB SEGMENTS CASCODE CURRENT SOURCE AVDD ACOM DVDD DCOM REFLO REFIO FSADJ SLEEP 2 FN4654.6 May 4, 2005 HI5860 Pin Descriptions PIN NO. 1-12 13,14 15 16 17 18 19 21 22 23 24 20, 25 26 27 28 PIN NAME D11 (MSB) Through D0 (LSB) NC SLEEP REFLO REFIO FSADJ COMP1 IOUTB IOUTA COMP2 AVDD ACOM DCOM DVDD CLK PIN DESCRIPTION Digital Data Bit 11, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit). No Connect. (Available as 2 additional LSBs on the HI5960, 14 bit device). Control Pin for Power-Down Mode. Sleep Mode is active high; connect to ground for Normal Mode. Sleep pin has internal 20µA active pulldown current. Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal reference. Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is enabled. Use 0.1µF cap to ground when internal reference is enabled. Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output Current = 32 x VFSADJ/RSET. For use in reducing bandwidth/noise. Recommended: Connect 0.1µF to AVDD . The complementary current output of the device. Full scale output current is achieved when all input bits are set to binary 0. Current output of the device. Full scale output current is achieved when all input bits are set to binary 1. Connect 0.1µF capacitor to ACOM. Analog Supply (+2.7V to +5.5V). Connect to Analog Ground. Connect to Digital Ground. Digital Supply (+2.7V to +5.5V). Clock Input. Input data to the DAC passes through the “master” latches when the clock is low and is latched into the “master” latches when the clock is high. Data presented to the “slave” latch passes through when the clock is logic high and is latched into the “slave” latches when the clock is logic low. Adequate setup time must be allowed for the MSBs to pass through the thermometer decoder before the clock goes high. This master-slave arrangement comprises an edge-triggered flip-flop, with the DAC being updated on the rising clock edge. For optimum spectral performance, it is recommended that the clock edge be skewed such that setup time is larger than the hold time. 3 FN4654.6 May 4, 2005 HI5860 Absolute Maximum Ratings Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . +5.5V Analog Supply Voltage AVDD to ACOM. . . . . . . . . . . . . . . . . . +5.5V Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V Digital Input Voltages (D11-D0, CLK, SLEEP) . . . . . . . DVDD + 0.3V Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD + 0.3V Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA Thermal Information Thermal Resistance (Typical, Note 1) θJA(°C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C (SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications AVDD = DVDD = +5V (except where otherwise noted), VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25°C for All Typical Value TA = -40°C TO 85°C PARAMETER SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL Differential Linearity Error, DNL Offset Error, IOS Offset Drift Coefficient TEST CONDITIONS MIN TYP MAX UNITS 12 “Best Fit” Straight Line (Note 8) (Note 8) (Note 8) (Note 8) -2.0 -1.0 -0.025 - ±0.5 ±0.5 0.1 +2.0 +1.0 +0.025 - Bits LSB LSB % FSR ppm FSR/°C° C % FSR % FSR ppm FSR/°C ppm FSR/°C mA V Full Scale Gain Error, FSE With External Reference (Notes 2, 8) With Internal Reference (Notes 2, 8) -10 -10 2 ±2 ±1 ±50 ±100 - +10 +10 20 1.25 Full Scale Gain Drift With External Reference (Note 8) With Internal Reference (Note 8) Full Scale Output Current, IFS Output Voltage Compliance Range DYNAMIC CHARACTERISTICS Maximum Clock Rate, fCLK Output Settling Time, (tSETT) Singlet Glitch Area (Peak Glitch) Output Rise Time Output Fall Time Output Capacitance Output Noise IOUTFS = 20mA IOUTFS = 2mA AC CHARACTERISTICS +5V Power Supply Spurious Free Dynamic Range, SFDR Within a Window fCLK = 100MSPS, fOUT = 20.2MHz, 10MHz Span (Notes 4, 8) fCLK = 100MSPS, fOUT = 5.04MHz, 4MHz Span (Notes 4, 8) fCLK = 50MSPS, fOUT = 5.02MHz, 2MHz Span (Notes 4, 8) (Note 3) ±0.05% (±2 LSB) (Note 8) RL = 25Ω (Note 8) Full Scale Step Full Scale Step (Note 3, 8) -0.3 130 - 35 5 2.5 2.5 10 50 30 - MHz ns pV•s ns ns pF pA/ √Hz pA/ √Hz - 77 95 95 - dBc dBc dBc 4 FN4654.6 May 4, 2005 HI5860 Electrical Specifications AVDD = DVDD = +5V (except where otherwise noted), VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25°C for All Typical Value (Continued) TA = -40°C TO 85°C PARAMETER +5V Power Supply Total Harmonic Distortion (THD) to Nyquist +5V Power Supply Spurious Free Dynamic Range, SFDR to Nyquist (fCLK/2) TEST CONDITIONS fCLK = 100MSPS, fOUT = 4.0MHz (Notes 4, 8) fCLK = 50MSPS, fOUT = 2.0MHz (Notes 4, 8) fCLK = 25MSPS, fOUT = 1.0MHz (Notes 4, 8) fCLK = 130MSPS, fOUT = 40.4MHz (Notes 4, 8) fCLK = 130MSPS, fOUT = 10.1MHz (Notes 4, 8) fCLK = 130MSPS, fOUT = 5.02MHz, T = 25°C (Notes 4, 8) fCLK = 130MSPS, fOUT = 5.02MHz, T = Min to Max (Notes 4, 8) fCLK = 100MSPS, fOUT = 40.4MHz (Notes 4, 8) fCLK = 100MSPS, fOUT = 20.2MHz (Notes 4, 8) fCLK = 100MSPS, fOUT = 5.04MHz, T = 25°C (Notes 4, 8) fCLK = 100MSPS, fOUT = 5.04MHz, T = Min to Max (Notes 4, 8) fCLK = 100MSPS, fOUT = 2.51MHz (Notes 4, 8) fCLK = 50MSPS, fOUT = 20.2MHz (Notes 4, 8) fCLK = 50MSPS, fOUT = 5.02MHz, T = 25°C (Notes 4, 8) fCLK = 50MSPS, fOUT = 5.02MHz, T = Min to Max (Notes 4, 8) fCLK = 50MSPS, fOUT = 2.51MHz (Notes 4, 8) fCLK = 50MSPS, fOUT = 1.00MHz (Notes 4, 8) fCLK = 25MSPS, fOUT = 1.0MHz (Notes 4, 8) +5V Power Supply Multitone Power Ratio fCLK = 20MSPS, fOUT = 2.0MHz to 2.99MHz, 8 Tones at 110kHz Spacing (Notes 4, 8) fCLK = 100MSPS, fOUT = 10MHz to 14.95MHz, 8 Tones at 530kHz Spacing (Notes 4, 8) +3V Power Supply Spurious Free Dynamic Range, SFDR Within a Window +3V Power Supply Total Harmonic Distortion (THD) to Nyquist fCLK = 100MSPS, fOUT = 20.2MHz, 30MHz Span (Notes 4, 8) fCLK = 100MSPS, fOUT = 5.04MHz, 8MHz Span (Notes 4, 8) fCLK = 50MSPS, fOUT = 5.02MHz, 8MHz Span (Notes 4, 8) fCLK = 100MSPS, fOUT = 4.0MHz (Notes 4, 8) fCLK = 50MSPS, fOUT = 2.0MHz (Notes 4, 8) fCLK = 25MSPS, fOUT = 1.0MHz (Notes 4, 8) MIN 68 66 68 66 68 66 TYP -71 -75 -76 55 66 74 54 62 74 75 64 74 76 78 78 76 76 73 92 92 -71 -75 -75 MAX UNITS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc 5 FN4654.6 May 4, 2005 HI5860 Electrical Specifications AVDD = DVDD = +5V (except where otherwise noted), VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25°C for All Typical Value (Continued) TA = -40°C TO 85°C PARAMETER +3V Power Supply Spurious Free Dynamic Range, SFDR to Nyquist (fCLK/2) TEST CONDITIONS fCLK = 130MSPS, fOUT = 40.4MHz (Notes 4, 8) fCLK = 130MSPS, fOUT = 10.1MHz (Notes 4, 8) fCLK = 130MSPS, fOUT = 5.02MHz (Notes 4, 8) fCLK = 100MSPS, fOUT = 40.4MHz (Notes 4, 8) fCLK = 100MSPS, fOUT = 20.2MHz (Notes 4, 8) fCLK = 100MSPS, fOUT = 5.04MHz (Notes 4, 8) fCLK = 100MSPS, fOUT = 2.51MHz (Notes 4, 8) fCLK = 50MSPS, fOUT = 20.2MHz (Notes 4, 8) fCLK = 50MSPS, fOUT = 5.02MHz, T = 25°C (Notes 4, 8) fCLK = 50MSPS, fOUT = 5.02MHz, T = Min to Max (Notes 4, 8) fCLK = 50MSPS, fOUT = 2.51MHz (Notes 4, 8) fCLK = 50MSPS, fOUT = 1.00MHz(Notes 4, 8) fCLK = 25MSPS, fOUT = 1.0MHz (Notes 4, 8) +3V Power Supply Multitone Power Ratio fCLK = 20MSPS, fOUT = 2.0MHz to 2.99MHz, 8 Tones at 110kHz Spacing (Notes 4, 8) fCLK = 100MSPS, fOUT = 10MHz to 14.95MHz, 8 Tones at 530kHz Spacing (Notes 4, 8) VOLTAGE REFERENCE Internal Reference Voltage, VFSADJ Internal Reference Voltage Drift Internal Reference Output Current Sink/Source Capability Reference Input Impedance Reference Input Multiplying Bandwidth (Note 8) DIGITAL INPUTS D11-D0, CLK (Note 3) (Note 3) (Note 3) (Note 3) 3.5 2.1 -25 -20 -10 5 3 0 0 5 1.3 0.9 +25 +20 +10 V V V V µA µA µA pF Pin 18 Voltage with Internal Reference 1.13 1.2 ±60 ±50 1 1.4 1.28 V ppm/°C MIN 68 66 - TYP 47 66 73 48 58 72 76 53 73 76 76 76 75 75 MAX - UNITS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc µA MΩ MHz Input Logic High Voltage with 5V Supply, VIH Input Logic High Voltage with 3V Supply, VIH Input Logic Low Voltage with 5V Supply, VIL Input Logic Low Voltage with 3V Supply, VIL Sleep Input Current, IIH Input Logic Current, IIH Input Logic Current, IIL Digital Input Capacitance, CIN TIMING CHARACTERISTICS Data Setup Time, tSU Data Hold Time, tHLD Propagation Delay Time, tPD CLK Pulse Width, tPW1 , tPW2 See Figure 4 (Note 3) See Figure 4 (Note 3) See Figure 4 See Figure 4 (Note 3) 4 1.5 1.2 2.5 - - ns ns ns ns 6 FN4654.6 May 4, 2005 HI5860 Electrical Specifications AVDD = DVDD = +5V (except where otherwise noted), VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25°C for All Typical Value (Continued) TA = -40°C TO 85°C PARAMETER POWER SUPPLY CHARACTERISTICS AVDD Power Supply DVDD Power Supply Analog Supply Current (IAVDD) (Notes 9) (Notes 9) 5V or 3V, IOUTFS = 20mA 5V or 3V, IOUTFS = 2mA Digital Supply Current (IDVDD) 5V (Note 5) 5V (Note 6) 5V (Note 7) 3V (Note 5) 3V (Note 6) 3V (Note 7) Supply Current (IAVDD) Sleep Mode Power Dissipation 5V or 3V, IOUTFS = Don’t Care 5V, IOUTFS = 20mA (Note 5) 5V, IOUTFS = 20mA (Note 6) 5V, IOUTFS = 20mA (Note 7) 5V, IOUTFS = 2mA (Note 6) 3V, IOUTFS = 20mA (Note 5) 3V, IOUTFS = 20mA (Note 6) 3V, IOUTFS = 20mA (Note 7) 3V, IOUTFS = 2mA (Note 6) Power Supply Rejection NOTES: 2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625µA). Ideally the ratio should be 32. 3. Parameter guaranteed by design or characterization and not production tested. 4. Spectral measurements made with differential transformer coupled output and no external filtering. 5. Measured with the clock at 50MSPS and the output frequency at 10MHz. 6. Measured with the clock at 100MSPS and the output frequency at 40MHz. 7. Measured with the clock at 130MSPS and the output frequency at 10MHz. 8. See “Definition of Specifications”. 9. It is recommended that the output current be reduced to 12mA or less to maintain optimum performance for operation below 3V. DVDD and AVDD do not have to be equal. Single Supply (Note 8) 2.7 2.7 -0.2 5.0 5.0 23 5 7 12 13 2.4 6 5 2.7 150 175 180 80 76 87 84 32 5.5 5.5 200 100 +0.2 V V mA mA mA mA mA mA mA mA mA mW mW mW mW mW mW mW mW % FSR/V TEST CONDITIONS MIN TYP MAX UNITS 7 FN4654.6 May 4, 2005 HI5860 Definition of Specifications Differential Linearity Error, DNL, is the measure of the step size output deviation from code to code. Ideally the step size should be 1 LSB. A DNL specification of 1 LSB or less guarantees monotonicity. Full Scale Gain Drift, is measured by setting the data inputs to be all logic high (all 1s) and measuring the output voltage through a known resistance as the temperature is varied from TMIN to TMAX . It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm of FSR (full scale range) per °C. Full Scale Gain Error , is the error from an ideal ratio of 32 between the output current and the full scale adjust current (through RSET). Integral Linearity Error, INL, is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve. Internal Reference Voltage Drift, is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm per °C. Offset Drift, is measured by setting the data inputs to all logic low (all 0s) and measuring the output voltage through a known resistance as the temperature is varied from TMIN to TMAX . It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm of FSR (full scale range) per degree °C. Offset Error, is measured by setting the data inputs to all logic low (all 0s) and measuring the output voltage through a known resistance. Offset error is defined as the maximum deviation of the output current from a value of 0mA. Output Settling Time, is the time required for the output voltage to settle to within a specified error band measured from the beginning of the output transition. The measurement is done by switching quarter scale. Termination impedance was 25Ω due to the parallel resistance of the 50Ω loading on the output and the oscilloscope’s 50Ω input. This also aids the ability to resolve the specified error band without overdriving the oscilloscope. Output Voltage Compliance Range, is the voltage limit imposed on the output. The output impedance should be chosen such that the voltage developed does not violate the compliance range. Power Supply Rejection, is measured using a single power supply. The supply’s nominal +5V is varied ±10% and the change in the DAC full scale output is noted. Reference Input Multiplying Bandwidth, is defined as the 3dB bandwidth of the voltage reference input. It is measured by using a sinusoidal waveform as the external reference with the digital inputs set to all 1s. The frequency is increased until the amplitude of the output waveform is 0.707 (-3dB) of its original value. Singlet Glitch Area, is the switching transient appearing on the output during a code transition. It is measured as the area under the overshoot portion of the curve and is expressed as a Volt-Time specification. This is tested using a single code transition across a major current source. Spurious Free Dynamic Range, SFDR, is the amplitude difference from the fundamental signal to the largest harmonically or non-harmonically related spur within the specified frequency window. Total Harmonic Distortion, THD, is the ratio of the RMS value of the fundamental output signal to the RMS sum of the first five harmonic components. Detailed Description The HI5860 is an 12-bit, current out, CMOS, digital to analog converter. Its maximum update rate is 130MSPS and can be powered by either single or dual power supplies in the recommended range of +3V to +5V. Operation with clock rates higher than 130MSPS is possible; please contact the factory for more information. It consumes less than 180mW of power when using a +5V supply with the data switching at 130MSPS. The architecture is based on a segmented current source arrangement that reduces glitch by reducing the amount of current switching at any one time. In previous architectures that contained all binary weighted current sources or a binary weighted resistor ladder, the converter might have a substantially larger amount of current turning on and off at certain, worst-case transition points such as midscale and quarter scale transitions. By greatly reducing the amount of current switching at certain “major” transitions, the overall glitch of the converter is dramatically reduced, improving settling time, transient problems, and accuracy. Digital Inputs and Termination The HI5860 digital inputs are guaranteed to CMOS levels. However, TTL compatibility can be achieved by lowering the supply voltage to 3V due to the digital threshold of the input buffer being approximately half of the supply voltage. The internal register is updated on the rising edge of the clock. To minimize reflections, proper termination should be implemented. If the lines driving the clock and the digital inputs are long 50Ω lines, then 50Ω termination resistors should be placed as close to the converter inputs as possible connected to the digital ground plane (if separate grounds are used). These termination resistors are not likely needed as long as the digital waveform source is within a few inches of the DAC. Ground Planes Separate digital and analog ground planes should be used. All of the digital functions of the device and their FN4654.6 May 4, 2005 8 HI5860 corresponding components should be located over the digital ground plane and terminated to the digital ground plane. The same is true for the analog components and the analog ground plane. Consult Application Note 9853. Outputs IOUTA and IOUTB are complementary current outputs. The sum of the two currents is always equal to the full scale output current minus one LSB. If single ended use is desired, a load resistor can be used to convert the output current to a voltage. It is recommended that the unused output be either grounded or equally terminated. The voltage developed at the output must not violate the output voltage compliance range of -0.3V to 1.25V. RLOAD (the impedance loading each current output) should be chosen so that the desired output voltage is produced in conjunction with the output full scale current. If a known line impedance is to be driven, then the output load resistor should be chosen to match this impedance. The output voltage equation is: VOUT = IOUT X RLOAD . These outputs can be used in a differential-to-single-ended arrangement to achieve better harmonic rejection. The SFDR measurements in this data sheet were performed with a 1:1 transformer on the output of the DAC (see Figure 1). With the center tap grounded, the output swing of pins 21 and 22 will be biased at zero volts. The loading as shown in Figure 1 will result in a 500mV signal at the output of the transformer if the full scale output current of the DAC is set to 20mA. REQ IS THE IMPEDANCE LOADING EACH OUTPUT 50Ω IOUTB PIN 21 PIN 22 HI5860 IOUTA 100Ω 50Ω 50Ω VOUT = (2 x IOUT x REQ)V Noise Reduction To minimize power supply noise, 0.1µF capacitors should be placed as close as possible to the converter’s power supply pins, AVDD and DVDD . Also, the layout should be designed using separate digital and analog ground planes and these capacitors should be terminated to the digital ground for DVDD and to the analog ground for AVDD . Additional filtering of the power supplies on the board is recommended. Voltage Reference The internal voltage reference of the device has a nominal value of +1.2V with a ±60ppm / °C drift coefficient over the full temperature range of the converter. It is recommended that a 0.1µF capacitor be placed as close as possible to the REFIO pin, connected to the analog ground. The REFLO pin (16) selects the reference. The internal reference can be selected if pin 16 is tied low (ground). If an external reference is desired, then pin 16 should be tied high (the analog supply voltage) and the external reference driven into REFIO, pin 17. The full scale output current of the converter is a function of the voltage reference used and the value of RSET. IOUT should be within the 2mA to 20mA range, though operation below 2mA is possible, with performance degradation. If the internal reference is used, VFSADJ will equal approximately 1.2V (pin 18). If an external reference is used, VFSADJ will equal the external reference. The calculation for IOUT (Full Scale) is: IOUT(Full Scale) = (VFSADJ/RSET) X 32. If the full scale output current is set to 20mA by using the internal voltage reference (1.2V) and a 1.91kΩ RSET resistor, then the input coding to output current will resemble the following: TABLE 1. INPUT CODING vs OUTPUT CURRENT INPUT CODE (D11-D0) 11 11111 11111 10 00000 00000 00 00000 00000 IOUTA (mA) 20 10 0 IOUTB (mA) 0 10 20 50Ω REPRESENTS THE SPECTRUM ANALYZER FIGURE 1. VOUT = 2 x IOUT x REQ, where REQ is ~12.5Ω. Allowing the center tap to float will result in identical transformer output, however the output pins of the DAC will have positive DC offset. Since the DAC’s output voltage compliance range is 0.3V to +1.25V, the center tap may need to be left floating or DC offset in order to increase the amount of signal swing available. The 50Ω load on the output of the transformer represents the spectrum analyzer’s input impedance. 9 FN4654.6 May 4, 2005 HI5860 Timing Diagrams 50% CLK D11-D0 V GLITCH AREA = 1/2 (H x W) HEIGHT (H) ERROR BAND IOUT WIDTH (W) t(ps) tSETT tPD FIGURE 2. OUTPUT SETTLING TIME DIAGRAM FIGURE 3. PEAK GLITCH AREA (SINGLET) MEASUREMENT METHOD tPW1 tPW2 CLK tSU tHLD D11-D0 tSU tHLD tSU tHLD 50% tPD tSETT IOUT tPD tSETT tPD tSETT FIGURE 4. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 FN4654.6 May 4, 2005