HIP0081AS1

HIP0080, HIP0081 TM Data Sheet November 2000 File Number 3018.5 Quad Inverting Power Drivers with Serial Diagnostic Interface The HIP0080/0081 Quad Power Drivers contain four individually protected NDMOS power output transistor switches to drive inductive and resistive loads such as: relays, solenoids, injectors, AC and DC motors, heaters and incandescent lamp displays. The 4 Power Drivers are low-side switches driven by CMOS logic input control stages. Each Output Power Driver is protected against over-current, over-temperature and over-voltage. An internal drain-to-gate zener diode provides the clamping protection for over-voltage. Diagnostic circuits provide ground short, supply short, open load and thermal overload detection for each of the 4 output stages. Each of the 4 input drivers and their respective diagnostic filters are controlled by one ENABLE input. The inputs are CMOS logic compatible and individually control the output drivers with an active high state for turnon. All other control inputs are active high with the exception of the Chip Select (CS) which is active low. The DATAIN (DI) and DATAOUT (DO) are positive logic and the Clock (CLK) input for the Serial Interface is active on the rising edge of the CLK pulse. All Inputs except the HIP0080 ENABLE have a nominal level of hysteresis. IN1, IN2, IN3, IN4 and ENABLE have pull-down resistors of approximately 100kΩ. This switches off any channel that has an unterminated input. Filters are used on the outputs of the fault sensing comparators to avoid the detection of short duration transient spikes. The on-chip oscillator is used to clock an internal shift register in each filter. If the fault condition is longer than a preset number of clock cycles, the fault condition is recognized and the respective bit is set in the diagnostic register. No filter is used in the thermal-overload feedback circuit and the bit is set when thermal shutdown occurs. For normal operating conditions, a Reset turns off all outputs when the VCC level drops below 3.5V. The internal bandgap and bias supply function includes a 5V regulated supply for the low voltage signal and logic circuits. Features • Low Side Power MOSFET Output Drivers • Output Driver Protection - Over-Current Shutdown - Over-Temperature Shutdown with Hysteresis - Over-Voltage Internal Clamp • HIP0081 Output Current Switching Capability: - Each Output, IOUT . . . . . . . . . . . . . . . . . . . . . . 2.2A DC - All Outputs ON, Equal IOUT . . . . . . . . . . . . . . . . 6A DC - All Outputs ON, Equal IOUT . . . . . . . . . . 8A PK, 500ms • HIP0080 Output Current Switching Capability: - Each Output, IOUT . . . . . . . . . . . . . . . . . . . . . . 1.3A DC - All Outputs ON, Unequal IOUT . . . . . . . . . . . . . . 3A DC - All Outputs ON, Unequal IOUT . . . . . . . . 4A PK, 500ms • HIP0080 - Low Idle Current Shutdown Mode • Regulated Interface for 5V CMOS Logic Inputs • Open Drain High Z DATAOUT • Fault Mode Output for Shorts, Opens and Over-Temperature • 16-Bit Serial Diagnostic Register • SPI Bus Compatible Data Readout • HIP0081 - Low θJC Power Package . . . . . . . . . . . . 3oC/W • -40oC to 125oC Operating Temperature Range Applications • Drivers For: - Solenoids - Relays - Power Output - Lamps - Injectors - Steppers - Motors - Displays • System Use: - Automotive - Appliances - Industrial - Robotics Ordering Information PART NUMBER HIP0081AS1 HIP0081AS2 HIP0080AM TEMP. RANGE (oC) -40 to 125 -40 to 125 -40 to 125 PACKAGE 15 Ld SIP 15 Ld SIP 28 Ld PLCC PKG. NO. Z15.05A Z15.05B N28.45 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 HIP0080, HIP0081 Pinouts HIP0081 (SIP) TOP VIEW HEAT SINK TAB AT SAME POTENTIAL AS PIN 8-GND HIP0080 (PLCC) TOP VIEW OUT 2 OUT 1 26 CLK DATA OUT 28 IN 2 CS 4 3 2 1 27 IN1 GND GND 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 5 6 7 8 9 25 GND 24 GND 23 GND 22 GND 21 GND 20 GND 19 GND GND GND OUT1 IN1 DATAOUT IN2 OUT2 CLK CS GND ENABLE VCC OUT3 IN3 DATAIN IN4 OUT4 GND GND 10 GND 11 12 ENABLE 13 VCC 14 OUT 3 15 16 DATAIN IN 3 17 18 OUT 4 Functional Block Diagram 1 OF 4 SWITCH/CHANNELS O.L. FILTER VCC1 100kΩ IN1 DR1-CNTL POR SC S.C. FILTER COMP DR EN TS COMP 10kΩ O.L. VREF 10kΩ VCC1 OUT1 G.S. FILTER COMP 74V VREF G.S. TEMP. SENSE VREF ISC LIMIT 0.01Ω IN 4 GND CS CLK DATAOUT DATAIN ENABLE POR (PWR-ON-RST) EN CONTROL AND 16-BIT DIAGNOSTIC SHIFT FCLK DO REGISTER (NOTE) LOW IDLE CURRENT POWER DOWN SWITCH (HIP0080 ONLY) 100kΩ 500kHz OSC (FILTER-FCLK) VCC1 14V BANDGAP REF. AND BIAS VOLTAGE SOURCES VCC NOTE: HIP0080 - No enable hysteresis. 2 HIP0080, HIP0081 Functional Signal Flow Diagram 1 OF 4 SWITCH/CHANNELS (SEE FUNCTIONAL BLOCK DIAGRAM) IN1 DR1 CNTL (DATAPATH) 4 IN2 DATAIN (DI) SHIFT REGISTER 4 IN3 DR3 CNTL (DATAPATH) 4 IN4 DR4 CNTL (DATAPATH) 4 4 4 BANDGAP AND BIAS VCC 4 DR OUT4 (DRVR) OUT4 4 DR OUT3 (DRVR) OUT3 DR2 CNTL (DATAPATH) 4 OUT2 DR OUT2 (DRVR) 4 DR OUT1 (DRVR) OUT1 TEST POR CS CONTROL CLK ENABLE (EN) OSC 3 SERIAL DATAOUT (DRIVER) DATAOUT (DO) LOW IDLE CURRENT POWER DOWN SWITCH (HIP0080 ONLY) 3 HIP0080, HIP0081 Absolute Maximum Ratings Supply Voltage (Logic and Control), VCC . . . . . . . . . . . . -16 to 45V Power MOSFET Drain Voltage, VO (Note 1) . . . . . . -0.5 to VCLAMP Maximum Output Clamp Energy, EOK (HIP0080) . . . . . . . . . Note 4 Maximum Output Clamp Energy, EOK (HIP0081) . . . . . . . . . Note 4 Input Voltage (Logic and Driver Inputs), VIN . . . . . . . . . . . -0.5 to 7V Output Voltage, DATAOUT . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 7V HIP0080 Output Current Each Output, IOUT(PEAK), (Note 2) . . . . . . -1.5A to IOUT(SC) Each Output, IOUT(DC) . . . . . . . . . . . . . . . . . . . . . . . . +1.3A Total of 4 Outputs ON, Unequal IOUT . . . . . . . . . . . . . . . . +3A Total of 4 Outputs ON, Unequal IOUT . . . . . +4A/500ms (Max) HIP0081 Output Current Each Output, IOUT(PEAK), (Note 2) . . . . . . . . . -2 to IOUT(SC) Each Output, IOUT(DC) . . . . . . . . . . . . . . . . . . . . . . . . +2.2A Total of 4 Outputs, ON, Unequal IOUT . . . . . . . . . . . . . . . +6A Total of 4 Outputs ON, Unequal IOUT . . . . . +8A/500ms (Max) Thermal Information Thermal Resistance (Typical, Note 3) θJA(oC/W) θJC(oC/W) HIP0080 . . . . . . . . . . . . . . . . . . . . . . . . 43 N/A HIP0080 (on 2 sq. in. PC Board) . . . . . 33 N/A HIP0081 . . . . . . . . . . . . . . . . . . . . . . . . 45 3 HIP0080 Power Dissipation with a 2 sq. in. PC Board Heat Sink: At 85oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.95W Above 85oC:. . . . . . . . . . . . . . . . . . . Derate Linearly at 30mW/oC HIP0081 Power Dissipation with Infinite Heat Sink: At 125oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.33W Above 125oC . . . . . . . . . . . . . . . . . Derate Linearly at 333 mW/oC Maximum Storage Temperature Range, TSTG . . . . -55oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . 300oC Die Characteristics HIP0080 Back Side Potential . . . . . . . . . . . . . . Frame, GND Leads HIP0081 Back Side Potential . . . . . . . . . Heat Sink Tab, GND Lead Operating Conditions Ambient Temperature Range . . . . . . . . . . . . . . . . . -40oC to 125oC Junction Temperature Range . . . . . . . . . . . . . . . . . -40oC to 150oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. The MOSFET Output Drain is internally Clamped with a Drain-to-Gate zener diode that turns-on the MOSFET to hold the Drain at the VCLAMP voltage. Refer to the Electrical Characteristic Tables for the VCLAMP voltage limits. 2. Each Output has Over-Current Shutdown protection in the positive current direction. The maximum peak current rating is determined by the minimum Over-Current Shutdown as detailed in the Electrical Specification Table. In the event of an Over-Current Shutdown the input drive is latched OFF. The output short must be removed and the input toggled OFF and ON to restore the output drive. 3. Effective Heat Sinking for the HIP0080 PLCC package requires a PC Board solder mount or equivalent. The HIP0080 θJA junction-to-air thermal resistance is given for a PC Board with 2 sq. in. of 1 oz. surface mount ground copper extending away from the package. For additional Power Dissipation Derating information, see Figure 8 curves. 4. Refer to Figures 4 and 5 Single Pulse Output Clamp Energy vs. Time Capability of the HIP0080 and HIP0081. The safe margin for single pulse energy operation is below the dotted line shown in Figures 4 and 5. Electrical Specifications VCC = 5.5V to 25V ±5%, TA = -40oC to 125oC, Unless Otherwise Specified HIP0080 HIP0081 MAX MIN TYP MAX UNITS PARAMETER POWER OUTPUTS Output ON Resistance (HIP0081) SYMBOL TEST CONDITIONS MIN TYP rON VCC = 10 to 25V, All Outputs ON IOUT1 = IOUT2 = IOUT3 = IOUT4 = 1A VCC = 5.5 to 10V, All Outputs ON IOUT1 = IOUT2 = IOUT3 = IOUT4 = 0.7A - - 1.0 2.0 - - 0.75 0.75 1.0 0.5 1.0 1.0 1.5 10 Ω Ω Ω Ω mA mA µA Output ON Resistance (HIP0080) rON VCC = 10 to 25V, All Outputs ON IOUT1 = IOUT2 = IOUT3 = IOUT4 = 0.5A VCC = 5.5 to 10V, All Outputs ON IOUT1 = IOUT2 = IOUT3 = IOUT4 = 0.4A HIP0081 Output Off Current IOFF Inputs Low, Each VOUT = 60V TA = 25oC to 125oC Inputs Low, Each VOUT = 60V, TA = -40oC HIP0081 Output Leakage Current IOFFLK Inputs Low, Each VOUT = 60V, VCC = 0V 4 HIP0080, HIP0081 Electrical Specifications VCC = 5.5V to 25V ±5%, TA = -40oC to 125oC, Unless Otherwise Specified (Continued) HIP0080 PARAMETER HIP0080 Output Off Current SYMBOL IOFF TEST CONDITIONS Inputs Low, Each VOUT = 25V, ENABLE High, TA = 25oC to 125oC Inputs Low, Each VOUT = 25V, ENABLE High, TA = -40oC HIP0080 Output Leakage Current Over-Voltage Clamp Range Current Short Circuit Prot. Short Circuit Det. Delay Output ON-OFF Voltage Ramp Rate Turn-On Delay Turn-Off Delay SUPPLY Power Supply Current Power Supply Reset Active ICC VCC_RST TA = 25oC to TA = 125oC TA = -40oC ISHTDN Enable Low 3 2.7 20 130 30 4 4 200 3 2.7 20 30 4 4 mA V V µA tPHL tPLH IOFFLK VCLAMP IOUT(SC) tSCDLY Resistive Load VCC = 14V, RLOAD = 14Ω VCC = 14V, RLOAD = 14Ω Inputs Low, Each VOUT = 25V, ENABLE Low IN Inputs Low (Outputs OFF), IOUT = 40mA Note 2 MIN 27 1.3 TYP 0.75 0.75 1.0 6 10 MAX 1.0 1.5 10 43 3 8 8 MIN 73 2.2 HIP0081 TYP 6 10 MAX 89 4.8 8 8 UNITS mA mA µA V A µs V/µs µs µs Shut-Down Current Mode INPUTS Low-Level Input Voltage High-Level Input Voltage Input Hysteresis Threshold Input Pull-Down Resistance DATAOUT (Open Drain) Leakage Current Logic Low Output Voltage Max. Logic Low Current Oscillator Frequency Serial Interface Clock Freq. VIL VIH VIN_HYS RPD (N.A. to HIP0080 ENABLE) IN1, IN2, IN3, IN4 and ENABLE 3.5 0.85 50 100 1 2.25 200 3.5 0.85 50 100 1 2.25 200 V V V kΩ IDO_LEAK VDO = 7V, DO OFF (High) VOL IOH fOSC fCLK Note 5 IDO = 1.6mA, DO ON (Low) VDO = 4.5V, DO ON 1.6 - 500 - 10 0.4 2 1.6 - 500 - 10 0.4 2 µA V mA kHz MHz DIAGNOSTIC AND PROTECTION Over-Temperature Shutdown Threshold Shutdown Temperature Hysteresis Output Short-to-GND Threshold Short-to-GND Hysteresis Open-Load Resistance for No-Load Warning Filter Delay Time for O.L. or Short-to-GND NOTE: 5. The maximum Serial Clock Frequency may be limited by the time constant of the external load network at the DATAOUT pin. VCC = 5.5V to 16V VCC = 5.5V to 16V VCC = 5.5V to 16V 150 5 165 15 0.24x VCC 0.02x VCC 12 25 150 5 165 15 0.24x VCC 0.02x VCC 12 25 oC oC V V kΩ µs 5 HIP0080, HIP0081 Diagnostic Interface Overview Each Quad Inverting Power Driver IC may be used as a single power switching driver, with or without the diagnostic interface. Where more than 4 Power Driver Switches are required, the HIP0080 or HIP0081 may be used in a multiple IC cascade connection. In cascade operation, the diagnostic data from all chips is read as a single serial sequence of fault bits. As shown in the Functional Block Diagram each output stage has voltage and temperature sensors to detect fault conditions while comparators and delay filters process the data. Four bits of diagnostic information is provided as fault feedback from each of the four output stages. When detected, the diagnostic data is put in a parallel diagnostic data register. Using the diagnostic control interface to address the system (one or more ICs in cascade), the fault data is transferred from the parallel diagnostic data register to a serial diagnostic data register as a sequence of 16 bits for each IC. All diagnostic data bits may be read using the Chip Select (CS) and the Clock (CLK) inputs. The CLK input must be low, when CS goes active low. After reading the first bit at DO to determine if there is an error flag, the following 16 bits of serial diagnostic data may be clocked out of DO. Clocking the CLK input synchronously shifts the serial register data out of DO while cascaded data (from other devices or sources) is shifted into the DI input. As data is shifted out of DO, the parallel diagnostic data register is cleared on the first rising edge of the CLK input, following the CS low. After each 16 clocks, cascaded diagnostic data from the next IC in sequence is then shifted out of the DO output. Shifting the serial diagnostic data out of DO is done as a continuous sequence, reading the data from all ICs in cascade while CS remains low. New diagnostic data can be stored in the parallel diagnostic data registers on each IC while the existing serial diagnostic data is read. Referring to Figure 1 and Figure 2, there are two sources that generate an OR’ed Fault Flag at DO when CS goes low. The two fault data sources are (1) the on-chip fault detection and (2) the off-chip DI input from front end ICs in the cascade. The fault data bit, labeled DF (Data Fault) in Figure 2, contains the OR’ed inputs from both sources. The DF bit is not part of the 16-bit serial diagnostic data sequence. In cascaded operation, the DI input for the first of the selected chips should be tied low. And, in single IC operation (no cascade), the DI input should also be tied low. In cascaded operation, the Error Flags are cascaded via the DI inputs. The on-chip fault Error Flag goes high if any one of the 16 diagnostic data fault bits have been set HIGH. This fault Error Flag bit precedes the 16 diagnostic data fault bits and is OR’ed with all diagnostic data fault bits. The DF bit flags the presence of an Error Flag fault on the IC and in any part of the cascaded string, including DI data input. As shown in Figure 3 each IC in the cascade provides an output which is passed to the DI input of the following IC and is passed on as an OR’ed bit to the DO output of the last IC in the cascade. A fault condition is immediately evident without reading all diagnostic data bits. 6 However, all bits must be read to determine which chip and which diagnostic bit has been set. The Fault Flag is reset by the CLK input when the bits are read. When no fault condition is detected, it is not necessary to toggle the CLK input. When a fault is detected, at least one toggle of the clock is needed to reset the parallel diagnostic register which clears the register of all detected fault states. The last IC in the string ORs its own 16 fault bits in the parallel diagnostic register data and sends this data bit to an Error Flag register. The Error Flag register outputs the presence of a fault in one or more bits of the parallel diagnostic data register. As shown in Figure 2, the Error Flag is the first bit in front of the serial register and is input to OR Gate, U7 with the DI input. The DI input passes through AND Gate, U6 when the GATE signal is high and output via the amplifier U8 to DO. The output amplifier U8 is active only while CS is low. When CS is low, the RS Flip-Flop drives the GATE output high. When the GATE is high, the cascaded DF bits are jammed from DI to DO. All Error Flags in the cascade are cleared (by the CLK input) when the serial diagnostic data is clocked out of DO. The GATE is an internal control signal that is forced high when the CLK input is low and CS goes low. The GATE will remain high, even when CS is returned to a high state, provided the CLK input has not changed from a low state. This condition still applies when fault data is detected. The DO output is not latched; however, the Error Flag is latched when CS goes low and will not be updated until the next time CS goes low. The fault data is preserved as long as the CLK input does not go high. If the CLK is high when CS goes low, the GATE will be disabled and no cascade data will be shifted from DI to DO. Under normal conditions, the CLK signal goes high to switch the GATE low and simultaneously shifts the first of 16 diagnostic data bits out of the serial diagnostic data register to DO. The CS low input is not latched and must be held low while all data is shifted out of DO. The diagnostic interfaces to the HIP0080 and HIP0081 are SPI compatible. The microcontroller is programmed to control the read and respond action based on the diagnostic readout. Normally the CS input is addressed and DO is read. If a fault is indicated by the Error Flag, all data is shifted out of DO and processed to determine the diagnostic fault condition. The Error Flag bit does require a separate input back to the microcontroller to initiate the serial data shift. When the CLK signal starts, the serial sequence starting with the first of the 16 serial diagnostic bits is input to the microcontroller. Serial Register Data Sequence The fault data follows the Serial Register Data Sequence of Table 1 in bit sequence and, in cascade, by IC sequence. In each of the 4 power switching output channels, the diagnostic sense circuits set 1-bit in the parallel diagnostic register for each of the 4 diagnostics fault conditions. A total of 16 diagnostics data bits are shifted to the serial register when CS goes low. Table 1 shows the order and sequence HIP0080, HIP0081 of the serial bits as they are shifted out of DO. The fault action that sets each of the diagnostics bits for each of the 4 switches is described below: Bit 1 - indicates a thermal overload when the sensed junction temperature of the output is greater than 150oC. When overtemperature is sensed, the sensor output directly gates-off the drive to the power output and the respective fault bit is set in the diagnostic register. When the chip is sufficiently cooled, the output is gated-on if the input remains ON. Bit 2 - indicates the fault condition for an output-to-supply short (shorted load). A small value of resistance (~0.01Ω) in the source-to-ground line of the output stage is used to sense the output short. A comparator senses the voltage level and filters the output to provide an input to the control stage and to the diagnostic register. The control state directly shuts down the output when an over-current condition is sensed. Under this condition of fault, the input driver is latched off. To restore the output drive, the short must be removed and the input toggled OFF and then ON. A short to the supply is the only error condition that requires an input toggle reset. Bit 3 - indicates the condition of an output to ground short. As shown in the Functional Block Diagram, each output stage has drain-to-supply (VCC1) and drain-to-ground pullup and pull-down resistors of approximately 10kΩ to sense this condition. When the output is off and the sense level is low, an output-to-ground short is detected by the comparator. This condition is sensed when the output is pulled lower than 0.24xVCC (typical). Bit 4 - indicates the condition of an open load on the output. The same divider noted for Bit 3 is used to set the output level. If the sense level is at or near the mid-range of the voltage supply, VCC1 when the output is in the off condition, a no-load condition is detected. TABLE 1. SERIAL REGISTER DATA SEQUENCE CHANNEL NO. Switch Channel 1 BIT NO. 1 2 3 4 Switch Channel 2 5 6 7 8 Switch Channel 3 9 10 11 12 Switch Channel 4 13 14 15 16 FAULT FUNCTION Over-Temperature Short to Supply Short to Ground Open Load Over-Temperature Short to Supply Short to Ground Open Load Over-Temperature Short to Supply Short to Ground Open Load Over-Temperature Short to Supply Short to Ground Open Load FAULT SYMBOL OT1 SB1 SG1 OI1 OT2 SB2 SG2 OI2 OT3 SB3 SG3 OI3 OT4 SB4 SG4 OI4 Serial Peripheral Interface Bus Control Technically, the HIP0080 and HIP0081 fault data has only 16 bits. Except for the Error Flag, DF data bit shown in Figure 2, the format matches that of a normal CPOL = 0, CPHA = 1 SPI protocol (polarities, phase, etc). The DF bit from the DO output is active only until the clock starts. The best way to take advantage of it (if desired) is to connect the DO to the SPI bus, and also to a port pin, or other logic input. After CS goes low and before the SPI clocks starts, the DF bit can be read. If it is a zero, then the rest of the data does not have to be read. (The data will be all 0’s = no errors). If the DF bit = 1, then the data must be read to find out which bit(s) is set. Multiple ICs can be cascaded such that an error bit on any IC will daisy chain up to the last DO; this allows the microcontroller to “wire-OR” all of the devices automatically. Other than bidirectional data IC types, different IC types may be cascaded. The HIP0080 or HIP0081 should be closest to the microcontroller to use the DF bit feature. ICs that do not have an OR’ed means of passing fault bit would require all data be clocked to check the diagnostic bits. Clamp Energy Ratings for the HIP0080 and HIP0081 Figures 4 and 5 define the Single Pulse Energy ratings for the HIP0080 and HIP0081. Refer to Application Note AN9416 for further information on Single Pulse Energy ratings for inductive load operation and Dissipation capability for the 15 pin Power SIP Package. The Device Under Test conducts when the zener over voltage clamp turns on the output. While drain-to-source voltage, VDS and drain current, ID are monitored, the current drive pulse width, tON in seconds is varied to determine the Single Pulse Energy capability. The energy in Joules is calculated from the following equation: Single Pulse Energy = VDS x ID x tON . Refer to Application Note 9416 for further information on Single Pulse Energy ratings for inductive load operation and Dissipation capability for the 15 pin Power SIP Package. 7 HIP0080, HIP0081 4 OUTPUTS AND 4 BITS PER OUTPUT 4 POR CLK CS RESET LOGIC 4 4 4 U3 1 (EXT. PULL-UP WITH LOAD) 5V 5kΩ Q U6 U7 U8* 50pF 16-BIT PARALLEL 16 DIAG. DATA REG. 16 DI 16-BIT SERIAL ERROR DIAG. DATA REG. FLAG BIT R U4 DO U1 U2 GATE S U5 U9 U8* FIGURE 1. DIAGNOSTIC INTERFACE LOGIC DI SHIFT REGISTER CS GATE CLK START OF 16 DIAGNOSTIC DATA BITS GATE DI SHIFT REGISTER DO IC1 DO DI GATE IC2 DO DI SHIFT REGISTER DF OT1 SB1 SG1 OI1 OT2 SB2..... GATE IC3 DO ERROR FLAG BIT FIGURE 2. DATA AND CLOCK TIMING FIGURE 3. CASCADED CHIP OPERATION TO READ DIAGNOSTIC DATA 8 HIP0080, HIP0081 10000 HIP0081 SINGLE PULSE ENERGY vs TIME TAMB = 25oC PULSE ENERGY (mJ) AR EA FE OP ER AT IN HIP0080 SINGLE PULSE ENERGY vs TIME TAMB = 25oC PULSE ENERGY (mJ) 10000 NOTE: SAFE OPERATING AREA BELOW DOTTED LINE NOTE: SAFE OPERATING AREA BELOW DOTTED LINE G 1000 SA 100 0.1 FE O 1 10 100 1000 100 0.1 1 10 SA R PE I AT NG AR EA 1000 100 1000 PULSE WIDTH TIME (ms) PULSE WIDTH TIME (ms) FIGURE 4. SINGLE PULSE ENERGY TEST SHOWING THE FAILURE BOUNDARY FOR EACH HIP0080 OUTPUT STRESSED TO POINT OF FAILURE FIGURE 5. SINGLE PULSE ENERGY TEST SHOWING THE FAILURE BOUNDARY FOR EACH HIP0081 OUTPUT STRESSED TO POINT OF FAILURE Dissipation In Multiple Outputs The HIP0080 and HIP0081 Power Drivers have multiple MOS Output Drivers and require special consideration with regard to maximum current and dissipation ratings. While each output has a maximum current specification consistent with the device structure, all such devices on the chip can not be simultaneously rated to the same high level of peak current. The total combined current and the dissipation on the chip must be adjusted for maximum allowable ratings, given simultaneous multiple output conditions. For the HIP0081, the maximum positive output current rating is 2.2A when one output is ON. When ALL outputs are ON, the rating is reduced to 1.5A because the total maximum current is limited to 6A. For any given application, all output drivers on a chip may or may not have a different level of loading. The discussion here is intended to provide relatively simple methods to determine the maximum dissipation and current ratings as a general solution and, as a special solution, when all switched ON outputs have the same current loading. This expression sums the dissipation, Pk of each output driver without regard to uniformity of dissipation in each MOS channel. The dissipation loss in an NMOS channel is given in Equation 2 where the current, I, is determined by the output load when the channel is turned ON. The channel resistance, rDS(ON) is a function of the circuit design, level of gate voltage and the chip temperature. Other switching losses may include I2R lost in the interconnecting metal on the chip and bond wires of the package. P k = I × r DS ( ON ) 2 (EQ. 2) The temperature rise in the package due to the dissipation is the product of the dissipation, PD and the thermal resistance, θJC of the package (Junction-to-Case). To determine the chip junction temperature, TJ , given the case (heat sink tab) temperature, TC , the linear heat flow solution is: T J = T C + P D × θ JC (EQ. 3) General Solution A general equation for dissipation should specify that the total power dissipation in a package is the sum of all significant elements of dissipation on the chip. However, in Power BiMOS Circuits very little dissipation is needed to control the logic and predriver circuits on the chip. The overall chip dissipation is primarily the sum of the I2R dissipation losses in each channel where the current, I is the output current and the resistance, R is the NMOS channel resistance, rDS(ON) of each output driver. As such, the total dissipation, PD for n output drivers is: = or: T C = T J – P D × θ JC (EQ. 3A) ∑ k=1 n Since this solution relates only to the package, further consideration must be given to a practical heat sink. The equation of linear heat flow assumes that the thermal resistance from Junction-to-Ambient (θJA) is the sum of the thermal resistance from Junction-to-Case and the thermal resistance from Case (heat sink)-to-Ambient. The Junctionto-Ambient thermal resistance, θJA is the sum of all thermal paths from the chip junction to the ambient temperature (TA) environment and can be expressed as: θ JA = θ JC + θ CA (EQ. 4) Pk (EQ. 1) 9 HIP0080, HIP0081 The Junction-to-Ambient equivalent to Equation 3, 3A is: T J = T A + P D × θ JA (EQ. 5) TA = 150oC - 1.5W x 30oC/W = 105oC. Equal Current Loading Solution Many applications may have equal current loading in the output drivers with equal saturated turn ON and temperature conditions. As such, a convenient method to show rating boundaries is to substitute the dissipation Equation 2 into the junction temperature Equation 3. For m outputs that are ON and conducting with equal currents, where I = I1 = I2 ..... = Im, we have the following solution for dissipation: P D = m × P k = m × I × r DS ( ON ) TJ – TC ------------------------------------------------m × θ JC × r DS ( ON ) 2 or: T A = T J – P D × θ JA (EQ. 5A) Not all Integrated Circuit packages have a directly definable case temperature because the heat is spread through the lead frame to a PC Board which is the effective heat sink. Calculation Example 1 For the HIP0081, θJC = 3oC/W and the worst case junction temperature, as an application design solution, should not exceed 150oC. For a given application, Equation 1 determines the dissipation, PD. Assume the package is mounted to a heat sink having a thermal resistance of 6oC/W and, for a given application, assume the dissipation is 3W and the ambient temperature (TA) is 100oC. From Equation 4, θJA is 9oC/W. The solution for junction temperature (TC) by Equation 3 is: TJ = 100oC + 3W x 9oC/W = 127oC. (EQ. 6) I= (EQ. 7) The number of output drivers ON and conducting (m) may be from 1 to n. (i.e., For all four output drivers of the HIP0081 ON, m = 4.) Maximum temperature, dissipation and current ratings must be observed. For a defined number of conducting Power MOS Output Drivers, we can plot the results for m devices showing I vs TC . Given the HIP0081 as an example, Figures 6 and Figure 7 illustrate the boundaries for temperature and current. Figure 6 shows the maximum current for a single output ON while Figure 7 shows the maximum current for all four outputs ON with equal current plotted versus Case Temperature, TC . Boundary conditions relate to the Absolute Maximum Ratings as defined in the Data Sheet. Calculation Example 2: Assume for the HIP0080, θJA = 30oC/W mounted on a PC Board with good heat sinking characteristics. Again, the worst case junction temperature, as an application design solution, should not exceed 150oC. Assume from the application, based on Equation 1, the dissipation, PD = 1.5W. The maximum junction temperature is known and can be used to determine the maximum allowable ambient temperature from Equation 5A as follows: MAX. DRIVER OUTPUT CURRENT SINGLE OUTPUT ON (A) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 50 75 100 CASE (HEAT SINK TAB) TEMPERATURE (oC) 125 150 (1) (2) CURVE (1): rDS(ON) = 1Ω CURVE (2): rDS(ON) = 0.5Ω THERMAL RESISTANCE, θJC = 3oC/W MAX. +IOUT(DC) FIGURE 6. HIP0081 MAXIMUM SINGLE OUTPUT CURRENT vs CASE (TAB) TEMPERATURE 10 HIP0080, HIP0081 MAX. DRIVE CURRENT, ALL OUTPUTS ON (WITH EQUAL CURRENT) (A) 2.0 1.5 MAX. ALL ON CURRENT LIMIT (EQUAL CURRENT) (3) (4) CURVE (3): rDS(ON) = 1Ω CURVE (4): rDS(ON) = 0.5Ω THERMAL RESISTANCE, θJC = 3oC/W 0.0 50 75 100 CASE (HEAT SINK TAB) TEMPERATURE (oC) 125 150 1.0 0.5 FIGURE 7. HIP0081 CURRENT vs CASE (TAB) TEMPERATURE, ALL OUTPUTS ON WITH EQUAL CURRENT 16 14 DISSIPATION WATTS (W) 12 10 8 6 4 2 0 -50 -25 0 25 HIP0081 WITH EXT. 6oC/W HEAT SINK (θJA = 9oC/W) HIP0081 WITH INFINITE HEAT SINK (θJC = θJA = 3oC/W) HIP0080 WITH θJA = 33oC/W (PC BOARDS AS HEAT SINK) 50 75 100 125 150 AMBIENT TEMPERATURE (oC) FIGURE 8. DISSIPATION DERATING CURVES 11 HIP0080, HIP0081 Single-In-Line Plastic Packages (SIP) D -XSEE TAB DETAIL A F Z15.05A (JEDEC MO-048 AB ISSUE A) 15 LEAD PLASTIC SINGLE-IN-LINE PACKAGE STAGGERED VERTICAL LEAD FORM INCHES SYMBOL MIN 0.172 0.024 0.014 0.778 0.684 0.416 MAX 0.182 0.031 0.024 0.798 0.694 0.426 MILLIMETERS MIN 4.37 0.61 0.36 19.76 17.37 10.57 MAX 4.62 0.79 0.61 20.27 17.63 10.82 E E1 -YL1 A B C TERMINAL N 3 L H L -Z- D E E1 E2 e e1 e2 e1 e2 e3 F L L1 N R1 TERMINAL #1 0.110 BSC 0.050 BSC 0.200 BSC 0.169 BSC 0.700 BSC 0.057 0.150 0.690 15 0.148 0.065 0.152 0.080 0.063 0.176 0.710 2.79 BSC 1.27 BSC 5.08 BSC 4.29 BSC 17.78 BSC 1.45 3.81 17.53 15 3.76 1.65 3.86 2.03 Rev. 1 4/98 1.60 4.47 18.03 e e3 B C LLLLLLL HHHHHHHH 0.010(0.25) M Z ØP XM YM 0.024(0.61) M TYP ALL LEADS Z Ø 0.015(0.38) M Z XS ØP R1 E2 TAB DETAIL NOTES: 1. Refer to series symbol list, JEDEC Publication No. 95. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1982. 3. N is the number of terminals. 4. Controlling dimension: INCH. 12 HIP0080, HIP0081 Single-In-Line Plastic Packages (SIP) -ZD ØP E2 -XA F Z15.05B 15 LEAD PLASTIC SINGLE-IN-LINE PACKAGE SURFACE MOUNT “GULLWING” LEAD FORM INCHES SYMBOL A E MILLIMETERS MIN 4.37 0.61 0.46 19.76 17.37 10.57 MAX 4.62 0.79 0.61 20.27 17.63 10.82 2.79 BSC 1.27 BSC 17.78 BSC 1.45 1.66 2.49 15 1.60 2.03 2.74 MIN 0.172 0.024 0.018 0.778 0.684 0.416 MAX 0.182 0.031 0.024 0.798 0.694 0.426 B C E1 R1 -Y- D E E1 E2 e 0.110 BSC 0.050 BSC 0.700 BSC 0.057 0.065 0.098 15 0.148 0.065 0.152 0.080 3.76 1.65 0.063 0.080 0.108 e 0.010 M B TYP Z XS YM C 15 SURFACES 0.004 0.008 Z (NOTE 3) e3 F L L1 N ØP 15 LEAD TIPS e3 3.86 2.03 0o- 8o R1 L L1 HEADER BOTTOM BOTTOM VIEW Rev. 1 11/97 NOTES: 1. Dimensioning and Tolerancing per ANSI Y14.5M - 1982. 2. N is the number of terminals. 3. All lead surfaces are within 0.004 inch of each other. No lead can be more than 0.004 inch above or below the header plane, ( -Z- Datum). 4. Controlling dimension: INCH. 0.814 0.407 C OF 0.150 L LAND PATTERN 0.130 0.700 0.662 0.774 0.050 TYP 0.030 TYP 0.350 0.700 13 HIP0080, HIP0081 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER C L 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP N28.45 (JEDEC MS-018AB ISSUE A) 0.004 (0.10) C 28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL A A1 MIN 0.165 0.090 0.485 0.450 0.191 0.485 0.450 0.191 28 MAX 0.180 0.120 0.495 0.456 0.219 0.495 0.456 0.219 MILLIMETERS MIN 4.20 2.29 12.32 11.43 4.86 12.32 11.43 4.86 28 MAX 4.57 3.04 12.57 11.58 5.56 12.57 11.58 5.56 NOTES 3 4, 5 3 4, 5 6 Rev. 2 11/97 0.025 (0.64) R 0.045 (1.14) D2/E2 C L E1 E D2/E2 VIEW “A” D D1 D2 E E1 E2 N D1 D 0.020 (0.51) MAX 3 PLCS A1 A 0.020 (0.51) MIN SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53) 0.045 (1.14) MIN 0.025 (0.64) MIN VIEW “A” TYP. NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. 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