HIP1011A

® HIP1011A Data Sheet November 16, 2004 FN4631.5 PCI Hot Plug Controller The HIP1011A is the second PCI Hot Plug Voltage bus control IC from Intersil. A drop-in alternative to the widely used HIP1011, the HIP1011A has the same form, fit and function but additionally features an adjustable latch-off time of the MOSFET switches and fault reporting. Like the HIP1011, the HIP1011A creates a small and simple yet complete power control solution with discrete power MOSFETs and a few passive components. Four independent supplies are controlled, +5V, +3.3, +12V, and -12V. The +12V and -12V switches are integrated. For the +5V and +3.3V supplies, overcurrent (OC) protection is provided by sensing the voltage across external currentsense resistors. For the +12V and -12V supplies OC protection is provided internally. In addition, an on-chip reference is used to monitor the +5V, +3.3V and +12V outputs for undervoltage (UV) conditions. The PWRON input controls the state of the switches. During an OC condition on any output, or a UV condition on the +5V, +3.3V or +12V outputs, a LOW (0V) is asserted on the FLTN output and all MOSFETs are latched-off. The time to FLTN signal going LOW and MOSFET latch-off is determined by a single capacitor from the FLTN pin to ground. This added feature allows the system OS to complete housekeeping activities in preparation for an unplanned shut down of the affected card. The FLTN latch is cleared when the PWRON input is toggled low again. During initial power-up of the main VCC supply (+12V), the PWRON input is inhibited from turning on the switches, and the latch is held in the Reset state until the VCC input is greater than 10V. User programmability of the overcurrent threshold, fault reporting response time, latch-off response time and turn-on slew rate is provided. A resistor connected to the OCSET pin programs the OC threshold. A capacitor may be added to the FLTN pin to adjust both the delay time to reporting a fault and the latch-off of the supplies after an OC or UV event. Capacitors connected to the gate pins set the turn-on rate. In addition the HIP1011A has also been enhanced to tolerate spurious system noise. Features • Adjustable Delay Time for Turn-Off and Fault Reporting • Controls All PCI Supplies: +5V, +3.3V, +12V, -12V • Internal MOSFET Switches for +12V and -12V Outputs • µP Interface for On/Off Control and Fault Reporting • Adjustable Overcurrent Protection for All Supplies • Provides Fault Isolation • Adjustable Turn-On Slew Rate • Minimum Parts Count Solution • No Charge Pump • Pb-Free Available (RoHS Compliant) Applications • PCI Hot Plug • CompactPCI Ordering Information PART NUMBER HIP1011ACB HIP1011ACBZA (See Note) HIP1011ACB-T HIP1011ACBZA-T (See Note) TEMP. RANGE (oC) 0 to 70 0 to 70 0 to 70 0 to 70 PACKAGE 16 Ld SOIC 16 Ld SOIC (Pb-free) Tape and Reel Tape and Reel (Pb-free) PKG. DWG. # M16.15 M16.15 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. Pinout HIP1011A (SOIC) TOP VIEW M12VIN FLTN 3V5VG VCC 12VIN 3VISEN 3VS OCSET 1 2 3 4 5 6 7 8 16 M12VO 15 M12VG 14 12VG 13 GND 12 12VO 11 5VISEN 10 5VS 9 PWRON 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2000, 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HIP1011A Typical Application 3.3V, 7.6A OUT 3.3V INPUT ITF86130SK8T 5mΩ, 1% 12V, 0.5A OUT -12V, 0.1A OUT 5V, 5A OUT 5mΩ, 1% 5V INPUT ITF86130SK8T -12V INPUT HIP1011A M12VIN FLTN 3V5VG VCC 12VIN 3VISEN 3VS OCSET 6.04kΩ 1% M12VO M12VG 12VG GND 12VO 5VISEN 5VS PWRON 0.033µF 0.033µF 0.033µF 12V INPUT (OPTIONAL) POWER CONTROL INPUT NOTE: All capacitors are ±10%. FAULT OUTPUT (ACTIVE LOW) Simplified Schematic SET (LOW = FAULT) 5VREF FAULT LATCH LOW = FAULT COMP + 4.6V FLTN INHIBIT RESET COMP + 2.9V VCC VCC VCC 5V ZENER REFERENCE 5VREF INHIBIT COMP + 10.8V VOCSET/17 COMP + + - INHIBIT 5VS VCC 3V5VG VCC 12VIN POWER-ON RESET LOW WHEN VCC < 10V COMP + VCC 100µA OCSET VCC PWRON VOCSET HIGH = FAULT HIGH = SWITCHES ON COMP + VOCSET/3.3 + 0.7Ω 12VO M12VIN COMP VOCSET/0.8 + VCC 12VG 0.3Ω VOCSET/13.3 + - 5VISEN 3VS 3VISEN 12VIN + GND - 2 M12VIN M12VG M12VO FN4631.5 November 16, 2004 HIP1011A Pin Descriptions PIN NO. 1 2 3 4 5 6 7 8 DESIGNATOR M12VIN FLTN 3V5VG VCC 12VIN 3VISEN 3VS OCSET FUNCTION -12V Input Fault Output 3.3V/5V Gate Output 12V VCC Input 12V Input 3.3V Current Sense 3.3V Source Overcurrent Set DESCRIPTION -12V Supply Input. Also provides power to the -12V overcurrent circuitry. 5V CMOS Fault Output; LOW = FAULT. A capacitor may be placed from this pin to ground to provide delay time to fault notification and power supply latch-off. Drive the gates of the 3.3V and 5V MOSFETs. Connect a capacitor to ground to set the startup ramp. During turn on, this capacitor is charged with a 25µA current source. Connect to unswitched 12V supply. Switched 12V supply input. Connect to the load side of the current sense resistor in series with source of external 3.3V MOSFET. Connect to source of 3.3V MOSFET. This connection along with pin 6 (3VISEN) senses the voltage drop across the sense resistor. Connect a resistor from this pin to ground to set the overcurrent trip point of all four switches. All four over current trips can be programmed by changing the value of this resistor. The default (6.04kΩ, 1%) is compatible with the maximum allowable currents as outlined in the PCI specification. Controls all four switches. High to turn switches ON, Low to turn them OFF. Connect to source of 5V MOSFET switch. This connection along with pin 11 (5VISEN) senses the voltage drop across the sense resistor. Connect to the load side of the current sense resistor in series with source of external 5V MOSFET. Switched 12V output. Connect to common of power supplies. 9 10 11 12 13 14 PWRON 5VS 5VISEN 12VO GND 12VG Power On Control 5V Source 5V Current Sense Switched 12V Output Ground Gate of Internal PMOS Connect a capacitor between 12VG and 12VO to set the start up ramp for the +12V supply. This capacitor is charged with a 25µA current source during start-up. The UV circuitry is enabled after the voltage on 12VG is less than 400mV. Therefore, if the capacitor on the pin 3 (3V5VG) is more than 25% larger than the capacitor on pin 14 (12VG) a false UV may be detected during start up. Gate of Internal NMOS Connect a capacitor between M12VG and M12VO to set the start up ramp for the M12V supply. This capacitor is charged with 25µA during start up. Switched -12V Output Switched 12V Output. 15 16 M12VG M12VO 3 FN4631.5 November 16, 2004 HIP1011A Absolute Maximum Ratings VCC, 12VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +14.0V 12VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V12VIN +0.5V 12VO, 12VG, 3V5VG . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V M12VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15.0V to +0.5V M12VO, M12VG . . . . . . . . . . . . . . . . . . . . . . VM12VIN-0.5V to +0.5V 3VISEN, 5VISEN . . . . . . . . . . . -0.5V to the Lesser of VCC or +7.0V Voltage, Any Other Pin. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V 12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3A M12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8A ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4KeV (HBM) Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .125oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Die Characteristics Number of Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 Operating Conditions VCC Supply Voltage Range. . . . . . . . . . . . . . . . . . +10.8V to +13.2V ±12V, 5V and 3.3V Input Supply Tolerances . . . . . . . . . . . . . . . . ±10% 12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +0.5A M12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +0.1A Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief 379 for details. 2. All voltages are relative to GND, unless otherwise specified. Electrical Specifications PARAMETER 5V / 3.3V SUPPLY CONTROL 5V Overcurrent Threshold 5V Overcurrent Threshold Voltage 5V Overcurrent Threshold Voltage 5V Undervoltage Trip Threshold Nominal 5.0V and 3.3V Input Supply Voltages, VCC = 12VIN = 12V, M12VIN = -12V, TA = TJ = 0 to 70oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS IOC5V VOC5V_1 VOC5V_2 V5VUV t5VUV tON5V IB5VS IB5VISEN IOC3V VOC3V_1 VOC3V_2 V3VUV t3VUV tON3V IB3VS IB3VISEN Vout_lo_35VG Vout_hi_35VG IC3V5VG See Typical Application Diagram VOCSET = 0.6V VOCSET = 1.2V 30 66 4.42 - 7.1 36 72 4.65 150 6.5 -26 -140 9.0 49 95 2.86 150 6.5 -26 -140 0.1 11.1 25.0 42 79 4.75 350 -20 -110 56 102 2.97 350 -20 -110 0.4 27.5 A mV mV V ns ms µA µA A mV mV V ns ms µA µA V V µA 5V Undervoltage Fault Response Time 5V Turn-On Time (PWRON High to 5VOUT = 4.75V) 5VS Input Bias Current 5VISEN Input Bias Current 3V Overcurrent Threshold 3V Overcurrent Threshold Voltage 3V Overcurrent Threshold Voltage 3V Undervoltage Trip Threshold 3V Undervoltage Fault Response Time 3V Turn-On Time (PWRON High to 3VOUT = 3.00V) 3VS Input Bias Current 3VISEN Input Bias Current 3V5VG Vout Low 3V5VG Vout High Gate Output Charge Current C3V5VG = 0.022µF, C5VOUT = 2000µF, RL = 1Ω PWRON = High PWRON = High See Typical Application Diagram VOCSET = 0.6V VOCSET = 1.2V -40 -160 42 88 2.74 - C3V5VG = 0.022µF, C3VOUT = 2000µF, RL = 0.43Ω PWRON = High PWRON = High PWRON = Low, FLTN = Low PWRON = High, FLTN = High PWRON = High, V3V5VG = 2V -40 -160 10.5 22.5 4 FN4631.5 November 16, 2004 HIP1011A Electrical Specifications PARAMETER Gate Turn-On Time (PWRON High to 3V5VG = 11V) Gate Turn-Off Time Gate Turn-Off Time +12V SUPPLY CONTROL On Resistance of Internal PMOS Overcurrent Threshold Overcurrent Threshold 12V Undervoltage Trip Threshold Undervoltage Fault Response Time Gate Charge Current Turn-On Time (PWRON High to 12VG = 1V) Turn-Off Time Turn-Off Time -12V SUPPLY CONTROL On Resistance of Internal NMOS Overcurrent Threshold Overcurrent Threshold Gate Output Charge Current Turn-On Time (PWRON High to M12VG = -1V) Turn-On Time (PWRON High to M12VO = -10.8V) Turn-Off Time Turn-Off Time M12VIN Input Bias Current CONTROL I/O PINS Supply Current OCSET Current Overcurrent to Fault Response Time Overcurrent to Fault Response Time Overcurrent to Fault Response Time PWRON Threshold Voltage FLTN Output Low Voltage FLTN Output High Voltage FLTN Output Latch Threshold 12V Power On Reset Threshold VTHPWRON VFLTN,OL VFLTN,OH VFLTN,TH VPOR,TH VCC Voltage Falling IFLTN = 2mA IFLTN = 0 to -4mA IVCC IOCSET tOC FLTN Cap = 100pF FLTN Cap = 1000pF FLTN Cap = 10µF 4 95 0.8 3.9 1.45 9.4 5 100 500 2200 30 1.6 0.6 4.3 1.8 10 5.8 105 960 2.1 0.9 4.9 2.25 10.6 mA µA ns ns µs V V V V V IBM12VIN rDS(ON)M12 IOC12V_1 IOC12V_2 ICM12VG tONM12V tONM12V tOFFM12V PWRON = High, ID = 0.1A, TA = TJ = 25oC VOCSET = 0.6V VOCSET = 1.2V PWRON = High, V3VG = -4V CM12VG = 0.022µF CM12VG = 0.022µF, CM12VO = 50µF, RL = 120Ω CM12VG = 0.1µF, M12VG CM12VG = 0.022µF, M12VG Falling 90% to 10% PWRON = High 0.5 0.15 0.30 22.5 0.7 0.18 0.37 25 160 16 18 3 2 0.9 0.25 0.50 27.5 300 23 2.6 Ω A A µA µs ms µs µs mA rDS(ON)12 IOC12V_1 IOC12V_2 V12VUV t12VUV IC12VG tON12V tOFF12V PWRON = High, V12VG = 3V C12VG = 0.022µF C12VG = 0.1µF, 12VG C12VG = 0.022µF, 12VG Rising 10% - 90% PWRON = High, ID = 0.5A, TA = TJ = 25oC VOCSET = 0.6V VOCSET = 1.2V 0.18 0.6 1.25 10.5 23.5 0.3 0.75 1.50 10.8 150 25.0 16 9 3 0.35 0.9 1.8 11.15 28.5 20 12 Ω A A V ns µA ms µs µs Nominal 5.0V and 3.3V Input Supply Voltages, VCC = 12VIN = 12V, M12VIN = -12V, TA = TJ = 0 to 70oC, Unless Otherwise Specified (Continued) SYMBOL tON3V5V tOFF3V5V TEST CONDITIONS C3V5VG = 0.1µF C3V5VG = 0.1µF, 3V5VG from 9.5V to 1V C3V5VG = 0.022µF, 3V5VG Falling 90% to 10% MIN TYP 280 13 2 MAX 500 17 UNITS µs µs µs 5 FN4631.5 November 16, 2004 HIP1011A Typical Performance Curves 340 1000 4.632 4.631 PMOS rON +12 (mΩ) NMOS rON -12 (mΩ) 320 NMOS -12 rON 900 4.630 4.629 4.628 4.627 260 0 5 600 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (oC) 4.626 0 2.858 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (oC) 3.3 UV 2.859 2.860 2.862 5 UV 3.3V UVTRIP (V) 70 2.861 300 PMOS +12 rON 280 800 700 FIGURE 1. rON vs TEMPERATURE 5V UVTRIP (V) FIGURE 2. UV TRIP vs TEMPERATURE 10.84 100 90 12 UV TRIP (V) OC Vth (mV) 10.83 3V OCVth 80 5V OCVth 70 10.82 10.81 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (oC) 60 0 5 10 15 20 25 30 35 40 45 50 55 60 65 TEMPERATURE (oC) FIGURE 3. 12 UV TRIP vs TEMPERATURE FIGURE 4. OC Vth vs TEMPERATURE (VROCSET = 1.21V) 102 101 IOC SET (mA) 100 99 98 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (oC) FIGURE 5. OCSET I vs TEMPERATURE 6 FN4631.5 November 16, 2004 HIP1011A Typical Performance Curves (Continued) 3V5VG 3V5VG FLTN FLTN FLTN 5V Iout 5V Iout VOLTAGE (2V / DIV) CURRENT (5A / DIV) TIME (1µs /DIV) VOLTAGE (2V / DIV) CURRENT (5A / DIV) TIME (1µs /DIV) FIGURE 6. FLTN, 3V5VG RESPONSE TO OC, FLTN = 100pF FIGURE 7. FLTN, 3V5VG RESPONSE TO OC, FLTN CAP = 0.001µF 3V5VG 3V5VG 5V Iout 5V Iout FLTN FLTN VOLTAGE (2V / DIV) CURRENT (5A / DIV) TIME (2µs /DIV) VOLTAGE (2V / DIV) CURRENT (5A / DIV) TIME (50µs /DIV) FIGURE 8. FLTN, 3V5VG RESPONSE TO OC, FLTN CAP = 0.01µF FIGURE 9. FLTN, 3V5VG RESPONSE TO OC, FLTN CAP = 1µF 10ms 1ms VG 100µs 10µs 1 µs 100ns 10ns 1ns 100pF 0.001µF 0.01µF 0.1µF 1 µF 10µF FIGURE 10. RESPONSE TIME vs FLTN CAP 7 FN4631.5 November 16, 2004 HIP1011A HIP1011A PCI Hot Plug Controller Key Feature Description and Operation A drop-in alternative to the widely used HIP1011, the HIP1011A additionally features an adjustable delay time to fault reporting and latch-off of the MOSFET switches. During an over current condition (OC) on any output, or an under voltage (UV) condition on the +5V, +3.3V or +12V outputs, a LOW (0V) is presented on the FLTN output and all MOSFETs are latched-off. A programmable delay time from an OC or UV event to the FLTN signal going LOW and MOSFET latch-off can be designed into the system by a single capacitor from the FLTN pin to ground. The addition of an increasingly larger capacitor value on the FLTN pin increases the time from the OC or UV occurrence to the start of the FLTN high to low transition. The capacitor also slows the falling ramp thus delaying reaching the FLTN latch threshold of ~2.4V. Once the FLTN latch voltage threshold is reached the HIP1011A then simultaneously shuts down all four supplies. This added feature enables the HIP1011A to ignore both transient UV and OC events to the extent of a single capacitor value in the system design. This feature also may allow the system OS to complete housekeeping activities in preparation for a possible unplanned shutdown of the affected card by receiving an early warning signal from the HIP1011A. (indicating a fault has occurred) and the start of the gate drive outputs latching off. The latch-off is initiated by the falling FLTN signal reaching the output latch threshold voltage, VFLTN, TH. Table 1 illustrates the effect of the FLTN capacitor on the response time. TABLE 1. RESPONSE TIME TABLE 0.001µF 3V5VG Response a 0.85µs 0.1µF 37µs 10µF 3.8ms VFLTN, TH FLTN a 3V5VG T1 T2 FIGURE 12. TIMING DIAGRAM Customizing and Optimizing Circuit Performance and Functionality HOW ADJUSTABLE IS THE FAULT REPORTING DELAY AND TIME TO POWER SUPPLY LATCH-OFF? Figure 12 illustrates the relationship between the FLTN signal and the gate drive outputs. Duration a, indicates the time between FLTN starting to transition from High to Low, 3.3V 7.6A OUT 3.3V INPUT 5mΩ 1% 12V 0.5A OUT CAN THE HIP1011A BE USED ON A CompactPCI BOARD? Yes, the HIP1011A can be used on a CompactPCI card application. See Technical Brief TB358. -12V 0.1A OUT 5V 5A OUT 5mΩ 1% 5V INPUT -12V INPUT HIP1011A M12VIN FLTN 3V5VG VCC 12VIN 3VISEN 3VS OCSET 6.04kΩ 1% M12VO M12VG 12VG GND 12VO 5VISEN 5VS PWRON 0.033µF 0.033µF 0.033µF 12V INPUT (SEE TABLE 1) POWER CONTROL INPUT NOTE: 3. All capacitors are ±±10%. FAULT OUTPUT (ACTIVE LOW) FIGURE 11. HIP1011A TYPICAL APPLICATION 8 FN4631.5 November 16, 2004 HIP1011A ARE THERE PCB LAYOUT DESIGN BEST PRACTICES TO FOLLOW? WHAT ARE THEY? As with most innovative ICs performing critical tasks there are crucial PCB layout best practices to follow for optimal performance. PCB traces that connect each end of the current sense resistors to the HIP1011A must not carry any load current. This can be accomplished by two dedicated PCB traces directly from the sense resistor to the HIP1011A, see examples of correct and incorrect layouts in Figure 13. inch SOICs. The typical application requires only 1.1 square inches of PCB board space. 0.75in 1.5in FIGURE 14. LAYOUT PLOT, ACTUAL SIZE (0.75in x 1.5in) CORRECT INCORRECT IS THERE A HIP1011A PCI HOT PLUG EVALUATION BOARD AVAILABLE? There is an evaluation board available through your local Intersil sales office. The HIP1011AEVAL1 board (Figure 15) is a simple board designed to demonstrate and evaluate the HIP1011A using an external PWRON signal simulating a PCI Hot Plug environment. The HIP1011AEVAL1 board comes in 2 parts, the mother board with the HIP1011A, MOSFETs with external components and a load board simulating a ‘typical’ PCI load with adequate space for modifying the existing load or to add an electronic load. Even with a number of available test points the HIP1011A implementation space is still very efficient. In addition, the demo board offers adequate space to evaluate the application note discussions found in AN9737. TO HIP1011A VS AND VISEN TO HIP1011A VS AND VISEN CURRENT SENSE RESISTOR FIGURE 13. SENSE RESISTOR LAYOUT Typical Applications: HIP1011A PCI Hot Plug Controller Introduction to HIP1011A and PCI Hot Plug Evaluation Board The HIP1011A is compatible with the PCI Hot Plug specification as it is derived from the widely used HIP1011. This device facilitates “HOT PLUGGING”, the removal or insertion of PCI compliant cards without the need to power down the server voltage bus. The HIP1011A controls all four, -12V, +12V, +3.3V, +5V supplies found in PCI applications, monitoring and protecting all against over current (OC) and the +12V, +3.3V, +5V for under voltage (UV) conditions. Reference the PCI Hot Plug specification available from www.pcisig.com. Figure 14 illustrates the PCB pattern for implementation of the HIP1011A with 4 power MOSFETs. Additional components for optimizing performance in particular applications, ambient electrical noise levels or desired features will be necessary. The ease of implementation of the HIP1011A and MOSFETs is complemented by the small PCB foot print necessary, since both are available in 0.150 9 FN4631.5 November 16, 2004 HIP1011A 3, 4, 5 TP8 TP4 3.3V INPUT R2 3.3VOUT BUS BOARD 2 TP6 1 TP7 12VOUT -12VOUT 9, 11, 12 TP5 5VOUT R1 TP11 5V INPUT 3.3V Q1, Q2 TP1 -12V INPUT TP2 HIP1011A M12VIN M12VO FLTN M12VG 3V5VG 12VG VCC GND 12VO 12VIN 3VISEN 5VISEN 5VS 3VS OCSET PWRON R3 R4 C4 INDICATES BANANA JACKS D1 JP2 5V 6 TP10 INDICATES EDGE CONNECTOR CARD INDICATES EDGE CONNECTOR SOCKET -12V CL4 Q3, Q4 C3 C1 C2 +12V CL3 RL4 CL1 RL2 5.0V CL2 RL3 7, 8, 10 TP9 GND LOAD BOARD RL1 VCC 12V INPUT TP3 JP1 PWRON IN FIGURE 15. HIP1011AEVAL1 Table 2 details the BOM for the HIP1011AEVAL1 board. TABLE 2. COMPONENT DESIGNATOR U1 Q1, Q2, Q3, Q4 R1, R2 C1, C2, C3 R3 C4 Conn. 1 R4 D1 JP1 JP2 RL1 RL2 RL3 RL4 CL1, CL2 CL3, CL4 COMPONENT NAME HIP1011ACB PCI Hot Plug Controller RF1K49211 RSENSE for 3.3V and 5V Supplies Gate Timing Capacitors Over Current Set Resistor Fault Stability Capacitor Connector for Load Card LED Series Resistor Fault Indicating LED VCC to Switched or Unswitched 12V Supply PWRON to 5V 3.3V Load Board Resistor 5.0V Load Board Resistor +12V Load Board Resistor -12V Load Board Resistor +3.3V and +5.0V Load Board Capacitor +12V and -12V Load Board Capacitor COMPONENT DESCRIPTION Intersil Corporation, HIP1011ACB PCI Hot Plug Controller Intersil Corporation, RF1K49211 7A, 12V, 20mΩ, Logic Level N-Channel MOSFET Dale, WSL-2512 10mΩ Metal Strip Resistor 0.033µF 805 Chip Capacitor 12.1kΩ 805 Chip Resistor 100pF 805 Chip Cap Sullins EZM06DRXH 4.7kΩ 805 Chip Resistor Red LED 0.01” Spaced Pins for Jumper Block 0.01” Spaced Pins for Jumper Block 1.1Ω , 10W 2.5Ω , 10W 47Ω , 5W 240Ω , 2W 2200µF 100µF 10 FN4631.5 November 16, 2004 HIP1011A Small Outline Plastic Packages (SOIC) N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45o 0.25(0.010) M BM M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 B MIN 0.053 0.004 0.014 0.007 0.386 0.150 MAX 0.069 0.010 0.019 0.010 0.394 0.157 MILLIMETERS MIN 1.35 0.10 0.35 0.19 9.80 3.80 MAX 1.75 0.25 0.49 0.25 10.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 1 02/02 L C D E e H h C 0.050 BSC 0.228 0.010 0.016 16 0o 8o 0.244 0.020 0.050 1.27 BSC 5.80 0.25 0.40 16 0o 6.20 0.50 1.27 e B 0.25(0.010) M C AM BS α µ A1 0.10(0.004) L N α NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN4631.5 November 16, 2004