HIP1012A

® HIP1012A Data Sheet March 2004 FN4419.6 Dual Power Distribution Controller The HIP1012A is a HOT SWAP dual supply power distribution controller. Two external N-Channel MOSFETs are driven to distribute power while providing load fault isolation. At turn-on, the gate of each external N-Channel MOSFET is charged with a 10µA current source. Capacitors on each gate (see the Typical Application Diagram), create a programmable ramp (soft turn-on) to control inrush currents. A built in charge pump supplies the gate drive for the 12V supply N-Channel MOSFET switch. Overcurrent protection is facilitated by two external current sense resistors. When the current through either resistor exceeds the user programmed value the controller enters the current regulation mode. The time-out capacitor, CTIM, starts charging as the controller enters the time out period. Once CTIM charges to a 2V threshold, the N-Channel MOSFETs are latched off. In the event of a fault at least three times the current limit level, the N-Channel MOSFET gates are pulled low immediately before entering time out period. The controller is reset by a rising edge on either PWRON pin. Choosing the voltage selection mode the HIP1012 controls either +12V/5V or +3.3V/+5V supplies. Features • HOT SWAP Dual Power Distribution Control for +5V and +12V or +5V and +3.3V • Provides Fault Isolation • Programmable Current Regulation Level • Programmable Time Out • Charge Pump Allows the Use of N-Channel MOSFETs • Power Good and Overcurrent Latch Indicators • Enhanced Overcurrent Sensitivity Available • Redundant Power On Controls • Adjustable Turn-On Ramp • Protection During Turn-On • Two Levels of Current Limit Detection Provide Fast Response to Varying Fault Conditions • Less Than 1µs Response Time to Dead Short • 3µs Response Time to 200% Current Overshoot • Pb-Free Package Option • Tape & Reel Packaging with ‘-T’ Part Number Suffix Ordering Information PART NUMBER HIP1012ACB HIP1012ACBZA (Note) TEMP. RANGE (°C) -0 to 70 -0 to 70 PACKAGE 14 Ld SOIC PKG. DWG. # M14.15 Applications • Redundant Array of Independent Disks (RAID) System • Power Distribution Control • Hot Plug, Hot Swap Components 14 Ld SOIC( Pb-free) M14.15 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. Pinout HIP1012A (SOIC) TOP VIEW 3/12VS 3/12VG VDD MODE/ PWRON1 PWRON2 5VG 5VS 1 2 3 4 5 6 7 14 3/12VISEN 13 RILIM 12 GND 11 CPUMP 10 CTIM 9 8 PGOOD 5VISEN Typical Application Diagram CPUMP RSENSE 12V OPTIONAL VDD RFILTER CFILTER CGATE RGATE HIP1012A 3/12VS 3/12VG VDD M/PON1 PWRON2 5VG 5VS 3/12VISEN RILIM GND CPUMP CTIM PGOOD 5ISEN RLOAD RILIM POWER ON INPUTS 5V CGATE RGATE CTIM 5V OR 3.3V RSENSE RLOAD 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Simplified Block Diagram 12VIN RSENSE TO LOAD 12VS OC CLIM + - R 100µA 2R 12V 12ISEN 10µA 2 12VG FALLING EDGE DELAY 18V CGATE 20Ω OPTIONAL VDD RFILTER CFILTER PWRON1 RISING EDGE RESET VDD R QN R Q S 20Ω CGATE 10µA 5VG PWRON2 12V ENABLE FALLING EDGE DELAY 5VS 5VIN + 3X RILIM RILIM ENABLE 18V POR GND ENABLE QPUMP 12V 10µA TO VDD CPUMP HIP1012A CPUMP 12V 3X + CLIM + OC R PGOOD 5ISEN HIP1012A OPTIONAL 2R + 2V CTIM CTIM + PGOOD OC LATCH RSENSE TO LOAD HIP1012A Pin Descriptions PIN # 1 2 SYMBOL 3V/12VS 3V/12VG FUNCTION 3.3 V/12V Source 3.3V/12V Gate DESCRIPTION Connect to source of associated external N-Channel MOSFET switch to sense output voltage. Connect to the gate of associated N-Channel MOSFET switch. A capacitor from this node to ground sets the turn-on ramp. At turn-on this capacitor will be charged to 17.4V by a 10µA current source when in 5v/12V mode of operation, otherwise capacitor will be charged to 11.4V. A small resistor (10 - 200Ω) should be placed in series with the gate capacitor to ground to prevent current oscillations. Connect to 12V supply. This can be either connected directly to the +12V rail supplying the load voltage or to a dedicated VDD +12V supply. If the former is chosen special attention to VDD decoupling must be paid. 3 VDD Chip Supply 4 MODE/ PWRON1 PWRON2 5 PWRON1 and PWRON2 are used to turn-on and reset the chip. Both outputs turn-on when Power ON/ Reset Invokes 3.3V operation either pin is driven low. After a current limit time out, the chip is reset by the rising edge of a when shorted to VDD, pin 3. reset signal applied to either PWRON pin. Each input has 100µA pull up capability which is compatible with 3V and 5V open drain and standard logic. PWRON1 is also used to invoke Power ON/ Reset 3.3V control operation in preference to +12V control. By tying pin 4 to pin 3 the charge pump is disabled and the UV threshold also shifts to 2.8V. 5V Gate Connect to the gate of the external 5V N-Channel MOSFET. A capacitor from this node to ground sets the turn-on ramp. At turn-on this capacitor will be charged to 11.4V by a 10µA current source. A small resistor (10 - 200Ω) should be placed in series with the gate capacitor to ground to prevent current oscillations. Connect to the source side of 5V external N-Channel MOSFET switch to sense output voltage. Connect to the load side of the 5V sense resistor to measure the voltage drop across this resistor between 5VS and 5VISEN pins. Indicates that all output voltages are within specification. PGOOD is driven by an open drain N-Channel MOSFET. It is pulled low when any output is not within specification. Connect a capacitor from this pin to ground. This capacitor controls the time between the onset of current limit and chip shutdown (current limit time-out). The duration of current limit time-out (in seconds) = 200kΩ x CTIM (Farads). Connect a 0.1µF capacitor between this pin and VDD (pin3). Directly connect this pin to VDD when in 3.3V control mode. 6 5VG 7 8 9 10 5VS 5VISEN PGOOD CTIM 5V Source 5V Current Sense Power Good indicator Current Limit Timing Capacitor Charge Pump Capacitor Chip Ground Current Limit Set Resistor 11 12 13 CPUMP GND RILIM A resistor connected between this pin and ground determines the current level at which current limit is activated. This current is determined by the ratio of the RILIM resistor to the sense resistor (RSENSE). The current at current limit onset is equal to 10µA x (RILIM/ RSENSE). Connect to the load side of sense resistor to measure the voltage drop across this resistor. 14 3V/12VISEN 3.3V/12V Current Sense 3 HIP1012A Absolute Maximum Ratings TA = 25°C VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +13.2V 3/12VG, CPUMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 18.5V 3/12VISEN, 3/12VS . . . . . . . . . . . . . . . . . . . . . . . -5V to VDD + 0.3V 5VISEN, 5VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5V to 7.5V PGOOD, RILIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7.5V MODE/PWRON1, PWRON2, CTIM, 5VG . . . . . -0.3V to VDD + 0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV (Class 2) Thermal Information Thermal Resistance (Typical, Note 1) θJA (°C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C (SOIC - Lead Tips Only) Operating Conditions VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . +10.5V to +13.2 Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. All voltages are relative to GND, unless otherwise specified. Electrical Specifications PARAMETER 12V CONTROL SECTION Current Limit Threshold Voltage (Voltage Across Sense Resistor) VDD = 12V, CVG = 0.01µF, CTIM = 0.1µF, RSENSE = 0.1Ω, CBULK = 220µF, ESR = 0.5Ω, TA = TJ = 0°C to 70°C, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VIL12V VIL12V 3XViL12V 3XVIL12V 20%iLrt 10%iLrt 1%iLrt RTSHORT tON12V ION12V 3XdisI 12VVUV V12VG RILIM =10kΩ RILIM = 5kΩ RILIM =10kΩ RILIM = 5kΩ 200% Current Overload, RILIM = 10kΩ, RSHORT = 6.0Ω 200% Current Overload, RILIM = 10kΩ, RSHORT = 6.0Ω 200% Current Overload, RILIM = 10kΩ, RSHORT = 6.0Ω C12VG = 0.01µF C12VG = 0.01µF C12VG = 0.01µF 12VG = 18V 92 47 250 100 8 0.5 10.5 100 53 300 165 2 4 10 500 12 10 0.75 10.8 17.3 108 59 350 210 1000 12 11.0 17.9 mV mV mV mV µs µs µs ns ms µA A V V 3X Current Limit Threshold Voltage (Voltage Across Sense Resistor) ±20% Current Limit Response Time (Current within 20% of Regulated Value) ±10% Current Limit Response Time (Current within 10% of Regulated Value) ±1% Current Limit Response Time (Current within 1% of Regulated Value) Response Time To Dead Short Gate Turn-On Time Gate Turn-On Current 3X Gate Discharge Current 12V Undervoltage Threshold Qpumped 12VG Voltage 3.3V/5V CONTROL SECTION Current Limit Threshold Voltage (Voltage Across Sense Resistor) 3X Current Limit Threshold Voltage (Voltage Across Sense Resistor) ±20% Current Limit Response Time (Current within 20% of regulated value) ±10% Current Limit Response Time (Current within 10% of Regulated Value) ±1% Current Limit Response Time (Current within 1% of Regulated Value) Response Time To Dead Short Gate Turn-On Time CPUMP = 0.1µF 16.8 VIL5V 3XVIL5V RILIM =10kΩ RILIM = 5kΩ RILIM =10kΩ RILIM = 5kΩ 200% Current Overload, RILIM = 10kΩ, RSHORT = 2.5Ω 200% Current Overload, RILIM = 10kΩ, RSHORT = 2.5Ω 200% Current Overload, RILIM = 10kΩ, RSHORT = 2.5Ω 92 47 250 100 - 100 53 300 155 2 4 10 500 5 108 59 350 210 - mV mV mV mV µs µs µs 800 ns ms RTSHORT tON5V CVG = 0.01µF CVG = 0.01µF 4 HIP1012A Electrical Specifications PARAMETER Gate Turn-On Current 3X Gate Discharge Current 5V Undervoltage Threshold 3.3V Undervoltage Threshold 3.3/5VG High Voltage VDD = 12V, CVG = 0.01µF, CTIM = 0.1µF, RSENSE = 0.1Ω, CBULK = 220µF, ESR = 0.5Ω, TA = TJ = 0°C to 70°C, Unless Otherwise Specified (Continued) SYMBOL ION5V 3XdisI 5VVUV 3.3VVUV 3/5VG TEST CONDITIONS CVG = 0.01µF CVG = 0.01µF, PWRON = Low MIN 8 0.5 4.35 2.65 11.2 TYP 10 0.75 4.5 2.8 11.9 MAX 12 4.65 2.95 UNITS µA A V V V SUPPLY CURRENT AND IO SPECIFICATIONS VDD Supply Current VDD POR Rising Threshold VDD POR Falling Threshold Current Limit Time-Out PWRON Pull-up Voltage PWRON Rising Threshold PWRON Hysteresis PWRON Pull-Up Current Current Limit Time-Out Threshold (CTIM) CTIM Charging Current CTIM Discharge Current CTIM Pull-Up Current RILIM Pin Current Source Output Charge Pump Output Current Charge Pump Output Voltage Charge Pump Output Voltage - Loaded Charge Pump POR Rising Threshold Charge Pump POR Falling Threshold TILIM PWRN_V PWR_Vth PWR_hys PWRN_I CTIM_Vth CTIM_I CTIM_disI CTIM_disI RILIM_Io Qpmp_Io Qpmp_Vo Qpmp_VIo Qpmp+Vth Qpmp-Vth CPUMP = 0.1µF, CPUMP = 16V No load Load current = 100µA VCTIM = 8V CTIM = 0.1µF PWRON pin open IVDD 4 9.5 9.3 16 1.8 1.1 0.1 60 1.8 8 1.7 3.5 90 320 17.2 16.2 15.6 15.2 8 10.0 9.8 20 2.4 1.5 0.2 80 2 10 2.6 5 100 560 17.4 16.7 16 15.7 10 10.7 10.3 24 3.2 2 0.3 100 2.2 12 3.5 6.5 110 800 16.5 16.2 mA V V ms V V V µA V µA mA mA µA µA V V V V HIP1012A Description and Operation The HIP1012A is a multifeatured dual power supply distribution controller, including programmable current limiting regulation and time to latch off. Additionally the HIP1012A operates both as a +3.3V and 5V or a +5V and +12V power supply controller with each mode having appropriate UnderVoltage (UV) fault notification levels. Upon initial power up HIP1012A can either isolate the voltage supply from the load by holding the external N-Channel MOSFET switches off or apply the supply rail voltage directly to the load for true hot swap capability. In either case the HIP1012A turns on in a soft start mode protecting the supply rail from sudden current loading. If either PWRON pin is pulled low the HIP1012A will be in true hot swap mode. Both PWRON pins must be high to turn off the HIP1012A thus isolating the power supply from the load through the external FETs. At turn-on, the gate capacitor of each external N-Channel MOSFET is charged with a 10µA current source. These capacitors create a programmable ramp (soft turn-on). A charge pump supplies the gate drive for the 12V supply switch driving that gate to 17V. The load currents pass through two external current sense resistors. When the voltage across either resistor exceeds the user programmed Overcurrent (OC) voltage threshold value, (see Table 1) the controller enters current regulation. At this time the time-out capacitor, CTIM, starts charging with a 10µA current source and the controller enters the time out period. The length of the time out period is set by the single external capacitor (see Table 2) placed from the CTIM pin (pin 10) to ground and is characterized by a lowered gate drive voltage to the appropriate external N-Channel MOSFET. Once CTIM charges to 2V, an internal comparator is tripped resulting in both N-Channel MOSFETs being latched off. 5 HIP1012A TABLE 1. RILIM RESISTOR 15kΩ 10kΩ 7.5kΩ 4.99kΩ NOTE: Nominal OC Vth = Rilim x 10µA. NOMINAL OC VTH 150mV 100mV 75mV 50mV and motor startup currents, choosing the current limiting level is crucial to provide both protection and still allow for this inrush current without latching off. Consider this in addition to the time out delay when choosing MOSFETs for your design. To these ends it is suggested that CR levels be programmed to 150% of nominal load. When using the HIP1012A in the 12V and 5V mode additional VDD decoupling may be necessary to prevent a power on reset due to a sag on VDD pin upon an OC latch off. The addition of a capacitor from VDD to GND may often be adequate but a small value isolation resistor may also be necessary (see the Simplified Block Diagram on page 2). Current loop stabilization is facilitated through a small value resistor in series with the gate timing capacitor. As the HIP1012A drives a highly inductive current load, instability characterized by the gate voltage repeatedly ramping up and down may appear. A simple method to enhance stability is provided by the substitution of a larger value gate resistor. Typically this situation can be avoided by eliminating long point to point wiring to the load. Random resets occur if the HIP1012A sense pins are pulled below ground when turning off a highly inductive load. Place a large load capacitor (10-50µF) on the output or ISEN clamping diodes to ground to eliminate. During the Time Out delay period with the HIP1012A in current limit mode, the VGS of the external N-Channel MOSFETs is reduced driving the N-Channel MOSFET switch into a high rDS(ON) state. Thus avoid extended time out periods as the external N-Channel MOSFETs may be damaged or destroyed due to excessive internal power dissipation. Refer to the MOSFET manufacturer’s data sheet for SOA information. External Pull Down resistors from the xISEN pins to ground will prevent the voltage outputs from floating up due to leakage current through the external switch FET body diode when the FETs are disabled and the outputs are open. Physical layout of Rsense resistors is critical to avoid the possibility of false overcurrent occurrences. Ideally trace routing between the Rsense resistors and the HIP1012A is direct and as short as possible with zero current in the sense lines as shown below. CORRECT INCORRECT TABLE 2. CTIM CAPACITOR 0.022µF 0.047µF 0.1µF NOMINAL TIME OUT PERIOD 4.4ms 9.4ms 20ms NOTE: Nominal time-out period in seconds = CTIM x 200kΩ. The HIP1012A responds to a load short (defined as a current level 3X the OC set point) immediately, driving the relevant N-Channel MOSFET gate to 0V in less than 10µs. The gate voltage is then slowly ramped up turning on the N-Channel MOSFET to the programmed current limit level; this is the start of the time out period. The programmed current level is held until either the OC event passes or the time out period expires. If the former is the case then the N-Channel MOSFET is fully enhanced and the CTIM charging current is diverted away from the capacitor. If the time out period expires prior to OC resolution then both gates are quickly pulled to 0V turning off both N-Channel MOSFETs simultaneously. Upon any UV condition the PGOOD signal will pull low when tied high through a resistor to the logic supply. This pin is a fault indicator but not the OC latch off indicator. For an OC latch off indication, monitor CTIM, pin 10. This pin will rise rapidly to 12V once the time out period expires. See Simplified Block Diagram on page 2 for OC latch off circuit suggestion. The HIP1012A is reset by a rising edge on either PWRON pin and is turned on by either PWRON pin being driven low. The HIP1012A can control either +12V/5V or +3.3V/+5V supplies. Tying the PWRON1 pin to VDD , invokes the +3.3V/+5V voltage mode. In this mode, the external charge pump capacitor is not needed and Cpump, pin 11 is tied directly to VDD . HIP1012A Application Considerations Current Regulation vs current trip often causes confusion when using this and other ICs with a Current Regulation (CR) feature. The CR level is the level at which the HIP1012 will hold an overcurrent load for the programmed duration. This level is programmable by the RLIM and RSENSE resistors values. As the current being monitored by the HIP1012A approaches a level >85% of the CR level the HIP1012A may trip-off due to variances in manufacturing and the design of the low gain high speed input comparators. In addition with the high levels of inrush current e.g., highly capacitive loads 6 TO ISEN AND RISET CURRENT SENSE RESISTOR FIGURE 1. SENSE RESISTOR PCB LAYOUT HIP1012A Typical Performance Curves 8.4 8.2 SUPPLY CURRENT(mA) 105 7.8 7.6 7.4 7.2 -40 CURRENT (µA) 8.0 104 103 -30 -20 -10 0 10 20 30 40 50 60 70 80 102 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 2. SUPPLY CURRENT FIGURE 3. RILIM SOURCE CURRENT 10.7 CTIM OC VOLTAGE THRESHOLD (V) -30 -20 -10 0 10 20 30 40 50 60 70 80 CTIM CURRENT SOURCE (µA) 2.04 10.6 2.02 2.00 10.5 1.98 10.4 1.96 10.3 -40 1.94 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 4. CTIM CURRENT SOURCE FIGURE 5. CTIM OC VOLTAGE THRESHOLD 11.00 4.615 2.888 12V UV THRESHOLD (V) 4.610 5V UV 2.886 10.98 4.605 3.3V UV 4.600 2.884 10.96 2.882 10.94 -40 -20 0 20 40 60 80 4.595 -40 -20 0 20 40 60 80 2.880 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 6. 12V UV THRESHOLD FIGURE 7. 5V/3.3V UV THRESHOLD 7 3.3V UV THRESHOLD (V) 5V UV THRESHOLD (V) HIP1012A Typical Performance Curves 17.36 (Continued) 11.935 11.930 3.3V, 5V GATE DRIVE (V) 17.6 17.34 12V GATE DRIVE (V) 12V VG 17.32 17.4 CHARGE PUMP VOLTAGE NO LOAD VOLTAGE (V) 17.2 11.925 11.920 11.915 17.30 3.3V, 5V VG 17.28 17.0 CHARGE PUMP VOLTAGE 100µA LOAD 11.910 11.905 11.900 80 16.8 17.26 -40 -20 0 20 40 60 16.6 -40 -20 TEMPERATURE (°C) 0 20 40 TEMPERATURE (°C) 60 80 FIGURE 8. 12V, 3/5V GATE DRIVE FIGURE 9. PUMP VOLTAGE 54.5 VOLTAGE THRESHOLD (mV) VOLTAGE THRESHOLD (mV) 102.5 54.0 12 OC Vth 102.0 12 OC VTth 53.5 101.5 5 OC Vth 53.0 101.0 5 OC Vth 52.5 -40 -20 0 20 40 60 80 100.5 -40 -20 0 20 40 60 80 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 10. OC VOLTAGE THRESHOLD WITH RLIM = 5kΩ FIGURE 11. OC VOLTAGE THRESHOLD WITH RLIM = 10kΩ 10.2 VDD LOW TO HIGH POWER ON RESET (V) 10.0 9.8 VDD HIGH TO LOW 9.6 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) FIGURE 12. POWER ON RESET VOLTAGE THRESHOLD 8 HIP1012A Exploring and Using the HIP1012EVAL1 Board (Figures 13 and 14) The HIP1012EVAL1 is a flexible platform for a thorough evaluation of the HIP1012A dual power supply controller. This eval board comes in three separate parts allowing the evaluation of two principal configurations. To simulate a passive back plane implementation both the GENERIC and LOAD sections are first connected together and then the GENERIC board is connected onto the BUS board. For an active backplane or for the HIP1012A on an interposer board configuration, the BUS and GENERIC sections are first connected together and then the load board is connected onto the GENERIC board. The HIP1012EVAL1 board has many built in features besides the configuration flexibility described above. The BUS board is designed so that adding suitable connectors and/or power supply capacitive filtering is very easy to do through the numerous through holes for each rail voltage and ground. Passive backplane power sequencing can be simulated by simply shortening the finger lengths for the rail(s) that need to come up after initial ground connection is made. The GENERIC board, is a flexible evaluation platform with many designed in features for user customizing and evaluation. The circuit is shipped default configured in the 3.3V and 5V controller mode by jumpers for easy reconfiguration (see Table 3 for jumper settings). The default configuration is highlighted in Table 3. The default OC levels are 5A on the 3.3V and 1A on the 5V supplies. To operate the HIP1012 GENERIC board in its default configuration (3V and 5V) a dedicated +12V power supply must be provided for the HIP1012 through tie point, W1 on the generic board. To operate the board in the +12V and 5V mode, JP2 and JP3 need to be reconfigured (see Table 3) and a suitable current load needs to be provided. A programmable electronic current load is an excellent evaluation tool for this device. The load board is configured to sink about 3A ±1A at 3.3V. For 12V operation, the load must be modified to sink less than 5A, otherwise, an OC failure upon power will occur. The GENERIC board is provided with a single pair of N-Channel MOSFETs, if currents > 6A are to be evaluated then an additional pair of MOSFETs can be installed in the provided space to reduce distribution losses. Additionally, for even higher current evaluations, space for TO-252AA, DPAK or D2PAK devices has been provided. Tie points on the output side of the GENERIC board are provided for direct access to a high current load. Performance customizing can easily be accomplished by substitution/addition of several SMD components to the existing layout or by utilizing the included bread board area. See Table 5 for the component listing and applicable formulae. The LOAD board, consists of four load switches, output resistive and capacitive loads and output on indicating 1 LED’s. The resistive loads are configured so that either no current, a low or high current load relative to the OC trip point can be invoked for both supplies. An OC event can be emulated by switching both switches of any one output to the on position (see Table 4, OC conditions highlighted). Load connection sequencing can be done by shorting the desired finger lengths. As noted, the GENERIC board is default configured for 3V and 5V operation. For 12V evaluation replace RL3 and RL4 with a suitable load. TABLE 3. JUMPER CONFIGURATION JP # 1 OPEN / SHORT CIRCUIT CONDITION Short to GND PWRON2 shorted to ground. True HOT SWAP mode. PWRON1 only controls reset 2-3 with rising edge. Short to 5V 1-2 Open PWRON2 shorted to 5V. Reset and turn on controlled only by PWRON1. Single input control mode PWRON2 will be internally pulled high to ~2.5V, compatible with logic signal. The HIP1012A can not turn on until PWRON2 is driven low. HIP1012A must be powered from a dedicated +12V power supply. HIP1012A VDD pin connected to same 12V supply as load. See Decoupling Concerns in Critical Items section. C1 in circuit. Charge pump capacitor necessary for 5V and 12V operating mode to develop ~ 11.7V for 12VG voltage. Shorts across charge pump capacitor, C1. Capacitor not needed in 3V and 5V mode. 1 2 2 Open Short 3 Open 3 4 Short Short to GND HIP1012A MODE/PWRON1 shorted to 1-2 ground. True HOT SWAP mode. PWRON2 rising edge only resets HIP1012A. Short to 5V 2-4 Short to VDD 2-3 Open MODE/PWRON1 shorted to 5V. PWRON2 only single mode control. HIP1012A MODE/PWRON1 connected to VDD pin. This along with JP3 installed invokes and configures HIP1012A for 3V and 5V operation. Controlled by PWRON2 HIP1012A MODE/PWRON1 will be internally pulled high to ~2.5V, compatible with logic. Redundant controller mode when each PWRON pin is driven by separate signals. 4 4 4 TABLE 4. LOAD CURRENT SW13 0 0 1 1 SW14 0 1 0 1 3.3V IOUT A 0 2 4 6 SW11 0 0 1 1 SW12 0 1 0 1 5.0V IOUT A 0 0.5 0.74 1.24 9 HIP1012A CEC1 3 /12VIN GND GND 5VIN 1 JP2 CEC2 Q2 R4 20Ω R2 20mΩ C1 0.1µF JP1 1 2 U1 3/12VS 3/12VG HIP1012A JP3 3/12ISEN RILIM GND CPUMP CTIM PGOOD 5VISEN 14 13 12 11 10 9 8 C2 0.047µF 10kΩ R5 C4 GND 0.01µF GND 5VOUT 3 / 12VOUT VDD 0.1µF C5 3 VDD JP4 4 MODE/ PWRON1 5 PWRON2 6 5VG 7 5VS R3 20Ω C3 0.01µF R101 LED1 R1 Q1 100mΩ NOTE: Test point number equals HIP1012A pin number. GENERIC BOARD CEF CEF 1,2,3 R102 LED2 CEF 4,5,6, 7,8,10 CEF 9,11, 12 SW11 R103 LED3 SW12 SW13 RL3 SW14 1.6Ω RL4 INPUT CEF RL1 RL2 10Ω GND BJ3 5VIN BJ4 1 7Ω 3.3/12VIN BJ1 GND BJ2 CEF 1,2,3 0.8Ω CEF 4,5,6 7,8,10 CEF 9,11,12 LOAD BOARD FIGURE 13. BUS BOARD 10 11 HIP1012A FIGURE 14. HIP1012EVAL1 EVAL BOARD HIP1012A TABLE 5. HIP1012EVAL1 BOARD COMPONENT LISTING COMPONENT DESIGNATOR GENERIC BOARD U1 Q1, Q2 QxB and QxC R1 R2 R3, R4 R5 R* C3, C4 C1 C2 HIP1012CB or HIP1012ACB RF1K49156, Si4404DY NOT POPULATED 5V Sense Resistor 3.3V/12V Sense Resistor Loop compensation Resistors Current Limit Set Resistor Isolation resistor (not provided, see Decoupling Concerns in Critical Items section) Gate Timing Capacitors Charge Pump Capacitor Time-out Set Capacitor Intersil Corporation, Dual Power Controller N-Channel MOSFET in 8 SOIC or equivalent replacement Mounting areas for additional 8 SOIC, DPAK or D2PAK packaged COMPONENT NAME COMPONENT DESCRIPTION MOSFETs 100mΩ, 1%, Metal Strip current sensing resistor 20mΩ, 1%, Metal Strip current sensing resistor 20Ω, Resistor in series with gate capacitor. This RC may be necessary to provide current loop stability. Keep resistor < 50Ω. 10kΩ, Current limit = ~10µA x (RILIM/ RSENSE). Add resistor (