HIP2122

100V, 2A Peak, High Frequency Half-Bridge Drivers with Rising Edge Delay Timer HIP2122, HIP2123 The HIP2122 and HIP2123 are 100V, high frequency, half-bridge MOSFET driver ICs. They are based on the popular ISL2100A and ISL2101A half-bridge drivers. Like the ISL2100A, two logic inputs, LI and HI, control both bridge outputs, LO and HO. All logic inputs are VDD tolerant. These drivers have a programmable dead-time to insure break-before-make operation between the high-side and low-side drivers. The dead-time is adjustable up to 220ns. The internal logic does not prevent both outputs from turning on simultaneously if both inputs are high simultaneously for a time greater than the programmed delay. A single PWM logic input controls both bridge outputs (HO, LO). An enable pin (EN), when low, drives both outputs to a low state. All logic inputs are VDD tolerant and the HIP2122 has CMOS inputs with hysteresis for superior operation in noisy environments. The HIP2122 has hysteretic inputs with thresholds that are proportional to VDD. The HIP2123 has 3.3V logic/TTL compatible inputs. Two package options are provided. The 10 lead 4x4 DFN package has standard pinouts. The 9 lead 4x4 DFN package omits pin 2 to comply with 100V conductor spacing per IPC-2221. Features • 9 Ld TDFN “B” Package Compliant with 100V Conductor Spacing Guidelines per IPC-2221 • Break-Before-Make Dead-Time Prevents Shoot-through and is adjustable up to 220ns • Bootstrap Supply Max Voltage to 114VDC • Wide Supply Voltage Range (8V to 14V) • Supply Undervoltage Protection • CMOS Compatible Input Thresholds with Hysteresis (HIP2122) • 1.6Ω/1Ω Typical Output Pull-up/Pull-down Resistance • On-Chip 1Ω Bootstrap Diode Applications • Telecom Half-Bridge DC/DC Converters • UPS and Inverters • Motor Drives • Class-D Amplifiers • Forward Converter with Active Clamp Related Literature • FN7668, HIP2120, HIP2121 “100V, 2A Peak, High Frequency Half-Bridge Drivers with Adjustable Dead Time Control and PWM Input” HALF BRIDGE 100V MAX HIP2122, HIP2123 VDD HI HB HO HS RDT VSS EPAD LO FEEDBACK WITH ISOLATION SECONDARY CIRCUITS DEADTIME (ns) 200 160 140 120 100 80 60 40 PWM CONTROLLER LI 20 8 16 24 32 RDT (kΩ) 40 48 56 64 80 FIGURE 1. TYPICAL APPLICATION FIGURE 2. DEAD-TIME vs TIMING RESISTOR December 23, 2011 FN7670.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. HIP2122, HIP2123 Block Diagram VDD HB HIP2122, HIP2123 HIP2122 HO HIP2122/23 UNDER VOLTAGE LEVEL SHIFT HO HS DELAY RDT OPTIONAL INVERSION FOR FUTURE PART NUMBERS DELAY HIP2122 HIP2122/23 EPAD EPAD IS ELECTRICALLY ISOLATED UNDER VOLTAGE LO LO VSS Pin Configurations HIP2122, HIP2123 (10 LD 4X4 TDFN) TOP VIEW VDD HB HO HS NC 1 2 3 4 5 EPAD 10 LO 9 8 7 6 VSS LI HI RDT HB HO HS 3 4 5 EPAD VDD 1 HIP2122, HIP2123 (9 LD 4X4 TDFN) TOP VIEW 10 LO 9 8 7 6 VSS LI HI RDT 2 FN7670.0 December 23, 2011 HIP2122, HIP2123 Pin Descriptions 9 LD TDFN 10 LD TDFN SYMBOL 1 3 4 5 8 7 9 10 6 1 2 3 4 8 7 9 10 5 6 VDD HB HO HS LI HI VSS LO NC RDT EPAD DESCRIPTION Positive supply voltage for lower gate driver. Decouple this pin with a ceramic capacitor to VSS. High-side bootstrap supply voltage referenced to HS. Connect the positive side of bootstrap capacitor to this pin. Bootstrap diode is on-chip. High-side output. Connect to gate of high-side power MOSFET. High-side source connection. Connect to source of high-side power MOSFET. Connect the negative side of bootstrap capacitor to this pin. Low side driver input. For LI = 1, LO = 1 after programmed delay time; for LI = 0, LO = 0 with minimal delay. High side driver input. For HI = 1, HO = 1 after programmed delay time; for Hi = 0, HO = 0 with minimal delay. Negative supply input, which will generally be ground. Low-side output. Connect to gate of low-side power MOSFET. No Connect. This pin is isolated from all other pins. A resistor connected between this pin and VSS adds additional delay time to the normal rising edge propagation delay. Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins. Ordering Information PART NUMBER (Notes 1, 2, 4) HIP2122FRTAZ HIP2123FRTAZ HIP2122FRTBZ (Note 3) HIP2123FRTBZ (Note 3) NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil PbHfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. “B” package option has alternate pin assignments for compliance with 100V Conductor Spacing Guidelines per IPC-2221. Note that Pin 2 is omitted for additional spacing. 4. For Moisture Sensitivity Level (MSL), please see device information page for HIP2122, HIP2123. For more information on MSL please see tech brief TB363. PART MARKING HIP 2122AZ HIP 2123AZ HIP 2122BZ HIP 2123BZ INPUT CMOS 3.3V/TTL CMOS 3.3V/TTL TEMP. RANGE (°C) - 40 to +125 - 40 to +125 - 40 to +125 - 40 to +125 PACKAGE (Pb-Free) 10 Ld 4x4 TDFN 10 Ld 4x4 TDFN 9 Ld 4x4 TDFN 9 Ld 4x4 TDFN PKG. DWG. # L10.4x4 L10.4x4 L9.4x4 L9.4x4 3 FN7670.0 December 23, 2011 HIP2122, HIP2123 Table of Contents Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Maximum Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ESD Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Selecting the Boot Capacitor Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Transients on HS Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PC Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 EPAD Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 FN7670.0 December 23, 2011 HIP2122, HIP2123 Absolute Maximum Ratings Supply Voltage, VDD, VHB - VHS (Notes 5, 6) . . . . . . . . . . . . . . . -0.3V to 18V LI and HI Input Voltage (Note 6) . . . . . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V Voltage on LO (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V Voltage on HO (Note 6) . . . . . . . . . . . . . . . . . . . . . VHS - 0.3V to VHB + 0.3V Voltage on HS (Continuous) (Note 6) . . . . . . . . . . . . . . . . . . . . . -1V to 110V Voltage on HB (Note 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118V Average Current in VDD to HB Diode . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Thermal Information Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 10 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . . 42 4 9 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . . . 42 4 Max Power Dissipation at +25°C in Free Air 10 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0W 9 Ld TDFN (Notes 7, 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1W Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Maximum Recommended Operating Conditions Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 14V Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V Voltage on HS . . . . . . . . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHS + 8V to VHS + 14V and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD - 1V to VDD + 100V HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .