HIP4020IBZT

DATASHEET HIP4020 FN3976 Rev.5.00 Feb 8, 2019 Half Amp Full Bridge Power Driver for Small 3V, 5V, and 12V DC Motors Features In the Functional Block Diagram of the HIP4020, the four switches and a load are arranged in an H-configuration so that the drive voltage from terminals OUTA and OUTB can be cross-switched to change the direction of current flow in the load. This is commonly known as 4-quadrant load control. As shown Figure 1, switches Q1 and Q4 are conducting or in an ON state when current flows from VDD through Q1 to the load, and then through Q4 to terminal VSSB; where load terminal OUTA is at a positive potential with respect to OUTB. Switches Q1 and Q4 are operated synchronously by the control logic. The control logic switches Q3 and Q2 to an open or OFF state when Q1 and Q4 are switched ON. To reverse the current flow in the load, the switch states are reversed where Q1 and Q4 are OFF while Q2 and Q3 are ON. Consequently, current then flows from VDD through Q3, through the load, and through Q2 to terminal VSSA, and load terminal OUTB is then at a positive potential with respect to OUTA. • Two independent controlled complementary MOS power output half H-drivers (full-bridge) for nominal 3V to 12V power supply operation • Split ±voltage power supply option for output drivers • Load switching capabilities to 0.5A • Single supply range +2.5V to +15V • Low standby current • CMOS/TTL compatible input logic • Over-temperature shutdown protection • Overcurrent limit protection • Overcurrent fault flag output • Direction, braking and PWM control • Pb-free plus anneal (RoHS compliant) Applications Terminals ENA and ENB are ENABLE inputs for the Logic A and B Input Controls. The ILF output is an Overcurrent Limit Fault Flag Output and indicates a fault condition for either Output A or B or both. The VDD and VSS are the Power Supply reference terminals for the A and B Control Logic Inputs and ILF Output. While the VDD positive power supply terminal is internally connected to each bridge driver, the VSSA and VSSB power supply terminals are separate and independent from VSS and may be more negative than the VSS ground reference terminal. The use of level shifters in the gate drive circuitry to the NMOS (low-side) output stages allows controlled level shifting of the output drive relative to ground. • DC motor driver • Relay and solenoid drivers • Stepper motor controller • Air core gauge instrument driver • Speedometer displays • Tachometer displays • Remote power switch • Battery operated switch circuits • Logic and microcontroller operated switch Related Literature For a full list of related documents, visit our website: • HIP4020 device page ENB A1 A2 ENA ILF VSS ISENSE ISENSE Q3 Q1 OUTB OUTA TSENSE Q2 LOAD B2 OVER TEMP. AND CURRENT LIMIT, LEVEL SHIFT, DRIVE CONTROL B1 CONTROL CONTROL LOGIC A LOGIC B VDD Q4 ISENSE ISENSE VSSA VSSB FIGURE 1. BLOCK DIAGRAM FN3976 Rev.5.00 Feb 8, 2019 Page 1 of 10 HIP4020 Ordering Information PART NUMBER (Notes 2, 3) PART MARKING TEMP. RANGE (°C) TAPE AND REEL (UNITS) (Note 1) PACKAGE (RoHS Compliant) PKG. DWG. # HIP4020IBZ HIP4020IBZ -40 to 85 - 20 Ld SOIC M20.3 HIP4020IBZT HIP4020IBZ -40 to 85 1k 20 Ld SOIC M20.3 NOTES: 1. See TB347 for details about reel specifications. 2. Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), see the HIP4020 device page. For more information about MSL, see TB363. Pinout SOIC TOP VIEW NC 1 ILF 2 19 VDD B2 3 18 NC ENB 4 17 OUTB B1 5 16 VSSB VSS 6 15 VSSA 20 NC ENA 7 14 OUTA A1 8 13 NC A2 9 12 VDD NC 10 11 NC Pin Descriptions PIN NUMBER SYMBOL 12, 19 VDD Positive power supply pins; internally common and externally connect to the same positive supply (V+). 15 VSSA Negative power supply pin; negative or ground return for Switch Driver A; externally connect to the supply (V-). 16 VSSB Negative power supply pin; negative or Ground return for Switch Driver B; externally connect to the supply (V-). 6 VSS 8, 5 A1, B1 Input pins used to control the direction of output load current to/from OUTA and OUTB, respectively. When connected, A1 and B1 can be controlled from the same logic signal to change the directional rotation of a motor. 9, 3 A2, B2 Input pins used to force a low state on OUTA and OUTB, respectively. When connected, A2 and B2 can be controlled from the same logic signal to activate dynamic braking of a motor. 7, 4 ENA, ENB 14, 17 OUTA, OUTB 2 ILF FN3976 Rev.5.00 Feb 8, 2019 DESCRIPTION Common ground pin for the Input Logic Control circuits. It can be used as a common ground with VSSA and VSSB. Input pins used to enable Switch Driver A and Switch Driver B, respectively. When low, the respective output is in a high impedance (Z) off-state. Since each switch driver is independently controlled, OUTA and OUTB can be separately PWM controlled as half H-switch drivers. Respectively, Switch Driver A and Switch Driver B output pins. Current limiting fault output flag pin; when in a high logic state, signifies that Switch Driver A or B, or both are in a Current Limiting Fault mode. Page 2 of 10 HIP4020 Absolute Maximum Ratings Thermal Information Supply Voltage; VDD to VSS or VSSA or VSSB . . . . . . . . . . . . .+15V Negative Output Supply Voltage, (VSSA, VSSB) . . . . . . . . . (Note 4) DC Logic Input Voltage (Each Input) . . . (VSS -0.5V) to (VDD +0.5V) DC Logic Input Current (Each Input)  15mA ILF Fault Output Current  15mA Output Load Current, (Self Limiting, see Elec. Spec.)IO(LIMIT) Thermal Resistance (Typical, Note 5) JA (°C/W) Plastic SOIC Package . . . . . . . . . . . . . . . . . . . . . . . 105 Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Operating ConditionsTA = 25°C Typical Operating Supply Voltage Range, VDD . . . . . . . +3 to +12V Low Voltage Logic Retention, Minimum VDD . . . . . . . . . . . . . . . .+2V Idle Supply Current; No Load, VDD = +5V. . . . . . . . . . . . . . . .0.8mA Typical P+N Channel rDS(ON) , VDD = +5V, 0.5A Load . . . . . . . . 2Ω CAUTION: Stresses above those listed in “Absolute Maximum Ratings” can cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 4. VSS is the required common ground reference for the logic input switching. The load currents may be switched positive and negative in reference to the VSS common ground by using a split supply for VDD (positive) to VSSA and VSSB (negative). For an uneven split in the supply voltage, the maximum negative output supply voltage for VSSA and VSSB is limited by the maximum VDD to VSSA or VSSB ratings. Since the VDD pins are internally tied together, the voltage on each VDD pins must be equal and common. 5. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = 25°C, VDD = +5V, VSSA = VSSB = VSS = 0V, unless otherwise specified PARAMETER Input Leakage Current SYMBOL ILEAK TEST CONDITIONS VDD = +15V MIN TYP MAX UNIT - - 25 nA Low Level Input Voltage VIL VSS - 0.8 V High Level Input Voltage VIH 2 - VDD V ILF Output Low, Sink Current IOH VOUT = 0.4V, VDD = +12V 15 - - mA ILF Output High, Source Current IOL VOUT = 11.6V, VDD = +12V - - -15 mA Input Capacitance CIN - 2 - pF P-Channel rDS(ON), Low Supply Voltage rDS(ON) VDD = +3V, ISOURCE = 250mA - 1.6 2.5 Ω N-Channel rDS(ON), Low Supply Voltage rDS(ON) VDD = +3V, ISINK = 250mA - 1 1.5 Ω P-Channel rDS(ON), High Supply Voltage rDS(ON) VDD = +12V, ISOURCE = 400mA - 0.6 1.2 Ω N-Channel rDS(ON), High Supply Voltage rDS(ON) VDD = +12V, ISINK = 400mA - 0.5 1.1 Ω OUTA, OUTB Source Current Limiting IO(LIMIT) VDD = +6V, VSS = 0V, VSSA = VSSB = -6V 480 625 1500 mA OUTA, OUTB Sink Current Limiting -IO(LIMIT) VDD = +6V, VSS = 0V, VSSA = VSSB = -6V 480 800 1500 mA - 0.8 1.5 mA 4.2 4.5 - V - 0.4 0.6 V 2.415 2.6 - V - 0.25 0.375 V Idle Supply Current; No Load IDD OUTA, OUTB Voltage High VOH ISOURCE = 450mA OUTA, OUTB Voltage Low VOL ISINK = 450mA OUTA, OUTB Voltage High VOH VDD = +3V, ISOURCE = 250mA OUTA, OUTB Voltage Low VOL VDD = +3V, ISINK = 250mA OUTA, OUTB Source Current Limiting IO(LIMIT) VDD = +12V 480 625 1500 mA OUTA, OUTB Sink Current Limiting -IO(LIMIT) VDD = +12V 480 800 1500 mA OUTA, OUTB Source Current Limiting IO(LIMIT) VDD = +3V 480 625 1500 mA OUTA, OUTB Sink Current Limiting -IO(LIMIT) VDD = +3V 480 800 1500 mA - 145 - °C Thermal Shutdown FN3976 Rev.5.00 Feb 8, 2019 TSD Page 3 of 10 HIP4020 Electrical Specifications TA = 25°C, VDD = +5V, VSSA = VSSB = VSS = 0V, unless otherwise specified (Continued) PARAMETER SYMBOL Response Time: VEN to VOUT Turn-On: Prop Delay TEST CONDITIONS MIN TYP MAX UNIT - 2.5 - µs tr - 4 - µs tPHL - 0.1 - µs tf - 0.1 - µs IO = 0.5A (Note 6) tPLH Rise Time Turn-Off: Prop Delay Fall Time NOTE: 6. See the Truth Table and the VEN to VOUT Switching Waveforms. Current IO refers to IOUTA or IOUTB as the output load current. Note that ENA controls OUTA and ENB controls OUTB. Each Half H-switch has independent control from the respective A1, A2, ENA or B1, B2, ENB inputs. See the terminal Information table for external pin connections to establish mode control switching. Figure 2 on page 4 shows a typical application circuit used to control a DC Motor. V+ VDD B2 ENB OFF A1 DIRECTION CONTROL LOGIC A A2 Q1 Q2 OVER-TEMP LIMIT ON LEVEL SHIFTER AND OC/OT LIMITER CONTROL LOGIC B BRAKE D1 D2 LEVEL SHIFTER AND OC/OT LIMITER B1 Q3 D3 D4 Q4 ENA ENABLE VSS VSSA OUTA OUTB (LOGIC GROUND) ILF VSSB LOAD V- FIGURE 2. TYPICAL MOTOR CONTROL APPLICATION CIRCUIT SHOWING DIRECTIONAL AND BRAKING CONTROL TRUTH TABLE SWITCH DRIVER A SWITCH DRIVER B INPUTS OUTPUT INPUTS OUTPUT A1 A2 ENA OUTA B1 B2 ENB OUTB H L H OH L L H OH L L H OL H L H OL H H H OL L H H OL L H H OL H H H OL X X L Z X X L Z L = Low logic level; H = High logic level Z = High Impedance (off state) OH = Output High (sourcing current to the output terminal) OL = Output Low (sinking current from the output terminal) X = Do not Care VEN VOUT 50% tPLH 90% 10% 50% tr 50% VEN tPHL VOUT 10% 90% 50% tf FIGURE 3. SWITCHING WAVEFORMS FN3976 Rev.5.00 Feb 8, 2019 Page 4 of 10 HIP4020 Application The HIP4020 is designed to detect load current feedback from sampling resistors of low value in the source connections of the output drivers to VDD, VSSA and VSSB (see Figure 2). When the sink or source current at OUTA or OUTB exceeds the preset OC (Overcurrent) limiting value of 550mA typical, the current is held at the limiting value. If the Over-Temperature (OT) Shutdown Protection limit is exceeded, temperature sensing BiMOS circuits limit the junction temperature to 150°C typical. Figure 2 shows the Full H-switch in a small motor-drive application. The left (A) and right (B) H-switch’s are controlled from the A and B inputs using the A and B control logic to the MOS output transistors Q1, Q2, Q3, and Q4. The circuit is intended to safely start, stop, and control rotational direction for a motor requiring no more than 0.5A of supply current. The stop function includes a dynamic braking feature. With the enable inputs low, the MOS transistors Q1 and Q3 are OFF; which cuts-off supply current to OUTA and OUTB. With the brake terminal low and enable inputs high, either Q1 and Q4 or Q3 and Q2 are driven into conduction by the direction input control terminal. The MOS output transistor pair chosen for conduction is determined by the logic level applied to the direction control; resulting in either Clockwise (CW) or Counter-Clockwise (CCW) shaft rotation. When the brake terminal is switched high (while holding the enable input high), the gates of both Q2 and Q4 are driven high. Current flowing through Q2 (from the motor terminal OUTA) at the moment of dynamic braking continues to flow through Q2 to the VSSA and VSSB external connection, and then continues through diode D4 to the motor terminal OUTB. As such, the resistance of the motor winding (and the A1 (DIR) A2 (BRAKE) ENA (ENABLE) series-connected path) dissipates the kinetic energy stored in the system. Reversing rotation, current flowing through Q4 (from the motor terminal OUTB), at the moment of dynamic braking, would continue to flow through Q4 to the VSSB and VSSA tie, and then continue through diode D2 to the motor terminal OUTA, to dissipate the stored kinetic energy as previously described. Where VDD to VSS are the power supply reference terminals for the control logic, the lowest practical supply voltage for proper logic control should be no less than 2.0V. The VSSA and VSSB terminals are separate and independent from VSS and may be more negative than the VSS ground reference terminal. However, the maximum supply level from VDD to VSSA or VSSB must not be greater than the absolute maximum supply voltage rating. Terminals A1, B1, A2, B2, ENA, and ENB are internally connected to protection circuits intended to guard the CMOS gate-oxides against damage due to electrostatic discharge. (See Figure 4) Inputs ENA, ENB, A1, B1, A2, and B2 have protection and level converters for TTL or CMOS Input Logic. These inputs are designed to typically provide ESD protection up to 2kV. However, these devices are sensitive to electrostatic discharge. Proper IC handling procedures should be followed. VDD INPUT LEVEL CONV. FIGURE 4. LOGIC INPUT ESD INTERFACE PROTECTION VDD P-DR LIMIT OT AND OC PROTECT Q1 Q2 D1 OUTA D2 N-DR LIMIT VSSA VDD B1 (DIR) B2 (BRAKE) ENB (ENABLE) P-DR LIMIT OT AND OC PROTECT Q3 Q4 D3 OUTB D4 N-DR LIMIT VSSB FIGURE 5. EQUIVALENT CONTROL LOGIC A AND B SHOWN DRIVING THE OUTA AND OUTB OUTPUT DRIVERS FN3976 Rev.5.00 Feb 8, 2019 Page 5 of 10 HIP4020 P-CHANNEL DRAIN CURRENT (mA) Typical Performance Curves 800 750 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 0.5Ω 1Ω 2Ω VDD = 12V VDD = 5V 0.0 0.1 0.2 0.3 0.4 0.5 0.6 VDD = 3V 0.7 0.8 0.9 1.0 1.1 1.2 1.3 DRAIN-TO-SOURCE VOLTAGE (V) 1.4 TYPICAL CURRENT LIMITING 1.5 1.6 1.7 1.8 1.9 2.0 N-CHANNEL DRAIN CURRENT (mA) FIGURE 6. TYPICAL CHARACTERISTIC OF THE P-MOSFET OUTPUT DRIVER DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE, TAMBIENT = 25°C 800 750 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 0.5Ω 1Ω VDD = 5V 2Ω VDD = 3V TYPICAL CURRENT LIMITING VDD = 12V 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 DRAIN-TO-SOURCE VOLTAGE (V) SHORT CIRCUIT CURRENT (mA) FIGURE 7. TYPICAL CHARACTERISTIC OF THE N-MOSFET OUTPUT DRIVER DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE, TAMBIENT = 25°C 800 750 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 N-CHANNEL P-CHANNEL 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 VDD SUPPLY VOLTAGE (V) FIGURE 8. TYPICAL CHARACTERISTIC OF THE P AND N OUTPUT DRIVER SHORT CIRCUIT CURRENT vs SUPPLY VOLTAGE, TAMBIENT = 25°C FN3976 Rev.5.00 Feb 8, 2019 Page 6 of 10 HIP4020 Typical Performance Curves (Continued) SATURATION VOLTAGE, VDD - VOUT (V) 0.65 HIP4020 SPLIT 5V COMMON GROUND VSAT vs LOAD CURRENT VDD = +5V VSS = VSSA = VSSB = GND 0.60 0.55 0.50 HIGH 0.45 LOW 0.40 0.35 0.30 0.25 VSAT(P) VSAT(N) 0.20 0.15 0.10 0.05 0.00 0 100 200 300 OUTPUT CURRENT, IO (A) 400 500 FIGURE 9. TYPICAL CHARACTERISTIC OF SATURATION VOLTAGE vs OUTPUT CURRENT USING A +5V SUPPLY, TAMBIENT = 25°C SATURATION VOLTAGE, VDD - VOUT (V) 0.70 HIP4020 SPLIT 3V VSAT vs LOAD CURRENT VDD = +3V VSS = GND VSSA = VSSB = -3V 0.65 0.60 0.55 0.50 HIGH 0.45 0.40 LOW 0.35 VSAT(P) 0.30 VSAT(N) 0.25 0.20 0.15 0.10 0.05 0.00 0 100 200 300 400 OUTPUT CURRENT, IO (A) 500 600 700 FIGURE 10. TYPICAL CHARACTERISTIC OF SATURATION VOLTAGE vs OUTPUT CURRENT USING A ±3V SPLIT SUPPLY, OUTPUT REFERENCE EQUAL LOGIC GROUND, TAMBIENT = 25°C SATURATION VOLTAGE, VDD - VOUT (V) 0.70 0.65 HIP4020 SPLIT ±6V VSAT vs LOAD CURRENT VDD = +6V VSS = GND VSSA = VSSB = -6V 0.60 0.55 0.50 0.45 0.40 HIGH 0.35 LOW 0.30 0.25 0.20 VSAT(P) 0.15 VSAT(N) 0.10 0.05 0.00 0 100 200 300 400 OUTPUT CURRENT, IO (A) 500 600 FIGURE 11. TYPICAL CHARACTERISTIC OF SATURATION VOLTAGE vs OUTPUT CURRENT USING A ±6V SPLIT SUPPLY, OUTPUT REFERENCE EQUAL LOGIC GROUND, TAMBIENT = 25°C FN3976 Rev.5.00 Feb 8, 2019 Page 7 of 10 HIP4020 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION Feb 8, 2019 FN3976.5 Added Related Literature section. Updated Ordering information table by removing retired part, added new notes, and moved to page 2. Moved Pin Descriptions below Pinout section. Added TB493 reference under Thermal Information section. Moved Note 6 to end of EC table. Updated P-Channel rDS(ON), Low Supply Voltage maximum specification from 2.1 to 2.5. Removed About Intersil section. Updated disclaimer. Sep17, 2015 FN3976.4 - Updated Ordering Information Table on page 2. - Added Revision History. - Added About Intersil Verbiage. - Updated POD M20.3 to latest revision changes are as follow: Top View: Corrected "7.50 BSC" to "7.60/7.40" (no change from rev 2; error was introduced in conversion) Changed "10.30 BSC" to "10.65/10.00" (no change from rev 2; error was introduced in conversion) Side View: Changed "12.80 BSC" to "13.00/12.60" (no change from rev 2; error was introduced in conversion) Changed "2.65 max" to "2.65/2.35" (no change from rev 2; error was introduced in conversion) Changed Note 1 from "ANSI Y14.5M-1982." to "ASME Y14.5M-1994" FN3976 Rev.5.00 Feb 8, 2019 CHANGE Page 8 of 10 HIP4020 Package Outline Drawing For the most recent package outline drawing, see M20.3. M20.3 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC) Rev 3, 2/11 20 INDEX AREA 7.60 7.40 1 2 10.65 10.00 0.25 (0.10) M B M 3 3 TOP VIEW 13.00 12.60 SEATING PLANE 2 2.65 2.35 5 0.75 1.27 BSC 0.49 0.35 7 0.25 (0.10) M 0.25 0.30 MAX C A M B S 1.27 0.40 x 45° 8° MAX 0.10 (0.004) SIDE VIEW 0.32 0.23 DETAIL "X" NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. (0.60) 1.27 BSC 2. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 20 (2.00) 3. Dimension does not include interlead lash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. (9.40mm) 5. Dimension is the length of terminal for soldering to a substrate. 6. Terminal numbers are shown for reference only. 7. The lead width as measured 0.36mm (0.14 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 8. Controlling dimension: MILLIMETER. 1 2 3 TYPICAL RECOMMENDED LAND PATTERN FN3976 Rev.5.00 Feb 8, 2019 9. Dimensions in ( ) for reference only. 10. JEDEC reference drawing number: MS-013-AC. Page 9 of 10 1RWLFH  'HVFULSWLRQVRIFLUFXLWVVRIWZDUHDQGRWKHUUHODWHGLQIRUPDWLRQLQWKLVGRFXPHQWDUHSURYLGHGRQO\WRLOOXVWUDWHWKHRSHUDWLRQRIVHPLFRQGXFWRUSURGXFWV DQGDSSOLFDWLRQH[DPSOHV