HIP6601CB

HIP6601, HIP6603 Data Sheet January 2000 File Number 4819 Synchronous-Rectified Buck MOSFET Drivers The HIP6601 and HIP6603 are high frequency, dual MOSFET drivers specifically designed to drive two power N-Channel MOSFETs in a synchronous-rectified buck converter topology. These drivers combined with a HIP630x Multi-Phase Buck PWM controller and Intersil UltraFETs™ form a complete core-voltage regulator solution for advanced microprocessors. The HIP6601 drives the lower gate in a synchronous-rectifier bridge to 12V, while the upper gate can be independently driven over a range from 5V to 12V. The HIP6603 drives both upper and lower gates over a range of 5V to 12V. This drive-voltage flexibility provides the advantage of optimizing applications involving trade-offs between switching losses and conduction losses. The output drivers in the HIP6601 and HIP6603 have the capacity to efficiently switch power MOSFETs at frequencies up to 2MHz. Each driver is capable of driving a 3000pF load with a 30ns propagation delay and 50ns transition time. Both products implement bootstrapping on the upper gate with only an external capacitor required. This reduces implementation complexity and allows the use of higher performance, cost effective, N-Channel MOSFETs. Adaptive shoot-through protection is integrated to prevent both MOSFETs from conducting simultaneously. Features • Drives Two N-Channel MOSFETs • Adaptive Shoot-Through Protection • Internal Bootstrap Device • Supports High Switching Frequency - Fast Output Rise Time - Propagation Delay 30ns • Small 8 Lead SOIC Package • Dual Gate-Drive Voltages for Optimal Efficiency • Three-State Input for Bridge Shutdown • Supply Under Voltage Protection Applications • Core Voltage Supplies for Intel Pentium® III, AMD® Athlon™ Microprocessors • High Frequency Low Profile DC-DC Converters • High Current Low Voltage DC-DC Converters Pinout HIP6601CB/HIP6603CB (SOIC) TOP VIEW Ordering Information PART NUMBER HIP6601CB HIP6603CB TEMP. RANGE (oC) 0 to 85 0 to 85 PACKAGE 8 Ld SOIC 8 Ld SOIC PKG. NO. M8.15 M8.15 UGATE BOOT PWM GND 1 2 3 4 8 7 6 5 PHASE PVCC VCC LGATE Block Diagram PVCC BOOT UGATE VCC PHASE +5V 10K PWM CONTROL LOGIC 10K SHOOTTHROUGH PROTECTION † VCC FOR HIP6601 PVCC FOR HIP6603 † LGATE GND 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. UltraFET™ is a trademark of Intersil Corporation. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 2000 Pentium® is a registered trademark of Intel Corporation. AMD® is a registered trademark of Advanced Micro Devices, Inc. HIP6601, HIP6603 Typical Application +12V +5V BOOT VCC PWM PVCC UGATE DRIVE PHASE HIP6601 LGATE +12V +5V +5V BOOT +VCORE VFB VCC VSEN PGOOD COMP VCC PWM1 PWM2 PWM3 PWM PVCC UGATE DRIVE PHASE HIP6601 LGATE VID MAIN CONTROL HIP6301 ISEN1 ISEN2 FS GND ISEN3 +5V BOOT PVCC VCC PWM DRIVE PHASE HIP6601 LGATE UGATE +12V 2 HIP6601, HIP6603 Absolute Maximum Ratings Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V BOOT Voltage (VBOOT - VPHASE). . . . . . . . . . . . . . . . . . . . . . . .15V Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V UGATE . . . . . . . . . . . . . . . . . . . . . . VPHASE - 0.3V to VBOOT + 0.3V LGATE . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to VPVCC + 0.3V ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . .3kV Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . .200V Thermal Information Thermal Resistance θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Operating Conditions Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0oC to 85oC Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125oC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V ±10% Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . . . . . . 5V to 12V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications PARAMETER VCC SUPPLY CURRENT Bias Supply Current Recommended Operating Conditions, Unless Otherwise Noted SYMBOL TEST CONDITIONS MIN TYP MAX UNITS IVCC IPVCC HIP6601, fPWM = 1MHz, VPVCC = 12V HIP6603, fPWM = 1MHz, VPVCC = 12V HIP6601, fPWM = 1MHz, VPVCC = 12V HIP6603, fPWM = 1MHz, VPVCC = 12V - 4.4 2.5 200 1.8 6.2 3.6 430 3.3 mA mA µA mA Power Supply Current POWER-ON RESET VCC Rising Threshold VCC Falling Threshold PWM INPUT Input Current PWM Rising Threshold PWM Falling Threshold UGATE Rise Time LGATE Rise Time UGATE Fall Time LGATE Fall Time UGATE Turn-Off Propagation Delay LGATE Turn-Off Propagation Delay Shutdown Window Shutdown Holdoff Time OUTPUT Upper Drive Source Impedance RUGATE RUGATE RLGATE RLGATE VVCC = 12V, VPVCC = 5V VVCC = VPVCC = 12V Upper Drive Sink Impedance VVCC = 12V, VPVCC = 5V VVCC = 12V, VPVCC = 12V Lower Drive Source Impedance VVCC = 12V, VPVCC = 5V VVCC = 12V, VPVCC = 12V Lower Drive Sink Impedance VVCC = VPVCC = 12V 2.5 7.0 2.3 1.0 4.5 9.0 1.5 3.0 7.5 2.8 1.3 5.0 9.5 2.9 Ω Ω Ω Ω Ω Ω Ω TRUGATE TRLGATE TFUGATE TFLGATE VPVCC = VVCC = 12V, 3nF load VPVCC = VVCC = 12V, 3nF load VPVCC = VVCC = 12V, 3nF load VPVCC = VVCC = 12V, 3nF load IPWM VPWM = 0 or 5V (See Block Diagram) 3.6 1.5 500 3.7 1.3 20 50 20 20 30 20 230 1.4 3.6 µA V V ns ns ns ns ns ns V ns 9.7 9.0 9.9 9.1 10.0 9.2 V V TPDLUGATE VVCC = VPVCC = 12V, 3nF load TPDLLGATE VVCC = VPVCC = 12V, 3nF load 3 HIP6601, HIP6603 Functional Pin Description UGATE (Pin 1) Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET. PVCC (Pin 7) For the HIP6601, this pin supplies the upper gate drive bias. Connect this pin from +12V down to +5V. For the HIP6603, this pin supplies both the upper and lower gate drive bias. Connect this pin to either +12V or +5V. BOOT (Pin 2) Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the appropriate capacitor value. PHASE (Pin 8) Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. The PHASE voltage is monitored for adaptive shoot-through protection. This pin also provides a return path for the upper gate drive. Description Operation Designed for versatility and speed, the HIP6601 and HIP6603 dual MOSFET drivers control both high-side and low-side NChannel FETs from one externally provided PWM signal. The upper and lower gates are held low until the driver is initialized. Once the VCC voltage surpasses the VCC Rising Threshold (See Electrical Specifications), the PWM signal takes control of gate transitions. A rising edge on PWM initiates the turn-off of the lower MOSFET (see Timing Diagram). After a short propagation delay [TPDLLGATE], the lower gate begins to fall. Typical fall times [TFLGATE] are provided in the Electrical Specifications section. Adaptive shoot-through circuitry monitors the LGATE voltage and determines the upper gate delay time [TPDHUGATE] based on how quickly the LGATE voltage drops below 1.0V. This prevents both the lower and upper MOSFETs from conducting simultaneously or shoot-through. Once this delay period is complete the upper gate drive begins to rise [TRUGATE] and the upper MOSFET turns on. PWM (Pin 3) The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the controller. GND (Pin 4) Bias and reference ground. All signals are referenced to this node. LGATE (Pin 5) Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET. VCC (Pin 6) Connect this pin to a +12V bias supply. Place a high quality bypass capacitor from this pin to GND. Timing Diagram PWM TPDHUGATE TPDLUGATE TRUGATE TFUGATE UGATE LGATE TFLGATE TPDLLGATE TPDHLGATE TRLGATE 4 HIP6601, HIP6603 A falling transition on PWM indicates the turn-off of the upper MOSFET and the turn-on of the lower MOSFET. A short propagation delay [TPDLUGATE] is encountered before the upper gate begins to fall [TFUGATE]. Again, the adaptive shoot-through circuitry determines the lower gate delay time, TPDHLGATE. The PHASE voltage is monitored and the lower gate is allowed to rise after PHASE drops below 0.5V. The lower gate then rises [TRLGATE], turning on the lower MOSFET. The bootstrap capacitor must have a maximum voltage rating above VCC + 5V. The bootstrap capacitor can be chosen from the following equation: Q GATE C BOOT ≥ ----------------------∆ V BOOT Where QGATE is the amount of gate charge required to fully charge the gate of the upper MOSFET. The ∆VBOOT term is defined as the allowable droop in the rail of the upper drive. As an example, suppose a HUF76139 is chosen as the upper MOSFET. The gate charge, QGATE , from the data sheet is 65nC for a 10V upper gate drive. We will assume a 200mV droop in drive voltage over the PWM cycle. We find that a bootstrap capacitance of at least 0.325µF is required. The next larger standard value capacitance is 0.33µF. Three-State PWM Input A unique feature of the HIP660X drivers is the addition of a shutdown window to the PWM input. If the PWM signal enters and remains within the shutdown window for a set holdoff time, the output drivers are disabled and both MOSFET gates are pulled and held low. The shutdown state is removed when the PWM signal moves outside the shutdown window. Otherwise, the PWM rising and falling thresholds outlined in the ELECTRICAL SPECIFICATIONS determine when the lower and upper gates are enabled. Gate Drive Voltage Versatility The HIP6601 and HIP6603 provide the user total flexibility in choosing the gate drive voltage. The HIP6601 lower gate drive is fixed to VCC [+12V], but the upper drive rail can range from 12V down to 5V depending on what voltage is applied to PVCC. The HIP6603 ties the upper and lower drive rails together. Simply applying a voltage from 5V up to 12V on PVCC will set both driver rail voltages. Adaptive Shoot-Through Protection Both drivers incorporate adaptive shoot-through protection to prevent upper and lower MOSFETs from conducting simultaneously and shorting the input supply. This is accomplished by ensuring the falling gate has turned off one MOSFET before the other is allowed to rise. During turn-off of the lower MOSFET, the LGATE voltage is monitored until it reaches a 1.0V threshold, at which time the UGATE is released to rise. Adaptive shoot-through circuitry monitors the PHASE voltage during UGATE turn-off. Once PHASE has dropped below a threshold of 0.5V, the LGATE is allowed to rise. PHASE continues to be monitored during the lower gate rise time. If the PHASE voltage exceeds the 0.5V threshold during this period and remains high for longer than 2µs, the LGATE transitions low. Both upper and lower gates are then held low until the next rising edge of the PWM signal. Power Dissipation Package power dissipation is mainly a function of the switching frequency and total gate charge of the selected MOSFETs. Calculating the power dissipation in the driver for a desired application is critical to ensuring safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of 125oC. The maximum allowable IC power dissipation for the SO8 package is approximately 800mW. When designing the driver into an application, it is recommended that the following calculation be performed to ensure safe operation at the desired frequency for the selected MOSFETs. The power dissipated by the driver is approximated as: 3 P = 1.05f sw  -- V U Q + V L Q  + I DDQ V 2 L CC U Power-On Reset (POR) Function During initial startup, the VCC voltage rise is monitored and gate drives are held low until a typical VCC rising threshold of 9.9V is reached. Once the rising VCC threshold is exceeded, the PWM input signal takes control of the gate drives. If VCC drops below a typical VCC falling threshold of 9.1V during operation, then both gate drives are again held low. This condition persists until the VCC voltage exceeds the VCC rising threshold. Internal Bootstrap Device Both drivers feature an internal bootstrap device. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. where fsw is the switching frequency of the PWM signal. VU and VL represent the upper and lower gate rail voltage. QU and QL is the upper and lower gate charge determined by MOSFET selection and any external capacitance added to the gate pins. The IDDQ VCC product is the quiescent power of the driver and is typically 30mW. The power dissipation approximation is a result of power transferred to and from the upper and lower gates. But, the internal bootstrap device also dissipates power on-chip during the refresh cycle. Expressing this power in terms of the upper MOSFET total gate charge is explained below. 5 HIP6601, HIP6603 The bootstrap device conducts when the lower MOSFET or it’s body diode conducts and pulls the PHASE node toward GND. While the bootstrap device conducts, a current path is formed that refreshes the bootstrap capacitor. Since the upper gate is driving a MOSFET, the charge removed from the bootstrap capacitor is equivalent to the total gate charge of the MOSFET. Therefore, the refresh power required by the bootstrap capacitor is equivalent to the power used to charge the gate capacitance of the MOSFET. 1 1 P REFRESH = -- f SW Q V = -- f SW Q V LOSS PVCC UU 2 2 200 1000 PVCC = VCC = 12V 800 POWER (mW) CU = CL = 3nF 600 400 CU = CL = 1nF CU = CL = 2nF CU = CL = 4nF CU = CL = 5nF 0 500 1000 FREQUENCY (kHz) 1500 2000 where QLOSS is the total charge removed from the bootstrap capacitor and provided to the upper gate load. The 1.05 factor is a correction factor derived from the following characterization. The base circuit for characterizing the drivers for different loading profiles and frequencies is provided. CU and CL are the upper and lower gate load capacitors. Decoupling capacitors [0.15µF] are added to the PVCC and VCC pins. The bootstrap capacitor value is 0.01µF. In Figure 1, CU and CL values are the same and frequency is varied from 50kHz to 2MHz. PVCC and VCC are tied together to a +12V supply. Curves do exceed the 800mW cutoff, but continuous operation above this point is not recommended. Figure 2 shows the dissipation in the driver with 3nF loading on both gates and each individually. Note the higher upper gate power dissipation which is due to the bootstrap device refresh cycle. Again PVCC and VCC are tied together and to a +12V supply. FIGURE 1. POWER DISSIPATION vs FREQUENCY 1000 PVCC = VCC = 12V 800 CU = CL = 3nF POWER (mW) 600 CU = 3nF 400 CL = 3nF 200 0 500 1000 FREQUENCY (kHz) 1500 2000 Test Circuit +5V OR +12V FIGURE 2. 3nF LOADING PROFILE +12V 0.01µF PVCC BOOT 2N7002 UGATE HIP660X VCC 0.15µF PWM PHASE LGATE 2N7002 CL 100kΩ CU 0.15µF The impact of loading on power dissipation is shown in Figure 3. Frequency is held constant while the gate capacitors are varied from 1nF to 5nF. VCC and PVCC are tied together and to a +12V supply. Figures 4 through 6 show the same characterization for the HIP6603 with a +5V supply on PVCC and VCC tied to a +12V supply. Since both upper and lower gate capacitance can vary, Figure 7 shows dissipation curves versus lower gate capacitance with upper gate capacitance held constant at three different values. These curves apply only to the HIP6601 due to power supply configuration. GND 6 HIP6601, HIP6603 600 400 PVCC = 5V VCC = 12V 320 POWER (mW) FREQUENCY = 800kHz PVCC = VCC = 12V 500 POWER (mW) CU = CL = 5nF CU = CL = 4nF CU = CL = 3nF 400 FREQUENCY = 500kHz 300 240 160 CU = CL = 2nF CU = CL = 1nF 200 FREQUENCY = 200kHz 100 1.0 2.0 3.0 4.0 5.0 80 0 500 1000 FREQUENCY (kHz) 1500 2000 GATE CAPACITANCE (CU = CL), (nF) FIGURE 3. POWER DISSIPATION vs LOADING 300 PVCC = 5V VCC = 12V 240 POWER (mW) FIGURE 4. POWER DISSIPATION vs FREQUENCY (HIP6603) 250 PVCC = 5V VCC = 12V CU = CL = 3nF POWER (mW) 200 FREQUENCY = 800kHz 150 180 CU = 3nF 120 100 FREQUENCY = 500kHz 60 CL = 1nF 50 FREQUENCY = 200kHz 0 1.0 0 500 1000 FREQUENCY (kHz) 1500 2000 2.0 3.0 4.0 5.0 GATE CAPACITANCE (CU = CL), (nF) FIGURE 5. 3nF LOADING PROFILE (HIP6603) 400 FIGURE 6. VARIABLE LOADING PROFILE (HIP6603) CU = 5nF PVCC = 5V VCC = 12V 350 POWER (mW) CU = 3nF 300 200 CU = 1nF 150 100 1.0 2.0 3.0 FREQUENCY (kHz) 4.0 5.0 FIGURE 7. POWER DISSIPATION vs LOADING (HIP6601) 7 HIP6601, HIP6603 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 L A1 B C D E α A1 0.10(0.004) C e H h L N 0.050 BSC 0.2284 0.0099 0.016 8 0o 8o 0.2440 0.0196 0.050 1.27 BSC 5.80 0.25 0.40 8 0o 6.20 0.50 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 8