HIP7030A2M

HIP7030A2 ADVANCE INFORMATION August 1996 J1850 8-Bit 68HC05 Microcontroller Description The HIP7030A2 HCMOS Microcomputer is a member of the CDP68HC05 family of low-cost single-chip microcomputers. The integrated hardware functions provide the system designer with a complete set of building blocks for implementing a “Class B” multiplexed communications network interface, which fully conforms to the VPW Multiplexed Wiring protocol specified in SAE Recommended Practice J1850. This 8-bit microcomputer unit (MCU) contains an onchip oscillator, CPU, 176 bytes of RAM, 2110 bytes of user ROM, 13 I/O lines, a J1850 Variable Pulse Width Symbol Encoder/Decoder (VPW SENDEC) system, a Serial Peripheral Interface (SPI) system, a two channel analog Comparator, a Watchdog Timer, a Slow Clock Detect, and a 16-bit Timer. The static HCMOS design allows operation at input frequencies up to 10MHz (5MHz internal clock). Features • Fully Supports VPW Specifications of SAE J1850 Standard for Class B Data Communications Network Interface • On-Chip Memory • 176 Bytes of RAM • 2110 Bytes of User ROM • 13 Bidirectional I/O Lines • 16-Bit Timer with Capture and Compare Registers • Serial Peripheral Interface (SPI) System • Watchdog Timer and Slow Clock Detect • 10MHz Operating Frequency (5.0MHz Internal Bus Frequency) at 5V • Built-In-Test Bootstrap Mode with 242 Bytes of ROM • Two Channel Analog Comparator • On-Chip Oscillator Amplifier • 8-Bit CPU Architecture • Power-Saving STOP, WAIT and Data Retention Modes • Full -40oC to 125oC Operating Range • Single 3.0V to 6.0V Supply • 28 Lead Dual-In-Line and Small Outline Plastic Packages Table of Contents Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Electrical & Timing Specifications . . . . . . . . . . . . . . . . . . . . . 3 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Integrated Hardware I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Built-In Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Programmable Timer Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . 27 J1850 VPW Messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Symbol Encoder Decoder Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 COP System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Effects of STOP and WAIT Modes . . . . . . . . . . . . . . . . . . . . 41 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Package Outline Dimensions . . . . . . . . . . . . . . . . . . . . 55 - 56 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 I/O, Control, Status and Data Register Definitions . . . . . . . 52 Ordering Information Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Ordering Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Software Features • Standard 68HC05 Instruction Set • True Bit Manipulation • Addressing Modes Include Indexed Addressing - Memory Mapped I/O Ordering Information PART NUMBER HIP7030A2P HIP7030A2M TEMP. RANGE (oC) -40 to 125 -40 to 125 PACKAGE 28 Lead Plastic DIP 28 Lead Plastic SOIC (W) PKG. NO. M28.3 E28.6 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 File Number 3646.2 1 HIP7030A2 Block Diagram OSCIN TCMP 2 TCAP PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 1 15 14 13 12 11 10 9 8 TIMER SYSTEM INTERNAL PROCESSOR CLOCK 24 OSCILLATOR AND ÷ 2 OSCOUT 23 16 OSCB 5 6 RESET IRQ PORT A I/O LINES SYMBOL INT ACCUMULATOR PORT A REG DATA DIR REG 8 8 5 PORT D REG + 6 PORT D SFR REG PORT D DIR REG 5 8 INDEX REGISTER CONDITION CODE REGISTER STACK POINTER A X CC S ALU CPU CONTROL 4 VPW SYMBOL ENCODER / DECODER AND ARBITRATION 3 VPW OUT VPW IN CPU SPI SYSTEM 25 26 27 28 SCK MOSI MISO SS PORT D I/O LINES 21 PD0 PD1 PD2, V2 PD3, V3 PD4, VR TCAP 20 19 18 17 - PROGRAM COUNTER HIGH PCH PROGRAM COUNTER LOW PCL + INTERNAL PROCESSOR CLOCK WATCHDOG AND SLOW CLOCK DETECT 2110 x 8 ROM VSS 22 VDD 7 242 x 8 BUILT-IN-TEST ROM 176 x 8 STATIC RAM Pinout HIP7030A2 (PDIP, SOIC) TOP VIEW TCAP 1 TCMP 2 VPW IN 3 VPW OUT 4 RESET 5 IRQ 6 VDD 7 PA7 8 PA6 9 PA5 10 PA4 11 PA3 12 PA2 13 PA1 14 28 SS 27 MISO 26 MOSI 25 SCK 24 OSCIN 23 OSCOUT 22 VSS 21 PD0 20 PD1 19 PD2, V2 18 PD3, V3 17 PD4, VREF 16 OSCB 15 PA0 2 HIP7030A2 Absolute Maximum Ratings Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V Input or Output Voltage Pins with VDD Diode . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Pins without VDD Diode . . . . . . . . . . . . . . . . . . . . . -0.3V to +10V Current Drain Per Pin, I (Excluding VDD and VSS) . . . . . . . . 25mA Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . +265oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2 Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9000 Gates Thermal Information Thermal Resistance (Typical) θJA Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60oC/W Plastic SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 75oC/W Maximum Package Power Dissipation at +125oC DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415mW SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325mW Operating Temperature Range (TA) . . . . . . . . . . . .-40oC to +125oC Storage Temperature Range (TSTG). . . . . . . . . . . .-65oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +3.0V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . . -40oC to 125oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .(0.8•VDD) to VDD Input Rise and Fall Time CMOS Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ns Max. CMOS Schmitt Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . .Unlimited DC Electrical Specifications PARAMETER No Load Output Voltage VDD = 5VDC ±10%, VSS = 0VDC, TA = -40oC to +125oC Unless Otherwise Specified SYMBOL VOL VOH CONDITIONS ILOAD < ±10µA MIN VDD -0.1 ILOAD = -0.8mA ILOAD = -0.08mA ILOAD = -1.6mA ILOAD = 0.17mA ILOAD = 1.6mA VDD -0.8 VDD -0.8 VDD -0.8 0.7•VDD 0.8•VDD VSS VSS 0.1•VDD TYP VDD -0.4 VDD -0.4 VDD -0.4 0.2 0.2 1.0 MAX 0.1 0.4 0.4 VDD VDD 0.3•VDD 0.2•VDD 0.5•VDD UNITS V V V V V V V V V V V V Output High Voltage: PA0-7, PD0-4, VPWOUT, TCMP Output High Voltage: OSCOUT Output High Voltage: MISO, MOSI, SCK, OSCB Output Low Voltage: OSCOUT Output Low Voltage: MISO, MOSI, SCK, OSCB Input High Voltage: PA0-7, PD0-4, MISO, MOSI, SS, SCK Input High Voltage: RESET, IRQ, TCAP, VPWIN, OSCIN Input Low Voltage: PA0-7, PD0-4, MISO, MOSI, SS, SCK Input Low Voltage: RESET, IRQ, TCAP, VPWIN, OSCIN Input Hysteresis Voltage: RESET, IRQ, TCAP, VPWIN, OSCIN Supply Current RUN WAIT (Note 2) STOP (Notes 2, 3) VOH VOH VOH VOL VOL VIH VIH VIL VIL VHYS IRUN IWAIT ISTOP fOSC = 10MHz External Square Wave TA = 25oC TA = -40oC to 125oC -10 -1 8 3.2 2 10 ±0.01 .001 18 10 50 250 +10 +1 mA mA µA µA µA µA I/O Ports Hi-Z Leakage Current: PA0-7, PD0-4, MISO, MOSI, SCK Input Current: RESET, IRQ, TCAP, OSCIN, VPWIN, SS IIL IIN 3 HIP7030A2 DC Electrical Specifications PARAMETER Capacitance: (Note 4) VDD = 5VDC ±10%, VSS = 0VDC, TA = -40oC to +125oC Unless Otherwise Specified (Continued) SYMBOL COUT CIN Powerdown Input Voltage: RESET, IRQ, VPWIN, OSCIN Comparator: Input Voltage: Input Current: Offset Voltage Response NOTES: 1. This device contains circuitry to protect the inputs against damage due to high static voltages of electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that VIN and VOUT be constrained to the range VSS96 >163 >239 >239 >280 NOMINAL NA 64 128 200 280 300 300 MAXIMUM ≤ 34 ≤ 96 ≤ 163 ≤ 239 NA NA NA The terms short and long are often used to refer to pulses of duration TV1 and TV2 respectively. VPW is a non-return-to-zero (NRZ) protocol in which each transition represents a complete bit of information. Accordingly, a 0 data bit will sometimes be transmitted as a passive pulse and sometimes as an active pulse. Similarly, a 1 data bit will sometimes be transmitted as a passive pulse and sometimes as an active pulse. In order to accommodate arbitration (see Bus Arbitration) a long active pulse represents a 0 data bit and a short active pulse represents a 1 data bit. Complementing this fact, a short passive pulse represents a 0 and a long passive pulse represents a 1. Starting from a transition to the active state, a 0 data bit will maintain the active level longer than a 1. Similarly, starting from a transition to the passive state, a 0 data bit will return to the active level quicker than a 1. These facts give rise to the dominance of 0’s over 1’s on the J1850 bus as depicted in Figure 25. See Bus Arbitration for additional details. SYNCHRONIZED 0 DATA BIT 0 1 DATA BIT 1 LONGER ACTIVE PULSE (0) CONTROLS THE BUS J1850 BUS 0 FIGURE 25A. DOMINANCE OF ACTIVE 0 DATA BIT SYNCHRONIZED 0 DATA BIT 0 1 DATA BIT 1 SHORTER PASSIVE PULSE (0) CONTROLS THE BUS J1850 BUS 0 FIGURE 25B. DOMINANCE OF PASSIVE 0 DATA BIT 34 HIP7030A2 Table 6 summarizes the complete set of symbol definitions based on duration and state. TABLE 6. J1850 SYMBOL DEFINITIONS SYMBOL 0 Data 1 Data SOF (Start of Frame) EOD (End of Data) EOF (End of Frame) IFS (Inter-Frame Separation) IDLE (Idle Bus) NB (Normalization Bit) BRK (Break) DEFINITION Passive TV1 or Active TV2 Active TV1 or Passive TV2 Active TV3 Passive TV3 Passive TV4 Passive TV6 Passive >TV6 nom Active TV1 or Active TV2 Active TV5 • Type 2 - One byte IFRs from multiple respondents (no CRC byte) • Type 3 - Multiple byte IFR from a single respondent (CRC appended) Bus Arbitration The nature of multiplexed communications leads to contention issues when two or more nodes attempt to transmit on the bus simultaneously. Within J1850 VPW systems, messages are assigned varying levels of priority which allows implementation of an arbitration scheme to resolve potential contentions. The specified arbitration is performed on a symbol by symbol basis throughout the duration of every message. Arbitration begins with the rising edge of the SOF pulse. No node should attempt to issue an SOF until an Idle bus has been detected (i.e., an Inter-Frame Separation (IFS) symbol with a period of TV6 has been received). If multiple nodes are ready to access the bus and are all waiting for an IFS to elapse, invariable skews in timing components will cause one arbitrary node to detect the Idle condition before all others and start transmission first. For this reason, all nodes waiting for an IFS will consider an IFS to have occurred if either: - An IFS nominal period has elapsed or, - An EOF minimum period has elapsed and a rising edge has been detected Arbitrating devices will all be synchronized during the SOF. Beginning with the first data bit and continuing to the EOF, every transmitting device is responsible for verifying that the symbol it sent was the symbol which appeared on the bus. Each transition, every transmitting node must decode the symbol, verify the received symbol matches the one sent, and begin timing of the next symbol. Since timing of the next symbol begins with the last transition detected on the bus, all transmitters are re-synchronized each symbol. When the received symbol doesn’t match the symbol sent, a conflict (bit collision) occurs. Any device detecting a collision will assume it has lost arbitration and immediately relinquish the bus. Typically, after losing arbitration, a device will attempt re-transmission of the message when the bus once again becomes Idle. The definition of 1 and 0 data bits (see Table 6 and discussion under VPW Symbol Definitions) leads to 0’s having priority over 1’s in this arbitration scheme. Header bytes are generally assigned such that arbitration is completed before the first data byte is transmitted. Because of the dominance of 0-bits and the MSB first bit order, a header with the hexadecimal value $00 will have highest priority, then $01, $02, $03, etc. An example of two nodes arbitrating for control of the bus is shown in Figure 27. In Frame Response (IFR) The distinction between two of the passive symbols, EOD and EOF, is subtle but important (refer to Figure 26). The EOD (TV3) interval signifies that the originator of the message is done broadcasting and any nodes which have been requested to respond (i.e., to acknowledge receipt of the message) can now do so. The EOD interval begins when the transmitting node has completed sending the eighth bit of the check byte. The transmitter simply releases the bus and allows it to revert to a passive state. In the course of normal messaging, no node can seize the bus until an EOD time has been detected. Once an EOD has elapsed, any nodes which are scheduled to produce an IFR will arbitrate for control of the bus (see Bus Arbitration) and respond appropriately. If no responses are forthcoming the bus remains in the passive state until an EOF (TV4) interval has elapsed. After the EOF has been generated, the frame is considered closed and the next communications on the bus will represent a totally new message. IFRs can consist of multiple bytes from a single respondent, one byte from a single respondent, or one byte from multiple respondents. In all cases the first response byte must be preceded by a normalization bit (NB) which serves as a start of response symbol and places the bus in an active state so that following the IFR byte(s) the bus will be left in the passive state. The NB symbol is by definition active, but can be either TV1 or TV2 in duration. The long variety (TV2) signifies the IFR contains a CRC byte. The short variety (TV1) precedes an IFR without CRC. Message Types Messages are classified into one of four Types according to whether the message has an IFR and what kind of IFR it is. The definitions are: • Type 0 - No IFR • Type 1 - One byte IFR from a single respondent (no CRC byte) 35 HIP7030A2 SOF HEADER . . . . DATA N CRC EOD NB IN FRAME RESPONSE EOD EOF FIGURE 26. J1850 MESSAGE WITH IN-FRAME-RESPONSE TRANSMITTER A 0 0 0 0 0 1 0 COLLISION DETECTEDBY B TRANSMITTER B 0 0 01 J1850 BUS IFS SOF HEADER (1 OR 3 BYTES) DATA 1 . . . DATA N CRC EOF FIGURE 27. TWO NODES ARBITRATING FOR CONTROL OF J1850 BUS Arbitration also takes place during the IFR portion of a message, if more than one node is attempting to generate a response. Arbitration begins with the NB symbol, which follows the EOD and precedes the first IFR byte. For Type 1 and Type 3 messages only the respondent which successfully arbitrates for control of the bus produces an IFR. All other respondents abort their IFRs. For Type 2 messages, all respondents which lose arbitration must count symbols and re-attempt transmission at the end of each byte. Each node, which successfully responds, eliminates itself from the subsequent arbitration until all nodes have responded. This arbitration scheme limits each respondent to a single byte during a Type 2 IFR. Break To force a message to be aborted before EOF is reached, a break (BRK) symbol can be transmitted by any node. The BRK symbol is an active pulse of duration TV5. Reception of a break causes all nodes to reset to a ready-to-receive state and to re-arbitrate for control following an IFS. Every symbol sent out on the VPWOUT is in effect inverted and echoed back on the VPWIN pin after some finite delay through the transceiver. In actuality, only long active symbols are guaranteed to be echoed unchanged. If the transmitted symbol is passive and another node is simultaneously sending an active symbol, the active symbol will dominate and pull the bus to a high level. The SENDEC circuitry includes a 3-bit digital filter which effectively filters out noise pulses less than 7µs in duration. Communications between the CPU and the SENDEC are via three registers mapped into Page 0 of the MCUs memory space. When transmitting symbols, the desired symbol is specified by writing an appropriate code to the SENDEC Data Register (SEDDR). Timing of each symbol is calculated from the last transition on the VPWIN line. Each write to the SEDDR, which occurs within 34µs of the last received transition, will enable the VPWOUT pin and the SENDEC automatically produces a transition on the VPWOUT pin after the proper delay (the seven microseconds added by the digital filter and a 17µs delay through the bus transceiver are compensated for). The VPWOUT pin remains active until 34µs after the last received transition. Failure to write a new symbol during the 34µs window causes the VPWOUT pin to go low until the next valid write or until the Force Start of Frame (FSOF) bit is set in the SENDEC Data Register (SEDDR). Decoding of received symbols is automatically performed by the SENDEC. The decoded symbol is valid until the next transition occurs. The value can be read via the SEDDR. Generally the SENDEC is programmed to interrupt the MCU with each transition on the VPWIN pin. When the SENDEC is receiving a message, the interrupt signals that a new symbol has been received and appropriate actions must be taken to read and process the symbol. When the SENDEC is transmitting, the transition interrupt signifies that the reflected symbol has been received, and it is time to start Variable Pulse Width Symbol Encoder Decoder (SENDEC) Overview Of SENDEC Operation The SENDEC hardware integrated in the HIP7030A2 facilitates generation and reception of J1850 messages on a symbol by symbol basis. Symbols are output from the SENDEC, as a digital signal, on the VPWOUT pin and input, as a digital signal, on the VPWIN pin. These two lines must be connected through a bus transceiver (such as the Intersil J1850 Bus Transceiver HIP7020) to the single wire J1850 bus. The transceiver is responsible for generating and receiving waveforms consistent with the physical layer specifications of J1850. In addition, the transceiver is responsible for providing isolation from bus transients. 36 HIP7030A2 timing the next symbol. The reflected symbol should be read and compared to the previously sent one. If the reflected symbol doesn’t match the symbol sent, a collision has occurred and the software must cease transmissions until the next idle period. If there was no collision, the new symbol must be immediately (within one TV1 minimum time) written to the SEDDR (the SEDDR is not buffered). In addition to features already discussed, the SENDEC includes, noise detection, idle bus detection, a clock prescaler, an echo fail detector, a wake-up facility, and a high speed receive mode. Symbol timing is based on the main MCU oscillator. The programmable prescaler allows proper SENDEC operation with 10MHz, 8MHz, or 4MHz oscillators. The high speed receive mode is a J1850 extension which allows maintenance equipment to transmit messages at 4X the normal 10.4Kbps rate. Software algorithms can be employed to implement message buffering and filtering, CRC generation and detection, IFR handling, and other needed features to create a complete J1850 VPW node. See the Applications section for typical algorithms. SENDEC Registers The SENDEC register set consists of the read-write SENDEC Data Register (SEDDR), the read-write SENDEC Control Register (SEDCR), and the read-only SENDEC Status Register (SEDSR). A detailed description of the operation of each follows: SENDEC Control Register (SEDCR) The SENDEC Control Register (SEDCR, location $0F) is an 8-bit read/write register which contains five control bits. One of the bits controls interrupts which are associated with a flag bit in the SENDEC Status Register (discussed following). Three bits control the clock prescaler and the high speed 4X mode of the SENDEC. The final bit doesn’t directly control the SENDEC, rather it controls the start-up delay following exit from the STOP mode of the processor. The bit assignments are illustrated below, followed by a detailed description of each bit. 7 TXIE 6 5 4 NDEL 3 2 4X 1 PRE1 0 PRE0 continues to run when the device enters STOP mode or when a ceramic resonator based oscillator is used. NDEL should not be used when the HIP7030A2 is driven by a quartz crystal based oscillator. NDEL is cleared by RESET and POR. B2, 4X When set, the 4X bit causes the SENDEC symbol timing to be accelerated by a factor of four. Due to fixed delays in the loop back from VPWOUT to VPWIN, the 4X mode is only useful for receiving symbols. 4X mode is intended for high speed data linking between the HIP7030A2 and maintenance or test equipment which has capability to send at the accelerated rate. Writing to the 4X bit is inhibited except when the NEW bit in the SENDEC Status Register (SEDSR) is set. Once modified, the new value of 4X doesn’t take effect until the next transition on the VPWIN pin. Receipt of a Break symbol on the VPWIN line will automatically clear 4X. RESET and POR clear the 4X bit. B1, PRE1; B2, PRE0 PRE1 and PRE0 control the SENDEC clock prescaler. The SENDEC circuit requires a fundamental clock of 1MHz. To generate the 1MHz frequency, while allowing a choice of MCU oscillator frequencies, the PRE1 and PRE0 bits must be set to match the OSCIN frequency. TABLE 7. SENDEC PRESCALER BIT SELECTION PRE1 PRE0 OSCIN FREQUENCY (MHz) 0 0 1 1 0 1 0 1 4 8 10 12 SEDCR (LOCATION $0F) B7, TXIE If the transition interrupt enable (TXIE) bit is set, the MCU will receive a SENDEC interrupt on the occurrence of each transition on the VPWIN line. If TXIE is low the TX interrupts are inhibited but the associated flags in the SENDEC Status Register (SEDSR) are still set (see discussion following). TXIE is cleared by RESET. B4, NDEL When set, the No Delay (NDEL) bit suppresses the 4064 tCYC delay which is normally introduced when exiting from the STOP mode via an interrupt. Instead of the 4064 tCYC delay a 96 tCYC delay is introduced. NDEL is intended for applications where the clock source to the HIP7030A2 Following RESET a window of 4 instructions is allowed for setting the PRE1 and PRE0 bits. Writes to these bits after the fourth instruction have no effect on their values. Table 7 gives the proper settings of PRE1 and PRE0 for various frequencies. RESET and POR force PRE1 to a 1 and PRE0 to a 0, selecting the 10MHz mode. SENDEC Status Register (SEDSR) The SENDEC Status Register (SEDSR, location $10) is an 8-bit read-only register which contains seven status bits. One of the bits is a flag bit which correspond to the interrupt control bit in the SENDEC Control Register (discussed earlier). Three other bits provide error status information. 37 HIP7030A2 Another two bits provide an indication of special symbols (Break, IFS) occurring on the bus. The final bit indicates the transmit status of the SENDEC. The bit assignments are illustrated below, followed by a detailed description of each bit. 7 TX 6 BRK 5 NEW 4 NOIZ 3 OVR 2 TALK 1 NECHO 0 - SOF symbol), the NEW flag is cleared on the active to passive transition. Polling NEW provides a convenient means for software to determine that transmission of a new message can be commenced. NEW is cleared by all resets. B4, NOIZ The noise (NOIZ) flag indicates that a symbol shorter than a legal TV1 has been received. NOIZ is cleared by a sequence of first reading the SEDSR followed by reading or writing the SEDCR. NOIZ is cleared by RESET. B3, OVR The overrun (OVR) flag is set if TALK is set in the SEDSR and a minimum short symbol time (34µs) has elapsed since the last transition and no write to the SEDDR has taken place. An overrun condition is a serious error and the user should treat it as such. When OVR is set it automatically forces the VPWOUT pin to a low level. OVR is cleared by a sequence of first reading the SEDSR followed by reading or writing the SEDCR. Setting of OVR is inhibited while NEW is true in the SEDSR. OVR is cleared by RESET. B2, TALK The transmit (TALK) flag is set if the HIP7030A2 is actively transmitting symbols via the SENDEC. TALK is set by writing a non-zero to the SEDDR (see SENDEC Data Register for details). The TALK bit is cleared by writing a $00 to the SEDDR, when NECHO is set, or when OVR is set. TALK is cleared by RESET. B1, NECHO The No Echo Received (NECHO) flag is set if, during the process of transmitting a symbol, the expected echo of the symbol is not received. This event will cause the VPWOUT pin to be forced to a 0 level. Setting of NECHO automatically clears the TALK bit. The time required to detect an echo failure is dependent on many factors. The minimum time to detect a failure is 105µs (26µs in 4X mode) and the maximum time to detect a failure is 512µs. When NECHO goes from a low to a high level, a SENDEC interrupt will be generated if the I-bit is cleared in the CC register. NECHO must go low then high again to generate another interrupt. NECHO is cleared by a sequence of first reading the SEDSR followed by reading or writing the SENDEC Data Register (SEDDR). NECHO is cleared by all resets. SEDSR (LOCATION $10) B7, TX The transition (TX) flag bit indicates that a transition has occurred on the VPWIN line. The line is first filtered through the SENDECs 3-bit digital filter to reject noise. Once set the TX flag will interrupt the MCU if the TXIE bit in the SEDCR is set and the I bit in the condition code register is clear. TX is cleared by a sequence of first reading the SEDSR followed by reading or writing the SENDEC Data Register (SEDDR). Note that both TX and NEW will be set on the leading edge of an SOF. See description of the NEW flag below. TX is cleared by RESET. B6, BRK The break (BRK) bit indicates that a break symbol has been detected on the VPWIN line. BRK is set at the end of the break symbol, on the active to passive transition. Once set the BRK flag will interrupt the MCU if the I-bit is cleared in the condition code register. BRK is cleared by a sequence of first reading the SEDSR followed by a read or write of the SEDCR. BRK is cleared by RESET. B5, NEW The new frame (NEW) flag indicates that one of two possible events has been detected on the J1850 bus: The bus has been passive for at least an IFS nominal symbol time (i.e., the bus is Idle) or, A transition has occurred on the bus following an EOF minimum (i.e., another node has started a new message). NEW is set when either of these events is detected. In the case of a transition following an EOF, the TX bit is also set. When NEW goes from a 0 to a 1, a SENDEC interrupt will be generated if the I-bit is cleared in the CC register. The NEW interrupt can be cleared under software control by reading the SEDSR followed by reading or writing the SEDCR. This only removes the source of the interrupt and does not clear the NEW bit. The NEW flag cannot be cleared by software. It is automatically cleared 128 (nominal) microseconds into the next (or current - if NEW was set by a transition following EOF) symbol. This is normally during the SOF of a new message. If the symbol is less than 128µs in duration (an illegal 38 HIP7030A2 SENDEC Data Register The SENDEC Data Register (SEDDR, location $11) is an 8bit read/write register which contains one write-only bit, three read/write bits, and four read-only bits. The write only bit triggers SOF symbols required to initiate new transmissions, the three read/write bits are used to specify transmitted symbol durations, and the four read only bits uniquely identify the received J1850 symbol. Reading the SEDDR at anytime provides the received symbol which resulted from the last transition of VPWIn. When writing data to the SEDDR, the value represents the duration of the symbol currently being transmitted. The bit assignments are illustrated below, followed by a detailed description. 7 FSOF 6 S2 5 S1 4 S0 3 LEV 2 R2 1 R1 0 R0 Writing a $00, at anytime, immediately disables transmissions (forcing the VPWOUT pin low) and clears the TALK bit in the SEDSR. This is the preferred method to end transmissions. RESET doesn’t affect S2-S0 TABLE 8. S2-S1 SYMBOL ENCODING S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 TRANSMIT SYMBOL Disable Transmit TV1 TV2 TV3 TV1 TV1 TV1 TV1 SEDDR (LOCATION $11) B7, FSOF Writing a 1 to the Force Start of Frame (FSOF) bit while simultaneously writing a non-zero value to S2-0, causes the VPWOUT to immediately go active (high level). The low to high transition will eventually be reflected on the VPWIN line causing a TX interrupt. Upon receipt of the TX interrupt an SOF symbol (S2-0 = 3) must be written to the SEDDR to time the high SOF. Setting the FSOF bit can only be done when the NEW flag is set in the SENDEC Status Register (NEW is set when the J1850 bus is idle or during the first portion of an SOF symbol). FSOF is a write only bit. Reading FSOF always returns a 0. B6, S2; B5, S1; B4, S0 When writing to the SEDDR, the three bits (S2-0) determine the transmitted symbol as shown in Table 8. During a write to the SEDDR the S2-0bits are ignored except in three specific situations: The NEW flag is high in the SEDSR) or, or, S2-0-bits = 0 In the first two cases, each write to the SEDDR will produce one properly timed symbol on the VPWOUT pin. The completion of the symbol is reported to the controller, not at the end of the transmitted symbol, but at the end of the symbol echoed back via the VPWIN input. Writing the FSOF bit, in conjunction with S2-0 = 3, produces the initial transition for the SOF symbol. All timing for a message begins with the receipt of that transition. A transition has been received on the VPWIN pin, from the bus, within the past 34µs B3, LEV; B2, R2; B1, R1; B0, R0 These four bits uniquely identify all symbols received via the VPWIN pin. The symbol decoding map is shown in Table 9. R2-0 represent the duration of the symbol and LEV represents the level of the symbol (active or passive) These bits are only updated upon detection of a bus transition and therefore reflect the last symbol received. An exception to this is for an Idle bus. When an Idle has been detected the values in R2R0 and LEV are immediately updated - no bus transition is necessary. R2-R0 = 101 with LEV = 0 indicates that the bus is currently Idle. Note that R2-0 combinations of 110 and 111 will not be produced by the SENDEC. A value of 101 represents all durations equal to and beyond an IFS/IDLE (for the passive case) and a BREAK (for the active case). RESET does not affect LEV or R2-R0. When a transition is detected on VPWIN, the received symbol is decoded and made available for reading via the SEDDR. The TX bit is set in the SEDSR and, if TXIE is high in the SEDCR, an interrupt will be generated. Once the transition is detected the next symbol begins timing out. A new symbol must be written to the SEDDR, before the minimum transmit time for a short symbol has elapsed (34µs). Failure to write to the SEDDR in time will result in the OVR bit being set and transmission aborted. This is a safety precaution to prevent “streaming” messages. The control routines should verify that the symbol sent matches the symbol received. A mismatch indicates the device has lost control of the bus. It is up to the user code to handle the collision, in terms of disabling the SENDEC, requeueing of the message, filtering the incoming message, etc. 39 HIP7030A2 TABLE 9. R2-R0 AND LEV SYMBOL DECODING R2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LEV 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RECEIVE SYMBOL Passive Noise Active Noise TV1 Passive TV1 Active TV2 Passive TV2 Active EOD SOF EOF BREAK IFS/IDLE BREAK - and capacitive components. Each positive transition on the OSCIN line reinitializes the timer. In the absence of frequent enough transitions on the input, the timer will eventually reach a preset limit at which point the MCU will be reset via a COP interrupt. When the frequency has dropped below the preset threshold a COP reset will take place. A COP reset is identical to a POR or RESET pin reset, except the restart vector is the COP Vector. Following the COP reset the HIP7030A2 is held reset until the start-up timeout of 4064 clocks has been reached. During the 4064 clocks the Slow Clock Detect circuit is inhibited. If at the end of the 4064 clocks the frequency remains below the threshold, a COP reset will immediately take place again. The primary purpose of this circuit is to force the HIP7030A2 off of the J1850 and SPI busses should the oscillator circuit fail. Due to variability of integrated resistors and capacitors there is a non-critical spread in the timeout specification of approximately 10:1. Maximum threshold is 200kHz. Refer to fSLOW in Electrical Specifications for details. There is no means to disable the Slow Clock Detect. RESET resets the Slow Clock Detect circuit and holds it reset until the start-up timeout of 4064 clocks has been reached and the RESET pin has gone high. Watchdog Timer The Watchdog Timer is a free-running 21 stage counter which divides the OSCIN input by 2,097,152. The Timer is software reset-able, and must be constantly reset before the terminal count is reached. Failure to reset the Watchdog Timer, in due time, results in a forced MCU RESET via a COP interrupt. 7 6 5 4 3 2 1 0 In the receive mode (i.e., no writes to the SEDDR) the controller typically responds to the TX interrupts and reads the incoming symbols as they become available, performing necessary real-time operations such as filtering messages, computing and verifying CRCs, and issuing IFRs. Computer Operating Properly (COP) System Introduction The Computer Operating Properly (COP) system is comprised of two basic circuit components. One is a free running watchdog timer which, left unattended, generates a periodic MCU reset. The second is a Slow Clock Detect circuit which constantly monitors the OSCIN line for activity. A lack of activity on OSCIN will generate a reset. Both circuits are capable of generating a COP interrupt which forces an MCU reset and restarts operation at the vector specified by the contents of location $1FFA, $1FFB. Because the COP interrupt behaves as a reset, the stack pointer is cleared and exiting the COP interrupt software handler must be done via a jump instruction as opposed to an RTI or RTS. The Watchdog Status Register (WSR, location $1E) contains a flag (Watchdog Flag - WDF, bit 0) which is set whenever a Watchdog Timer overflow interrupt occurs. The WDF bit is cleared by a POR or a write to the Watchdog Reset Register (WRR, location $1D) with bit 0 = 0. The WDF can be used to distinguish the type of COP reset (Watchdog timeout vs. Slow Clock Detect) which has occurred. Following are the details of each of the two circuit. Slow Clock Detect Circuit The Slow Clock Detect Circuit consists of a reset-able timer element. The timer is constructed with integrated resistive Watchdog Reset Register WRR (LOCATION $1D) Resetting the Watchdog Timer requires two distinct operations. A write of the value $55 to the Watchdog Reset Register (WRR, location $1D) must be followed by a write of the value $AA to the WRR. There is no limit on the time between the writes, other than both must take place before the Watchdog Timer has reached its limit. Typically the two writes are placed in distinct sections of code, which can only be reached by proper flow through the software. Each time that a write is made to the WRR with bit 0 = 0, the Watchdog Flag in the WSR is cleared. This will happen as a normal side effect of clear the Watchdog Timer via the $55, $AA sequence. The Watchdog flag is also cleared by POR. RESET and Slow Clock Detect do not affect the WDF. It is set by a Watchdog Timer overflow and can be used to distinguish a Slow Clock Detect reset from the Watchdog reset, both of which share the COP reset vector ($1FFA,$1FFB). 7 0 6 0 5 0 4 0 3 0 2 0 1 1 0 WDF WSR (LOCATION $1E) 40 HIP7030A2 Watchdog timeout periods for various OSCIN frequencies are given in Table 10. There is no mechanism to disable the Watchdog Timer. RESET clears the Watchdog Timer to its initial value. TABLE 10. WATCHDOG TIMEOUTS FOR COMMON OSCIN FREQUENCIES WATCHDOG TIMEOUT 175ms 210ms 262ms 524ms OSCIN FREQUENCY (MHz) 12 10 8 4 the IRQ pin, then the counter resumes from its stopped value as if nothing had happened. Another feature of the programmable timer, in the STOP mode, is that if at least one valid input capture edge occurs at the TCAP pin, the input capture detect circuitry is armed. This action does not set any timer flags or “wake up” the MCU, but when the MCU does “wake up” there will be an active input capture flag (and data) from that first valid edge which occurred during the STOP mode. If the STOP mode is exited by an external reset (logic low on RESET pin), then no such input capture flag or data action takes place even if there was a valid input capture edge (at the TCAP pin) during the MCU STOP mode. SENDEC During STOP Mode When the MCU enters the STOP mode, the absence of any internal clocks causes all SENDEC functions, except Wake Up to cease. If the SENDEC was currently being used to transmit a symbol, that symbol is truncated and the VPWOUT is forced to a low (passive) state. For proper operation, a STOP instruction should not be executed except when the bus is idle. Normally all transitions are first filtered through the SENDECs 3-bit digital filter. When in STOP mode the 3-bit filter is bypassed and any passive to active transition (high to low) on VPWIN will cause a SENDEC interrupt which will, in turn, cause the processor to exit the STOP mode. Upon exiting the STOP mode the processor will execute a SENDEC interrupt. The setting of the TX bit in the SEDSR does not bypass the 7µs filter and as such the TX bit will not be set when first awakening from STOP. If the NDEL bit has been set prior to entering STOP, software should delay 8µs and check TX. If at that time TX has not been set, the assumption can be made that a noise pulse caused the wakeup and the STOP mode can be reentered. When NDEL is not employed monitoring of TX must continue for several hundred microseconds, as a complete message could have transpired during the oscillator start-up time. During handling of a SENDEC interrupt following STOP, the SEDSR must be read at least one time to remove the source of the interrupt. SPI During STOP Mode When the MCU enters the STOP mode, the baud rate generator which drives the SPI shuts down. This essentially stops all master mode SPI operation. To ensure the SPI bus remains free for transfers, the MSTR bit in the SPCR is cleared, configuring the SPI pins in slave mode. If the STOP instruction is executed during an SPI transfer, in which the HIP7030A2 was the master, that transfer is aborted. If the STOP mode is exited by a RESET, then the appropriate control/status bits are cleared and the SPI is disabled. If the device is in the slave mode when the STOP instruction is executed, the slave SPI will still operate. It can still accept data and clock information in addition to transmitting its own data back to a master device. At the end of a possible transmission with a slave SPI in the STOP mode, no flags are set until an IRQ or SENDEC interrupt results in an MCU “wake up”. Caution should be observed when operating the SPI (as a slave) during the STOP mode because none of the protection circuitry (write collision, mode fault, etc.) is active. Effects of Stop and Wait Modes on the Timer, COP, and Serial Systems Introduction The STOP and WAIT instructions have different effects on the programmable timer, VPW Symbol Encoder/Decoder (SENDEC), and serial peripheral interface (SPI) systems. These effects are discussed separately below. Stop Mode When the processor executes the STOP instruction, the internal oscillator is turned off. This halts all internal CPU processing including the operation of the programmable timer, serial communications interface, and serial peripheral interface. The only way for the MCU to “wake up” from the STOP mode is by receipt of an external interrupt (logic low on IRQ pin), a negative edge on the VPWIN pin, or by the detection of a RESET (logic low on RESET pin or a poweron reset). Execution will resume at the instruction immediately following the STOP instruction that caused the HIP7030A2 to enter the STOP mode. Normally a start-up delay of 4064 tCYC is inserted after exiting from STOP before fetching the first instruction. This delay is intended to guarantee stability of a crystal clock source. If it is known that the clock source will be stable prior to exiting STOP, then the NDEL bit in the SEDCR can be set prior to executing the STOP instruction. Setting NDEL has the effect of shortening the start-up delay to 96 tCYC. The effects of the STOP mode on each of the MCU systems (COP, Timer, SENDEC, and SPI) are described separately in the following sections. COP During STOP Mode When the MCU enters the STOP mode, the Watchdog Timer and the Slow Clock Detect circuits are both inhibited. Timer During STOP Mode When the MCU enters the STOP mode, the timer counter stops counting (the internal processor is stopped) and remains at that particular count value until the STOP mode is exited by an interrupt (if exited by RESET the counter is forced to $FFFC). If the STOP mode is exited by an external low on 41 Wait Mode When the MCU enters the WAIT mode, the CPU clock is halted. All CPU action is suspended; however, the timer, SENDEC, and SPI systems remain active. In fact an interrupt from the timer, SENDEC, or SPI (in addition to a logic low on the IRQ or RESET pins) causes the processor to exit the WAIT mode. Since the three systems mentioned above operate as they do in the normal mode, only a general discussion of the WAIT mode is provided below. Note that the Slow Clock Detect and Watchdog Timer circuitry continues to function during WAIT. It is requisite upon the designed to ensure that the CPU is removed from WAIT (via an external or TIMER or SENDEC interrupt) frequently enough to prevent a Watchdog Timer overflow. The WAIT mode power consumption depends on how many systems are active. The power consumption will be highest when all the systems (timer, TCMP, SENDEC, and SPI) are active. The power consumption will be the least when the SENDEC and SPI systems are disabled (timer operation cannot be disabled in the WAIT mode). If a non-RESET exit from the WAIT mode is performed (i.e., timer overflow interrupt exit), the state of the remaining systems will be unchanged. If a RESET exit from the WAIT mode is performed all the systems revert to the disabled reset state. Instruction Set The MCU has a set of 62 basic instructions. They can be divided into five different types: register/memory, read-modify-write, branch, bit manipulation, and control. The following paragraphs briefly explain each type. All the instructions within a given type are presented in individual tables. Register/Memory Instructions Most of these instructions use two operands. The first operand is either the accumulator or the index register. The second operand is obtained from memory using one of the addressing modes. The operand for the jump unconditional (JMP) and jump to subroutine (JSR) instructions is the program counter. Refer to Table 11. Read-Modify-Write Instructions These instructions read a memory location or a register, modify or test its contents, and write the modified value back to memory or to the register. The test for negative or zero (TST) instruction is an exception to the read-modify-write sequence since it does not modify the value. Refer to Table 12. 42 TABLE 11. REGISTER/MEMORY INSTRUCTIONS ADDRESSING MODES IMMEDIATE FUNCTION Load A from Memory Load X from Memory Store A in Memory Store X in Memory Add Memory to A Add Memory and Carry to A Subtract Memory Subtract Memory From A with Borrow AND Memory to A OR Memory with A Exclusive OR Memory with A Arithmetic Compare A with Memory Arithmetic Compare X with Memory Bit Test Memory with A (Logical Compare) Jump Unconditional Jump to Subroutine DIRECT EXTENDED INDEXED (NO OFFSET) INDEXED (8-BIT OFFSET) INDEXED (16-BIT OFFSET) OP NO. NO. OP NO. NO. OP NO. NO. OP NO. NO. OP NO. NO. OP NO. NO. MNEM CODE BYTES CYCLES CODE BYTES CYCLES CODE BYTES CYCLES CODE BYTES CYCLES CODE BYTES CYCLES CODE BYTES CYCLES LDA LDX STA STX ADD ADC SUB SBC A6 AE AB A9 A0 A2 2 2 2 2 2 2 2 2 2 2 2 2 B6 BE B7 BF BB B9 B0 B2 2 2 2 2 2 2 2 2 3 3 4 4 3 3 3 3 C6 CE C7 CF CB C9 C0 C2 3 3 3 3 3 3 3 3 4 4 5 5 4 4 4 4 F6 FE F7 FF FB F9 F0 F2 1 1 1 1 1 1 1 1 3 3 4 4 3 3 3 3 E6 EE E7 EF EB E9 E0 E2 2 2 2 2 2 2 2 2 4 4 5 5 4 4 4 4 D6 DE D7 DF DB D9 D0 D2 3 3 3 3 3 3 3 3 5 5 6 6 5 5 HIP7030A2 5 5 43 AND ORA EOR CMP A4 AA A8 A1 2 2 2 2 2 2 2 2 B4 BA B8 B1 2 2 2 2 3 3 3 3 C4 CA C8 C1 3 3 3 3 4 4 4 4 F4 FA F8 F1 1 1 1 1 3 3 3 3 E4 EA E8 E1 2 2 2 2 4 4 4 4 D4 DA D8 D1 3 3 3 3 5 5 5 5 CPX A3 2 2 B3 2 3 C3 3 4 F3 1 3 E3 2 4 D3 3 5 BIT A5 2 2 B5 2 3 C5 3 4 F5 1 3 E5 2 4 D5 3 5 JMP JSR - - - BC BD 2 2 2 2 CC CD 3 3 3 3 FC FD 1 1 2 5 EC ED 2 2 3 6 DC DD 3 3 4 7 TABLE 12. READ-MODIFY-WRITE INSTRUCTIONS ADDRESSING MODES INHERENT (A) FUNCTION Increment Decrement Clear Complement Negate (2’s Complement) Rotate Left Thru Carry Rotate Right Thru Carry Logical Shift Left MNEM INC DEC CLR COM NEG ROL ROR LSL LSR ASR TST MUL OP CODE 4C 4A 4F 43 40 49 46 48 44 47 4D 42 NO. NO. BYTES CYCLES 1 1 1 1 1 1 1 1 1 1 1 1 3 3 3 3 3 3 3 3 3 3 3 11 INHERENT (X) OP CODE 5C 5A 5F 53 50 59 56 58 54 57 5D NO. NO. BYTES CYCLES 1 1 1 1 1 1 1 1 1 1 1 3 3 3 3 3 3 3 3 3 3 3 OP CODE 3C 3A 3F 33 30 39 36 38 34 37 3D DIRECT NO. NO. BYTES CYCLES 2 2 2 2 2 2 2 2 2 2 2 5 5 5 5 5 5 5 5 5 5 4 OP CODE 7C 7A 7F 73 70 79 76 78 74 77 7D INDEXED (NO OFFSET) NO. NO. BYTES CYCLES 1 1 1 1 1 1 1 1 1 1 1 5 5 5 5 5 5 5 5 5 5 4 INDEXED (8-BIT OFFSET) OP CODE 6C 6A 6F 63 60 69 66 68 64 67 6D NO. NO. BYTES CYCLES 2 2 2 2 2 2 2 2 2 2 2 6 6 6 6 6 6 6 HIP7030A2 6 6 6 5 - 44 Logical Shift Right Arithmetic Shift Right Test for Negative or Zero Multiply HIP7030A2 Branch Instructions Most branch instructions test the state of the condition code register and if certain criteria are met, a branch is executed. This adds an offset between -127 and +128 to the current program counter. Refer to Table 13. TABLE 13. BRANCH INSTRUCTIONS RELATIVE ADDRESSING MODE OP CODE 20 21 22 23 NO. BYTES 2 2 2 2 NO. CYCLES 3 3 3 3 TABLE 14B. BIT TEST AND BRANCH INSTRUCTIONS OP CODE 2•n 01 + 2•n NO. BYTES 3 3 NO. CYCLES 5 5 Clear Bit n bytes (page zero). An additional feature allows the software to test and branch on the state of any bit within the first 256 locations. The bit set, bit clear, and bit test and branch functions are all implemented with a single instruction. For the test and branch instructions, the value of the bit tested is automatically placed in the carry bit of the condition code register. Refer to Table 14. TABLE 14A. BIT SET/CLEAR INSTRUCTIONS OP CODE 10 + 2•n 11 + 2•n NO. BYTES 2 2 NO. CYCLES 5 5 FUNCTION Set Bit n MNEM BSET n (n = 0 . . .7) BCLR n (n = 0 . . .7) FUNCTION Branch Always Branch Never Branch IFF Higher Branch IFF Lower or Same Branch IFF Carry Clear (Branch IFF Higher or Same) Branch IFF Carry Set (Branch IFF Lower) Branch IFF Not Equal Branch IFF Equal Branch IFF Half Carry Clear Branch IFF Half Carry Set Branch IFF Plus Branch IFF Minus Branch IFF Interrupt Mask Bit is Clear Branch IFF Interrupt Mask Bit is Set Branch IFF Interrupt Line is Low Branch IFF Interrupt Line is High Branch to Subroutine MNEM BRA BRN BHI BLS BCC 24 2 3 FUNCTION Branch IFF Bit n is Set Branch IFF Bit n is Clear MNEM BRSET n (n = 0 . . . 7) BRCLR n (n = 0 . . . 7) (BHS) 24 2 3 BCS (BLO) BNE BEQ BHCC 25 25 26 27 28 2 2 2 2 2 3 3 3 3 3 Control Instructions These instructions are register reference instructions and are used to control processor operation during program execution. Refer to Table 15. TABLE 15. CONTROL INSTRUCTIONS INHERENT BHCS 29 2 3 FUNCTION MNEM TAX TXA SEC CLC SEI CLI OP CODE 97 9F 99 98 9B 9A NO. BYTES 1 1 1 1 1 1 NO. CYCLES 2 2 2 2 2 2 BPL BMI BMC 2A 2B 2C 2 2 2 3 Transfer A to X 3 Transfer X to A 3 Set Carry Bit BMS 2D 2 3 Clear Carry Bit Set Interrupt Mask Bit BIL 2E 2 3 Clear Interrupt Mask Bit BIH 2F 2 3 Software Interrupt SWI RTS RTI RSP NOP STOP WAIT 83 81 80 9C 9D 8E 8F 1 1 1 1 1 1 1 10 6 9 2 2 2 2 Return from Subroutine Return from Interrupt BSR AD 2 6 Bit Manipulation Instructions The MCU is capable of setting or clearing any bit which resides in the first 256 bytes of the memory space except for ROM, port D data location ($03), serial peripheral status register ($0B), serial communications status register (10), timer status register ($13), and timer input capture register ($14 $15). All port registers, port DDRs, timer, two serial systems, on-chip RAM, and 48 bytes of ROM reside in the first 256 Reset Stack Pointer No-Operation Stop Wait 45 HIP7030A2 Alphabetical Listing The complete instruction set is given in alphabetical order in Table 16. Opcode Map Table 17 is an opcode map for the instructions used on the MCU. Extended In the extended addressing mode, the effective address of the argument is contained in the two bytes following the opcode. Instructions with extended addressing modes are capable of referencing arguments anywhere in memory with a single three-byte instruction. EA = (PC + 1) : (PC + 2); PC ← PC + 3 Address Bus High ← (PC + 1); Address Bus Low ← (PC + 2) Indexed, No Offset In the indexed, no offset addressing mode, the effective address of the argument is contained in the 8-bit index register. Thus, this addressing mode can access the first 256 memory locations. These instructions are only one byte long. This mode is used to move a pointer through a table or to address a frequently referenced RAM or I/O location. EA = X; PC ← PC + 1 Address Bus High ← 0; Address Bus Low ← X Indexed, 8-Bit Offset Here the EA is obtained by adding the contents of the byte following the opcode to that of the index register; therefore, the operand is located anywhere within the lowest 511 memory locations. For example, this mode of addressing is useful for selecting the mth element in a n element table. All instructions are two bytes. The content of the index register (S) is not changed. The content of (PC + 1) is an unsigned 8-bit integer. One byte offset indexing permits look-up tables to be easily accessed in either RAM or ROM. EA = X + (PC + 1); PC ← PC + 2 Address Bus High ← K; Address Bus Low ← X + (PC + 1) where: K = the carry from the addition of x + (PC + 1). Indexed, 16-Bit Offset In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the two unsigned bytes following the opcode. This addressing mode can be used in a manner similar to indexed 8-bit offset, except that this three byte instruction allows tables to be anywhere in memory (e.g., jump tables in ROM). The content of the index register is not changed. EA = X + [(PC + 1) : (PC + 2)]; PC ← PC + 3 Address Bus High ← (PC + 1) + K Address Bus Low ← X + (PC + 2) where: K = The carry from the addition of X + (PC + 2). Relative Relative addressing is only used in branch instructions. In relative addressing, the content of the 8-bit signed byte following the opcode (the offset) is added to the PC if and only if the branch condition is true. Otherwise, control proceeds to the next instruction. The span of relative addressing is limited to the range of -126 to +129 bytes from the branch instruction opcode location. EA = PC + 2 + (PC + 1); PC ← EA if branch taken; otherwise, EA = PC ← PC + 2. Addressing Modes The MCU uses ten different addressing modes to provide the programmer with an opportunity to optimize the code to all situations. The various indexed addressing modes make it possible to locate data tables, code conversion tables, and scaling tables anywhere in the memory space. Short indexed accesses are single byte instructions, while the longest instructions (three bytes) permit accessing tables throughout memory. Short absolute (direct) and long absolute (extended) addressing are also included. One and two byte direct addressing instructions access all data bytes in most applications. Extended addressing permits jump instructions to reach all memory. Table 17 shows the addressing modes for each instruction, with the effects each instruction has on the condition code register. The term “effective address” (EA) is used in describing the various addressing modes, and is defined as the byte address to or from which the argument for an instruction is fetched or stored. The ten addressing modes of the processor are described below. Parentheses are used to indicate “contents of” the location or register referred to; e.g., (PC) indicates the contents of the location pointed to by the PC. An arrow indicates “is replaced by”, and a colon indicates concatenation of two bytes. Inherent In inherent instructions, all the information necessary to execute the instruction is contained in the opcode. Operations specifying only the index register or accumulator, and no other arguments, are included in this mode. Immediate In immediate addressing, the operand is contained in the byte immediately following the opcode. Immediate addressing is used to access constants which do not change during program execution (e.g., a constant used to initialize a loop counter). EA = PC + 1; PC ← PC + 2 Direct In the direct addressing mode, the effective address of the argument is contained in a single byte following the opcode byte. Direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two byte instruction. This includes most on-chip RAM and all I/O registers. Direct addressing is efficient in both memory and time. EA = (PC +1); PC ← PC + 2 Address Bus High 0; Address Bus Low ← (PC + 1) 46 HIP7030A2 Bit Set/Clear Direct addressing and bit addressing are combined in instructions which set and clear individual memory and I/O bits. In the bit set and clear instructions, the byte is specified as a direct address in the location following the opcode. The first 256 addressable locations are thus, accessed. The bit to be modified within that byte is specified in the first three bits of the opcode. The bit set and clear instructions occupy two bytes, one for the opcode (including the bit number) and the other to address the byte which contains the bit of interest. EA = (PC + 1); PC ← PC + 2 Address Bus High ← 0; Address Bus Low ← (PC + 1). Bit Test and Branch Bit test and branch is a combination of direct addressing, bit set/clear addressing, and relative addressing. The actual bit to be tested, within the byte, is specified within the low order nibble of the opcode. The address of the data byte to be tested is located via a direct address in the location following the opcode byte (EA1). The signed relative 8-bit offset is in the third byte (EA2) and is added to the PC if the specified bit is set or cleared in the specified memory location. This single three byte instruction allows the program to branch based on the condition of any bit in the first 256 locations of memory. EA1 = (PC +1) Address Bus High Q 0; Address Bus Low ← (PC + 1) EA2 = PC + 3 + (PC + 2); PC ← EA2 if branch taken; otherwise, PC ← PC + 3. Power Considerations The average chip-junction temperature, TJ, in oC can be obtained from: TJ = TA + (PD•θ JA) Where: TA = Ambient Temperature, oC θ JA = Package Thermal Resistance Junction-to-Ambient, oC/W PD = PINT + PI/O PINT = ICC•VCC , Watts - Chip Internal Power PI/O = Power Dissipation on Input and Output Pins - User Determined For most applications PI/O < PINT and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K / (TJ + 273oC) Solving equations 1 and 2 for K gives: K = PD•(TA + 273oC) + θJA•PD2 (EQ. 3) (EQ. 2) (EQ. 1) Where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for a know TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA. VDD R2 TEST POINT C R1 EQUIVALENT TEST LOAD (SEE TABLE FOR VALUES OF R1 AND R2) PINS VDD = 4.5V PA0 - PA7, PD0 - PD4 MISO, MOSI, SCK R1 3.26kΩ 1.9kΩ R2 2.38kΩ 2.2kΩ C 50pF 200pF 47 HIP7030A2 TABLE 16. INSTRUCTION SET CONDITION CODES ADDRESSING MODES BIT INDEXED BIT TEST (NO INDEXED INDEXED SET/CLE AND MNEM INHERENT IMMEDIATE DIRECT EXTENDED RELATIVE OFFSET) (8 BITS) (16 BITS) AR BRANCH H I N Z C ADC ADD AND ASL ASR BCC BCLR BCS BEQ BHCC BHCS BHI BHS BIH BIL BIT BLO BLS BMC BMI BMS BNE BPL BRA BRN BRCLR BRSET BSET BSR CLC CLI CLR CMP COM CPX DEC X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Λ•ΛΛΛ Λ•ΛΛΛ • • • • • • • • • • • • • • • • • • • • • • • • • • • • •Λ•Λ •ΛΛΛ •ΛΛΛ • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •ΛΛ• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •Λ •Λ • • • • •0 • • •0• • • • • • •01• •ΛΛΛ •ΛΛ1 •ΛΛ •ΛΛ• 48 HIP7030A2 TABLE 16. INSTRUCTION SET (Continued) CONDITION CODES ADDRESSING MODES BIT INDEXED BIT TEST (NO INDEXED INDEXED SET/CLE AND MNEM INHERENT IMMEDIATE DIRECT EXTENDED RELATIVE OFFSET) (8 BITS) (16 BITS) AR BRANCH H I N Z C EOR INC JMP JSR LDA LDX LSL LSR MUL NEG NOP ORA ROL ROR RSP RTI RTS SBC SEC SEI STA STOP STX SUB SWI TAX TST TXA WAIT X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X • • • • • • • • •ΛΛ• •ΛΛ• • • • • • • • • •ΛΛ• •ΛΛ• •ΛΛΛ • 0ΛΛ • •0 0• • • • • • • •ΛΛΛ • • • • •ΛΛ• •ΛΛΛ •ΛΛΛ • • • • ????? • • • • • • • •ΛΛΛ • • •1 • • •1• • •ΛΛ• • • •0• • • •ΛΛ• •ΛΛΛ • • • • •1• • • • • • •ΛΛ• • • • • • • •0• Condition Code Symbols: H = Half Carry (from Bit 3) I = Interrupt Mask N = Negate (Sign Bit) Z = Zero 0 = Cleared Λ = Test and Set if True Cleared Otherwise • = Not Affected ? = Load CC Register From Stack C = Carry/Borrow 1 = Set Bit 7 6 5 4 3 2 1 0 49 TABLE 17. INSTRUCTION SET OPCODE MAP BIT MANIPULATION BTB HI LOW 0 3 BRANC H REL 2 5 3 READ/MODIFY/WRITE DIR 3 5 CONTROL IX 7 6 5 REGISTER/MEMORY IMM A 2 BSC 1 5 INH 4 3 INH 5 3 IX1 6 INH 8 9 INH 9 DIR B 3 EXT C 4 IX2 D 5 IX1 E 4 IX F 3 0 HI LOW 0 IX 3 BRSET0 BTB 2 5 BSET0 BSC 2 5 BRA REL 2 3 NEG DIR 1 NEGA INH 1 NEGX INH 2 NEG IX1 1 NEG IX 1 RTI INH 6 2 SUB IMM 2 2 SUB DIR 3 3 SUB EXT 3 4 SUB IX2 2 5 SUB IX1 1 4 SUB 1 3 BRCLR0 BTB 2 5 BCLR0 BSC 2 5 BRN REL 3 11 1 RTS INH 2 CMP IMM 2 2 CMP DIR 3 3 CMP EXT 3 4 CMP IX2 2 5 CMP IX1 1 4 CMP IX 3 1 2 3 BRSET1 BTB 2 5 BSET1 BSC 2 5 BHI REL 3 5 1 MUL INH 3 3 6 5 10 2 SBC IMM 2 2 SBC DIR 3 3 SBC EXT 3 4 SBC IX2 2 5 SBC IX1 1 4 SBC IX 3 2 3 3 BRCLR1 BTB 2 5 BCLR1 BSC 2 5 BLS REL 2 3 COM DIR 1 5 COMA INH 1 3 COMX INH 2 3 COM IX1 1 6 COM IX 1 SWI INH 2 CPX IMM 2 2 CPX DIR 3 3 CPX EXT 3 4 CPX IX2 2 5 CPX IX1 1 4 CPX IX 3 3 4 3 BRSET2 BTB 2 5 BSET2 BSC 2 5 BCC REL 2 3 LSR DIR 1 LSRA INH 1 LSRX INH 2 LSR IX1 1 5 LSR IX 2 AND IMM 2 2 AND DIR 3 3 AND EXT 3 4 AND IX2 2 5 AND IX1 1 4 AND IX 3 HIP7030A2 4 50 5 3 BRCLR2 BTB 2 5 BCLR2 BSC 2 5 BCS REL 3 5 2 BIT IMM 2 2 BIT DIR 3 3 BIT EXT 3 4 BIT IX2 2 5 BIT IX1 1 4 BIT IX 3 5 6 3 BRSET3 BTB 2 5 BSET3 BSC 2 5 BNE REL 2 3 ROR DIR 1 5 3 RORA INH 1 3 3 RORX INH 2 3 6 ROR IX1 1 6 5 ROR IX 5 2 2 LDA IMM 2 LDA DIR 3 4 LDA EXT 3 5 LDA IX2 2 6 LDA IX1 1 5 LDA IX 4 6 7 3 BRCLR3 BTB 2 5 BCLR3 BSC 2 5 BEQ REL 2 3 ASR DIR 1 5 ASRA INH 1 3 ASRX INH 2 3 ASR IX1 1 6 ASR IX 5 1 TAX INH 2 2 2 STA DIR 3 3 STA EXT 3 4 STA IX2 2 5 STA IX1 1 4 STA IX 3 7 8 3 BRSET4 BTB 2 5 BSET4 BSC 2 5 BHCC REL 2 3 LSL DIR 1 5 LSLA INH 1 3 LSLX INH 2 3 LSL IX1 1 6 LSL IX 5 1 CLC INH 2 2 EOR IMM 2 2 EOR DIR 3 3 EOR EXT 3 4 EOR IX2 2 5 EOR IX1 1 4 EOR IX 3 8 9 3 BRCLR4 BTB 2 5 BCLR4 BSC 2 5 BHCS REL 2 3 ROL DIR 1 5 ROLA INH 1 3 ROLX INH 2 3 ROL IX1 1 6 ROL IX 5 1 SEC INH 2 2 ADC IMM 2 2 ADC DIR 3 3 ADC EXT 3 4 ADC IX2 2 5 ADC IX1 1 4 ADC IX 3 9 A 3 BRSET5 BTB 2 5 BSET5 BSC 2 5 BPL REL 2 3 DEC DIR 1 DECA INH 1 DECX INH 2 DEC IX1 1 DEC IX 1 CLI INH 2 2 ORA IMM 2 2 ORA DIR 3 3 ORA EXT 3 4 ORA IX2 2 5 ORA IX1 1 4 ORA IX 3 A B 3 BRCLR5 BTB 2 5 BCLR5 BSC 2 5 BMI REL 3 5 3 3 6 5 1 SEI INH 2 2 ADD IMM 2 ADD DIR 2 3 ADD EXT 3 3 ADD IX2 2 4 ADD IX1 1 3 ADD IX 2 B C 3 BRSET6 BTB 2 BSET6 BSC 2 BMC REL 2 INC DIR 1 INCA INH 1 INCX INH 2 INC IX1 1 INC IX 1 RSP INH 2 JMP DIR 3 JMP EXT 3 JMP IX2 2 JMP IX1 1 JMP IX C TABLE 17. INSTRUCTION SET OPCODE MAP (Continued) BIT MANIPULATION BTB HI LOW D 3 BRANC H REL 2 5 3 READ/MODIFY/WRITE DIR 3 4 CONTROL IX 7 5 4 REGISTER/MEMORY IMM A 2 6 BSC 1 5 INH 4 3 INH 5 3 IX1 6 INH 8 INH 9 DIR B 5 EXT C 6 IX2 D 7 IX1 E 6 IX F 5 0 HI LOW D IX 3 BRCLR6 BTB 2 5 BCLR6 BSC 2 5 BMS REL 2 3 TST DIR 1 TSTA INH 1 TSTX INH 2 TST IX1 1 TST IX 2 1 NOP INH 2 BSR REL 2 2 JSR DIR 3 3 JSR EXT 3 4 JSR IX2 2 5 JSR IX1 1 4 JSR E 3 BRSET7 BTB 2 5 BSET7 BSC 2 5 BIL REL 3 5 3 3 6 5 1 STOP INH 2 2 2 LDX IMM 2 LDX DIR 3 4 LDX EXT 5 3 LDX IX2 2 6 LDX IX1 1 5 LDX IX 4 E F 3 BRCLR7 BTB 2 BCLR7 BSC 2 BIH REL 2 CLR DIR 1 CLRA INH 1 CLRX INH 2 CLR IX1 1 CLR IX 1 WAIT INH 1 TXA INH 2 STX DIR 3 STX EXT 3 STX IX2 2 STX IX1 1 STX IX F INH = Inherent IMM = Immediate DIR = Direct EXT = Extended REL = Relative BSC = Bit Set/Clear BTB = Bit Test and Branch BTB = Bit Test and Branch IX = Indexed, No Offset IX1 = Indexed, 8-Bit Offset IX2 = Indexed, 16-Bit Offset LSB of Opcode HI LOW 0 3 0 MSB of Opcode HIP7030A2 5 Number of Cycles BRSET0 Instruction Mnemonic BTB Number of Bytes/Addressing Mode 51 HIP7030A2 $0000 I/O 8 PA7 I/O 9 PA6 I/O 10 PA5 I/O 11 PA4 I/O 12 PA3 I/O 13 PA2 I/O 14 PA1 I/O 15 PA0 PORT A Pin Numbers Pin Name $0001 $0002 $0003 CMP3 18 V3>VREF UNUSED UNUSED CMP2 19 V2>VREF 0 - I/O 17 PD4/VREF I/O 18 PD3/V2 I/O 19 PD2/V1 I/O 20 PD1 I/O 21 PD0 PORT D Pin Numbers Pin Name $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F I/O I/O I/O I/O I/O I/O I/O I/O DDRA UNUSED UNUSED 0 0 0 0 0 CMPE I/O 0 UNUSED SPIE SPIF SPE WCOL 0 MSTR MODF CPOL 0 CPHA 0 SPR1 0 SPR0 0 SPCR SPSR SPDR I/O 0 I/O 0 I/O STE1 I/O STE0 DDRD SFRD SPI DATA REGISTER UNUSED UNUSED TXIE TX FSOF ICIE ICF Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 UNUSED $55/$AA 0 0 0 0 0 0 1 WDF BRK S2 OCIE OCF NEW S1 TOIE TOF NDEL NOIZ S0 0 0 OVR LEV 0 0 4X TALK R2 0 0 PRE1 NECHO R1 IEDG 0 PRE0 0 R0 OLVL 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 SEDCR SEDSR SEDDR TCR TSR CAPHI CAPLO CMPHI CMPLO CNTHI CNTLO ALTHI ALTLO WRR WSR RESERVED RESERVED I/O, CONTROL, STATUS, AND DATA REGISTER DEFINITIONS Ordering Information Sheet 52 HIP7030A2 A. Package Type (select one): 28 Ld Dual-In-Line Plastic (E) 28 Ld SO (M) B. Choose from the following microcomputer option. A manufacturing mask will be generated from this information. Refer to data sheet or data book instructions for submitting data for ROM patterns. OSCB - Buffered Oscillator Output (select one) Enabled Disabled C. Customer Company ____________________________________________________________________________ Address _____________________________________________________________________________________ City _________________________________________________________________________________________ Phone ( ____ ) ___________________________________________ Extension ________________________ Contact Person _______________________________________________________________________________ Customer Part Number _________________________________________________________________________ D. Pattern Media (S-Record Formatted File Should Be Used - Unspecified locations are filled with 0’s) Floppy Disk: 31/2” 51/4” MODEM Upload: S-Record Filename _________________ Medium if other than above † _____________________________________________________________________ Signature _________________________________________________ † The HIP7030A2 requires 8K of data Title ______________________________ Date _____________________________ 53 HIP7030A2 ROM Ordering Instructions The HIP7030A2 family of microcontrollers contains mask programmed ROMs. The contents of these ROMs are personalized to meet a customer’s code requirements during manufacturing of the ICs. The code is programmed via photomasking techniques. Semiconductor manufacturing is a batch process, and all microcontrollers manufactured in a given lot (a batch) will contain identical ROM code. Intersil generates a customer’s ROM mask from an ASCII representation of the desired ROM contents together with other specific information. The preceding page contains a sheet which can be used to provide the required information when ordering a masked ROM microcontroller. Data Format Options The ROM data can be submitted in various formats. The following list summarizes the principal formats which Intersil will accept. The list is in order of preference, with S-Record formatted data files being the preferred format. • • • • • S-Record Formatted Hex Data File via modem upload S-Record Formatted Hex Data File via e-mail S-Record Formatted Hex Data File on floppy disk 6805 Assembly Language Source File on floppy disk Contents of a 27XX type EPROM/EEPROM Procedure for Submitting Data When submitting data via a physical medium such as a floppy disk or EPROM, the “Ordering Information Sheet” on the preceding page must be completed and submitted with the data. When utilizing the Intersil Customer Pattern Retrieval System (modem upload) the customer will be prompted for the same information as that specified on the “Ordering Information Sheet”. If the data is submitted via e-mail, the message should include the same information as that specified on the “Ordering Information Sheet”. Intersil Customer Pattern Retrieval System To access the Intersil Customer Pattern Retrieval System, you must first obtain an account ID and password from your Intersil sales representative. The system is accessed by dialing 1-908-685-6541. It is presently set to run with baud rates up to 2400 baud, with 8 data bits, 1 stop bit, and no parity bit. The data transfer is done using text mode Kermit transfers. Check the Intersil Corporate Internet Site, http://www.intersil.com, for the latest information on the Intersil Customer Pattern Retrieval System. Regardless of the medium used to transfer the data, contents of all of the User ROM regions of the memory map of the particular microcontroller should be specified. This includes any Page 0 User ROM and User Reset/Interrupt Vectors. Data should not be specified for the Self Check ROM space of a device. All unused locations should either not be specified (S-Record and source files) or specified as $00 (EPROM/EEPROM). Any unspecified locations will be filled with $00 by Intersil. 54 HIP7030A2 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M28.3 (JEDEC MS-013-AE ISSUE C) 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 L MILLIMETERS MIN 2.35 0.10 0.33 0.23 17.70 7.40 MAX 2.65 0.30 0.51 0.32 18.10 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0926 0.0040 0.013 0.0091 0.6969 0.2914 MAX 0.1043 0.0118 0.0200 0.0125 0.7125 0.2992 B C D E α A1 0.10(0.004) C e H h L N 0.05 BSC 0.394 0.01 0.016 28 0o 8o 0.419 0.029 0.050 1.27 BSC 10.00 0.25 0.40 28 0o 10.65 0.75 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 55 HIP7030A2 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E28.6 (JEDEC MS-011-AB ISSUE B) 28 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 3.18 0.356 0.77 0.204 35.1 0.13 15.24 12.32 MAX 6.35 4.95 0.558 1.77 0.381 39.7 15.87 14.73 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.125 0.014 0.030 0.008 1.380 0.005 0.600 0.485 MAX 0.250 0.195 0.022 0.070 0.015 1.565 0.625 0.580 A E A2 L A C L -AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A1 A2 -C- B B1 C D D1 E E1 e eA eB L N eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 0.100 BSC 0.600 BSC 0.115 28 0.700 0.200 2.54 BSC 15.24 BSC 2.93 28 17.78 5.08 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 56