HIP9011

® HIP9011 Data Sheet January 6, 2006 FN4367.2 Engine Knock Signal Processor The HIP9011 is used to provide a method of detecting premature detonation often referred to as “Knock or Ping” in internal combustion engines. The IC is shown in the Simplified Block Diagram. The chip can select between one of two sensors, if needed for accurate monitoring or for “V” type engines. Internal control via the SPI bus is fast enough to switch sensors between each firing cycle. A programmable bandpass filter processes the signal from either of the sensor inputs. The bandpass filter can be selected to optimize the extraction the engine knock or ping signals from the engine background noise. Further single processing is obtained by full wave rectification of the filtered signal and applying it to an integrator whose output voltage level is proportional to the knock signal amplitude. The chip is under microprocessor control via a SPI interface bus. Features • Two Sensor Inputs • Microprocessor Programmable • Accurate and Stable Filter Elements • Digitally Programmable Gain • Digitally Programmable Time Constants • Digitally Programmable Filter Characteristics • On-Chip Crystal Oscillator • Programmable Frequency Divider • External Clock Frequencies up to 24MHz - 4, 5, 6, 8, 10, 12, 16, 20, and 24MHz • Operating Temperature Range -40oC to 125oC • Pb-Free Plus Anneal Available (RoHS Compliant) Ordering Information PART NUMBER HIP9011AB PART MARKING HIP9011AB TEMP. RANGE (oC) -40 to 125 -40 to 125 PACKAGE 20 Ld SOIC 20 Ld SOIC (Pb-free) PKG. DWG. # M20.3 M20.3 Applications • Engine Knock Detector Processor • Analog Signal Processing Where Controllable Filter Characteristics are Required HIP9011ABZ HIP9011ABZ (See Note) Add “T” suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Simplified Block Diagram CH0FB CH0IN CH0NI CH1FB CH1IN CH1NI + 3RD ORDER ANTIALIASING FILTER CHANNEL SELECT SWITCHES + PROGRAMMABLE GAIN STAGE 2- 0.111 64 STEPS PROGRAMMABLE BANDPASS FILTER 1-20kHz 64 STEPS ACTIVE FULL WAVE RECTIFIER PROGRAMMABLE INTEGRATOR 40 - 600µs 32 STEPS OUTPUT DRIVER INTOUT AND SAMPLE AND HOLD OSCIN CLOCK OSCOUT PROGRAMMABLE DIVIDER TO SWITCHED CAPACITOR NETWORKS POWER SUPPLY AND BIAS CIRCUITS VMID VDD GND REGISTERS AND STATE MACHINE TEST SPI INTERFACE SCK CS SI SO INT/HOLD 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1999, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HIP9011 Pinout HIP9011 (SOIC) TOP VIEW VDD GND VMID INTOUT NC NC INT/HOLD CS OSCIN 1 2 3 4 5 6 7 8 9 20 CH0NI 19 CH0IN 18 CH0FB 17 CH1FB 16 CH1IN 15 CH1NI 14 TEST 13 SCK 12 SI 11 SO OSCOUT 10 Pin Descriptions PIN NUMBER 1 2 3 4 5, 6 7 8 9 10 11 DESIGNATION VDD GND VMID INTOUT NC INT/HOLD CS OSCIN OSCOUT SO Five volt power input. This pin is tied to ground. This pin is connected to the internal mid-supply generator and is brought out for bypassing by a 0.022µF capacitor. Buffered output of the integrator. Output signal is held by an internal Sample and Hold circuit when INT/HOLD is low. These pins are not internally connected. Do Not Use. Selects whether the chip is in the Integrate Mode (Input High) or in the Hold Mode (Input Low). This pin has an internal pull down. A low input on this pin enables the chip to communicate over the SPI bus. This pin has an internal pull-up. Input to inverter used for the oscillator circuit. A 4MHz crystal or ceramic resonator is connected between this pin and pin 10. To bias the inverter, a 1.0MΩ to 10MΩ resistor is usually connected between this pin and pin 10. Output of the inverter used for the oscillator. See pin 9 above. Output of the chip SPI data bus. This is a three-state output that is controlled via the SPI bus. The output is placed in the high impedance state by setting CS high when the chip is not selected. This high impedance state can also be programmed by setting the LSB of the prescaler word to 1. This will take precedence over CS. A 0 enables the active state. The Diagnostic Mode overrides these conditions. Input of the chip SPI data bus. Data length is eight bits. This pin has an internal pull-up. Input from the SPI clock. Normally low, the data is transferred to the chip internal circuitry on the falling clock edge. This pin has an internal pull up. A low on this pin places the chip in the diagnostic mode. For normal operation this pin is tied high or left open. This pin has an internal pull up. Non-inverting input of Channel one. Inverting input to channel one amplifier. A resistor is tied from this summing input to the transducer. A second resistor is tied between this pin and pin 17, CH1FB to establish the gain of the amplifier. Output of the channel one amplifier. This pin is used to apply feedback. Output of the channel zero amplifier. This pin is used to apply feedback. Inverting input to channel zero amplifier. Remainder same as channel one amplifier except feedback is applied from pin 18. Non-inverting input of Channel 0. Remainder the same as pin 16, except feedback is applied from terminal 18. DESCRIPTION 12 13 14 15 16 17 18 19 20 SI SCK TEST CH1NI CH1IN CH1FB CH0FB CH0IN CH0NI 2 FN4367.2 January 6, 2006 HIP9011 Absolute Maximum Ratings DC Logic Supply, VDD . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Max Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Maximum Power Dissipation, PD For TA = -40oC to 70oC . . . . . . . . . . . . . . . . . . . . . . . 400mW Max For TA = 70oC to 125oC, Derate Linearly at . . . . . . . . . . 6mW/oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range, TSTG . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC At a Distance 1/16 ±1/32 inch, (1.59 ±0.79mm) from Case for 10s Max. (SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER DC ELECTRICAL SPECIFICATIONS Quiescent Supply Current Midpoint Voltage, Pin 3 Midpoint Voltage, Pin 3 Low Input Voltage, Pins INT/HOLD, CS, SI, SCK High Input Voltage, Pins INT/HOLD, CS, SI, SCK Hysteresis voltage, Pins INT/HOLD, CS, SI, SCK Internal Pull-Up Current Internal Pull-Down Current Low Level Output, Pin SO High Level Output, Pin SO Three-State Leakage Pin SO Low Level Output, Pin 10, OSCOUT High Level Output, Pin 10, OSCOUT SPI BUS INTERFACE AC Parametrics CS Falling to SCLK Rising CS Rising to SCLK Falling SCLK Low SCLK High SCLK Falling to CS Rising Data High Setup Time Data Low Setup Time Data High Hold Time Data Low Hold Time Min Time Between 2 Programmed Words CS Rising to INT/Hold Rising tCCH tCCL tPWL tPWH tSCCH tSUH tSUL tHH tHL tCSH tCIH 10 80 60 60 60 20 20 10 10 200 8 ns ns ns ns ns ns ns ns ns ns µs IDD VMID VMID VIL VIH VHYST I Source CS, SI, VDD = 5.0V, Measured at GND SCK, TEST I Sink, INT/HOLD VOL VOH IL VOL VOH VDD = 5.0V, Measured at VDD ISOURCE = 1.6mA, VDD = 5.0V ISINK = 200µA, VDD = 5.0V Measured at GND; VDD = 5.0V ISOURCE = 500µA; VDD = 5.0V ISINK = -500µA; VDD = 5.0V VDD = 5.25V, GND = 0V VDD = 5.0V, IL = 2mA Source VDD = 5.0V, IL = 0mA 2.3 2.4 70 0.85 0.01 4.8 4.4 5.0 2.45 2.5 50 -50 4.9 8.0 2.55 2.6 30 0.30 5.0 ±10 1.5 mA V V % of VDD % of VDD V µA µA V V µA V V VDD = 5V ±5%, GND = 0V, Clock Frequency 4MHz ±0.1%, TA = -40oC to 125oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 3 FN4367.2 January 6, 2006 HIP9011 Electrical Specifications PARAMETER INPUT AMPLIFIERS CH0 and CH1 High Output Voltage CH0 and CH1 Low Output Voltage Voltage Gain ANTIALIASING FILTER Response 1kHz to 20kHz, Referenced to 1kHz Attenuation at 180kHz, Referenced to 1kHz PROGRAMMABLE FILTERS Peak to Peak Voltage Output Filters Q (Note 2) PROGRAMMABLE GAIN AMPLIFIERS Percent Amplifier Gain Deviation INTEGRATOR Integrator Reset Voltage VRESET Pin 4 Voltage at Start of Integration Cycle; VDD = 5.0V Hold Mode, Pin 7 = 0V, VDD = 5.0V Pin 4 set to 20% to 80% of VDD 75 125 175 mV %G Run Mode ±1 % VOUT Q Run Mode Run Mode 3.5 4.0 2.5 VP-P Q BW ATTEN Test Mode Test Mode -10 -0.5 -15 dB dB VOUTHI VOUTLO ACL ISINK = 100µA, VDD = 5.0V ISOURCE = 100µA; VDD = 5.0V Input R = 47.5K, Feedback R = 475kΩ 4.7 +18 4.9 15 +20 200 +21 V mV dB VDD = 5V ±5%, GND = 0V, Clock Frequency 4MHz ±0.1%, TA = -40oC to 125oC, Unless Otherwise Specified (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Integrator Droop after 500µs VDROOP - ±3 ±50 mV DIFFERENTIAL CONVERTER Differential to Single Ended Converter Offset Voltage Change In Converter Output SYSTEM GAIN DEVIATION Gain Deviation from “Ideal Equation” Correlation Factor + 5.0% (Note 3) VOUT VRESET Run Mode, maximum signal output from Input Amplifier