HM-6551

® HM-6551/883 Data Sheet July 2003 FN2988.2 256 x 4 CMOS RAM The HM-6551/883 is a 256 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation. On chip latches are provided for address and data outputs allowing efficient interfacing with microprocessor systems. The data output buffers can be forced to a high impedance state for use in expanded memory arrays. The HM-6551/883 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature. Features • This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. • Low Power Standby . . . . . . . . . . . . . . . . . . . . . 50µW Max • Low Power Operation. . . . . . . . . . . . . . . .20mW/MHz Max • Fast Access Time. . . . . . . . . . . . . . . . . . . . . . . 220ns Max • Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min • TTL Compatible Input/Output • High Output Drive - 1 TTL Load • Internal Latched Chip Select • High Noise Immunity PKG. DWG. # Ordering Information PACKAGE CERDIP TEMP. RANGE -55°C to +125°C 220ns 300ns • On-Chip Address Register • Latched Outputs • Three-State Output HM1-6551B/883 HM1-6551/883 F22.4 Pin Descriptions PIN A E W S D Q Address Input Chip Enable Write Enable Chip Select Data Input Data Output DESCRIPTION Pinout HM-6551/883 (CERDIP) TOP VIEW A3 1 A2 2 A1 3 A0 4 A5 5 A6 6 A7 7 GND 8 D0 9 Q0 10 D1 11 22 VCC 21 A4 20 W 19 S1 18 E 17 S2 16 Q3 15 D3 14 Q2 13 D2 12 Q1 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HM-6551/883 Functional Diagram A LATCHED ADDRESS REGISTER 5 A 5 8 D0 D1 D2 D3 A A A A A GATED COLUMN DECODER AND DATA I/O D D D 3 A 3 L DATA OUTPUT Q LATCHES Q Q A Q2 A Q3 A 8 8 8 D Q A Q0 Q1 GATED ROW DECODER 32 32 x 32 MATRIX A0 A1 A5 A6 A7 E W S2 S1 L D SELECT Q LATCH LATCHED ADDRESS REGISTER A2 A3 A4 NOTES: 1. Select Latch: L Low → Q = D and Q latches on rising edge of L. 2. Address Latches And Gated Decoders: Latch on falling edge of E and gate on falling edge of E. 3. All lines positive logic-active high. 4. Three-State Buffers: A high → output active. 5. Data Latches: L High → Q = D and Q latches on falling edge of L. 2 HM-6551/883 Absolute Maximum Ratings Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V Input, Output or I/O Voltage . . . . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Information Thermal Resistance θJA θJC CERDIP Package . . . . . . . . . . . . . . . . 60°C/W 15°C/W Maximum Storage Temperature Range . . . . . . . . . . . .-65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +175°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . +300°C Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . . . -55°C to +125°C Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V nput High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . .VCC -2.0V to VCC Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max. Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1930 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. TABLE 1. HM-6551/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested (NOTE 1) CONDITIONS VCC = 4.5V IOL = 1.6mA VCC = 4.5V IOH = -0.4mA VCC = 5.5V, VI = GND or VCC VCC = 5.5 V, VO = GND or VCC VCC = 2.0V, E = VCC IO = 0mA, VI = VCC or GND VCC = 5.5V, (Note 2) E = 1MHz, IO = 0mA VI = VCC or GND VCC = 5.5V, IO = 0mA VI = VCC or GND GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 LIMITS TEMPERATURE -55°C ≤ TA ≤ +125°C -55°C ≤ TA ≤ +125°C -55°C ≤ TA ≤ +125°C -55°C ≤ TA ≤ +125°C -55°C ≤ TA ≤ +125°C MIN 2.4 -1.0 -1.0 MAX 0.4 +1.0 +1.0 10 UNITS V V µA µA µA PARAMETER Output Low Voltage Output High Voltage Input Leakage Current Output Leakage Current Data Retention Supply Current Operating Supply Current Standby Supply Current NOTES: SYMBOL VOL VOH II IOZ ICCDR ICCOP 1, 2, 3 -55°C ≤ TA ≤ +125°C - 4 mA ICCSB 1, 2, 3 -55°C ≤ TA ≤ +125°C - 10 µA 1. All voltages referenced to device GND. 2. Typical derating 1.5mA/MHz increase in ICCOP. 3 HM-6551/883 TABLE 2. HM-6551/883 A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS (NOTES 1, 2) CONDITIONS VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V, Note 3 VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V GROUP A SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 HM-6551B/883 TEMPERATURE -55°C ≤ TA ≤ +125°C -55°C ≤ TA ≤ +125°C -55°C ≤ TA ≤ +125°C -55°C ≤ TA ≤ +125°C -55°C ≤ TA ≤ +125°C -55°C ≤ TA ≤ +125°C -55°C ≤ TA ≤ +125°C -55°C ≤ TA ≤ +125°C -55°C ≤ TA ≤ +125°C -55°C ≤ TA ≤ +125°C -55°C ≤ TA ≤ +125°C -55°C ≤ TA ≤ +125°C -55°C ≤ TA ≤ +125°C -55°C ≤ TA ≤ +125°C -55°C ≤ TA ≤ +125°C -55°C ≤ TA ≤ +125°C -55°C ≤ TA ≤ +125°C -55°C ≤ TA ≤ +125°C -55°C ≤ TA ≤ +125°C MIN 5 220 100 0 0 40 40 100 0 120 120 120 120 120 320 MAX 220 220 130 130 HM-6551/883 MIN 5 300 100 0 0 50 50 150 0 180 180 180 180 180 400 MAX 300 300 150 150 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns PARAMETER Chip Enable Access Time Address Access Time Chip Select 1 Output Enable Time Write Enable Output Disable Time Chip Select 1 Output Disable Time Chip Enable Pulse Negative Width Chip Enable Pulse Positive Width Address Setup Time Chip Select 2 Setup Time Address Hold Time Chip Select 2 Hold Time Data Setup Time Data Hold Time Chip Select 1 Write Pulse Setup Time Chip Enable Write Pulse Setup Time Chip Select 1 Write Pulse Hold Time Chip Enable Write Pulse Hold Time Write Enable Pulse Width Read or Write Cycle Time NOTES: (1) (2) (3) (4) (5) (6) (7) (8) (9) SYMBOL TELQV TAVQV TS1LQX TWLQZ TS1HQZ TELEH TEHEL TAVEL TS2LEL (10) TELAX (11) TELS2X (12) TDVWH (13) TWHDX (14) TWLS1H (15) TWLEH (16) TS1LWH (17) TELWH (18) TWLWH (19) TELEL 1. All voltages referenced to device GND. 2. Input pulse levels: 0.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: IOL = 1.6mA, IOH = -0.4mA, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 3. TAVQV = TELQV + TAVEL. 4 HM-6551/883 TABLE 3. HM-6551B/883 AND HM-6551/883 ELECTRICAL PERFORMANCE SPECIFICATIONS LIMITS PARAMETER Input Capacitance SYMBOL CI CONDITIONS VCC = Open, f = 1MHz, All Measurements Referenced to Device Ground VCC = Open, f = 1MHz, All Measurements Referenced to Device Ground NOTE 1 TEMPERATURE TA = +25°C MIN MAX 10 UNITS pF Output Capacitance CO 1 TA = +25°C - 12 pF NOTE: 1. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process and/or design changes. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C & D METHOD 100%/5004 100%/5004 100%/5004 100%/5004 Samples/5005 Samples/5005 SUBGROUPS 1, 7, 9 1 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9 5 HM-6551/883 Timing Waveforms (8) TAVEL A (10) TELAX VALID (19) TELEL (7) TEHEL E (9) TS2LEL S2 TELS2X (11) (9) TS2LEL TELEH (6) TEHEL (7) (8) TAVEL NEXT D TELQV (1) TAVQV (2) Q (3) TS1LQX S1 HIGH VALID OUTPUT TS1HQZ (5) W TIME REFERENCE -1 0 1 2 3 4 5 FIGURE 1. READ CYCLE TRUTH TABLE TIME REFERENCE -1 0 1 2 3 4 5 H L L INPUTS E H S1 H X L L L H X S2 X L X X X X L W X H H H H X H A X V X X X X V D X X X X X X X OUTPUTS Q Z Z X V V Z Z FUNCTION Memory Disabled Addresses and S2 are Latched, Cycle Begins Output Enabled but Undefined Data Output Valid Outputs Latched, Valid Data, S2 Unlatches Prepare for Next Cycle (Same as -1) Cycle Ends, Next Cycle Begins (Same as 0) The HM-6551/883 Read Cycle is initiated by the falling edge of E. This signal latches the input address word and S2 into on-chip registers providing the minimum setup and hold times are met. After the required hold time, these inputs may change state without affecting device operation. S2 acts as a high order address and simplifies decoding. For the output to be read, E, S1 must be low and W must be high. S2 must have been latched low on the falling edge of E. The output data will be valid at access time (TELQV). The HM-6551/883 has output data latches that are controlled by E. On the rising edge of E the present data is latched and remains in that state until E falls. Also on the rising edge of E, S2 unlatches and controls the outputs along with S1. Either or both S1 or S2 may be used to force the output buffers into a high impedance state. 6 HM-6551/883 Timing Waveforms (Continued) (8) TAVEL A (10) TELAX VALID TELEL (19) TEHEL (7) E (9) TS2LEL S2 TELS2X (11) (9) TS2LEL TELEH (6) TEHEL (7) (8) TAVEL NEXT D DATA VALID TWLEH (15) TELWH (17) TWHDX (13) W TDVWH (12) TWLWH (18) TS1LWH (16) TWLS1H (14) S1 TIME REFERENCE -1 0 1 2 3 4 5 FIGURE 2. WRITE CYCLE TRUTH TABLE TIME REFERENCE -1 0 1 2 3 4 5 H L L INPUTS E H S1 H X L L X H X S2 X L X X X X L H X X W X X A X V X X X X V D X X X V X X X OUTPUTS Q Z Z Z Z Z Z Z FUNCTION Memory Disabled Cycle Begins, Addresses and S2 are Latched Write Period Begins Data In is Written Write is Completed Prepare for Next Cycle (Same as -1) Cycle Ends, Next Cycle Begins (Same as 0) In the Write Cycle the falling edge of E latches the addresses and S2 into on-chip registers. S2 must be latched in the low state to enable the device. The write portion of the cycle is defined as E, W, S1 being low and S2 being latched simultaneously. The W line may go low at any time during the cycle providing that the write pulse setup times (TWLEH and TWLS1H) are met. The write portion of the cycle is terminated on the first rising edge of either E, W, or S1. If a series of consecutive write cycles are to be executed, the W line may be held low until all desired locations have been written. If this method is used, data setup and hold times must be referenced to the first rising edge of E or S1. By positioning the write pulse at different times within the E and S1 low time 7 (TELEH), various types of write cycles may be performed. If the S1 low time (TS1LS1H) is greater than the W pulse, plus an output enable time (TS1LQX), a combination read-write cycle is executed. Data may be modified an indefinite number of times during any write cycle (TELEH). The HM-6551/883 may be used on a common I/O bus structure by tying the input and output pins together. The multiplexing is accomplished internally by the W line. In the write cycle, when W goes low, the output buffers are forced to a high impedance state. One output disable time delay (TWLQZ) must be allowed before applying input data to the bus. HM-6551/883 Test Load Circuit DUT (NOTE 1) CL IOH + - 1.5V IOL EQUIVALENT CIRCUIT NOTE: 1. Test head capacitance includes stray and jig capacitance. Burn-In Circuit HM-6551/883 CERDIP VCC C1 F7 F6 F5 F4 F9 F10 F11 1 2 A3 A2 VCC 22 A4 21 W 20 S1 19 E 18 S2 17 Q3 16 D3 15 Q2 14 D2 13 Q1 12 F8 F2 F0 F0 F1 F3 F3 F3 F3 F3 3 A1 4 5 6 7 8 A0 A5 A6 A7 GND D0 F3 F3 F3 9 10 Q0 11 D1 NOTES: All resistors 47kΩ ±5%. F0 = 100kHz ±10%. F1 = F0 ÷ 2, F2 = F1 ÷ 2, F3 = F2 ÷ 2 . . . F12 = F11 ÷ 2. VCC = 5.5V ±0.5V. VIH = 4.5V ±10%. VIL = -0.2V to +0.4V. C1 = 0.01µF Min. 8 HM-6551/883 Die Characteristics DIE DIMENSIONS: 132 x 160 x 19 ±1mils METALLIZATION: Type: Si - Al Thickness: 11kÅ ±2kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ±1kÅ WORST CASE CURRENT DENSITY: 1.337 x 105 A/cm2 LEAD TEMPERATURE (10s soldering): ≤300oC Metallization Mask Layout HM-6551/883 S1 W E S2 Q3 D3 Q2 D2 Q1 D1 A4 VCC A3 A2 Q0 A1 A0 A5 A6 A7 GND D0 NOTE: Pin numbers correspond to DIP Package only. 9 HM-6551/883 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A - B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH F22.4 MIL-STD-1835 GDIP1-T22 (D-7, CONFIGURATION A) 22 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.350 MAX 0.225 0.026 0.023 0.065 0.045 0.018 0.015 1.111 0.410 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 8.89 MAX 5.72 0.66 0.58 1.65 1.14 0.46 0.38 28.22 10.41 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 6/13/95 α eA c1 D E e eA eA/2 L Q S1 e DS eA/2 c 0.100 BSC 0.400 BSC 0.200 BSC 0.125 0.015 0.005 90o 22 0.200 0.070 105o 0.015 0.030 0.010 0.0015 2.54 BSC 10.16 BSC 5.08 BSC 3.18 0.38 0.13 90o 22 5.08 1.78 105o 0.38 0.76 0.25 0.038 aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. α aaa bbb ccc M N All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10