HMP8154EVAL1

® HMP8154, HMP8156A Data Sheet November 4, 2005 FN4343.4 NTSC/PAL Encoders The HMP8154 and HMP8156A NTSC and PAL encoders are designed for use in systems requiring the generation of highquality NTSC and PAL video from digital image data. YCbCr or RGB digital video data drive the P0-P23 inputs. Overlay inputs are processed and the data is 2x upsampled. The Y data is optionally lowpass filtered to 6MHz and drives the Y analog output. Cb and Cr are each lowpass filtered to 1.3MHz, quadrature modulated, and summed. The result drives the C analog output. The digital Y and C data are also added together and drive the two composite analog outputs. The YCbCr data may also be converted to RGB data to drive the DACs, allowing support for analog component RGB and the European SCART connector. The DACs can drive doubly-terminated (37.5Ω) lines, and run at a 2x oversampling rate to simplify the analog output filter requirements. Any unused DACs may be powered down to reduce power consumption. Features • (M) NTSC and (B, D, G, H, I, M, N, CN) PAL Operation • ITU-R BT.601 and Square Pixel Operation • Digital Input Formats - 4:2:2 YCbCr - 8-Bit or 16-Bit - 4:4:4 RGB - 16-Bit (5, 6, 5) or 24-Bit (8, 8, 8) - Linear or Gamma-Corrected - 8-Bit BT.656 • Overlay Mixing - 7 Colors - Internal, External, or Hard Mixing Control • Analog Output Formats - Y/C + Two Composite - RGB + Composite (SCART) • Flexible Video Timing Control - Timing Master or Slave - Programmable Input Sync Timing - Selectable Polarity on Each Control Signal - Programmable Blank Output Timing - Field Output • Closed Caption Encoding for NTSC and PAL • 2x Upscaling of SIF Video Ordering Information PART MARKING HMP8154 CN HMP8156 ACN HMP8156 ACNZ TEMP. RANGE (°C) 0 to 70 PKG. DWG. # PART NUMBER HMP8154CN PACKAGE 64 Ld PQFP Q64.14x14 HMP8156ACN 0 to 70 64 Ld PQFP Q64.14x14 • Three Line Vertical Flicker Filter (HMP8154 only) • Four 2x Oversampling, 10-Bit DACs with Power Down • I2C Interface • Verilog Models Available • Pb-Free Plus Anneal Available (RoHS Compliant) HMP8156ACNZ (See Note) HMP8154EVAL1 HMP8156EVAL1 HMP8156EVAL2 0 to 70 64 Ld PQFP Q64.14x14 (Pb-free) Daughter/Stand-Alone Card Evaluation Platform* Frame Grabber Evaluation Platform* *Described in the Applications Section NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Applications • Multimedia PCs • Video Conferencing • Video Editing • Related Products - NTSC/PAL Encoders: HMP8170-HMP8173 - HMP8190/91 - NTSC/PAL Decoders: HMP8112A, HMP8115, HMP8116, HMP8130/31 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1998, 2002, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Functional Block Diagram P0 - P23 OVERLAY PROCESSING OPTIONAL GAMMA CORRECTION COLOR SPACE CONVERSION Y/Cb/Cr 4:4:4 (2:2:2 SIF) 2 2X UPSCALING (SIF MODE) 4:2:2 TO 4:4:4 SAMPLE CONVERSION FLICKER FILTER (HMP8154 ONLY) CLOSED CAPTIONING PROCESSING INTERNAL 1.225V REFERENCE HMP8154, HMP8156A VREF (OPTIONAL) SA Y SCL HOST INTERFACE 2X UPSAMPLE 4:4:4 TO 8:8:8 Cb/Cr LP FILTER FS ADJUST ∑ DAC Y/G SDA RESET LP FILTER ∑ DAC NTSC/ PAL 1 HSYNC VSYNC VIDEO TIMING CONTROL CHROMA MODULATION DAC NTSC/ PAL 2/ R BLANK CLK DAC FIELD C/B CLK2 4343.4 November 4, 2005 HMP8154, HMP8156A Functional Operation The HMP8154 and HMP8156A are fully integrated digital encoders. Either accepts digital video input data and generates four analog video output signals. The input data format is selectable and includes YCbCr, RGB, and overlay data. The outputs are configurable to be either two composite video signals and Y/C (S-Video) or one composite and component RGB video. The HMP8154/HMP8156A accepts pixel data in one of several formats and transforms it into 4:4:4 sampled luminance and chrominance (YCbCr) data. If enabled, the encoder also mixes overlay data with the input data. The encoder then interpolates the YCbCr data to twice the pixel rate and low pass filters it to match the bandwidth of the video output format. If enabled, the encoder also adds Closed Captioning information to the Y data. At the same time, the encoder modulates the chrominance data with a digitally synthesized subcarrier. Finally, the encoder outputs luminance, chrominance, and their sum as analog signals using 10-bit D/A converters. The HMP8154/HMP8156A provides operating modes to support all versions of the NTSC and PAL standards and accepts full and SIF size input data with rectangular (ITU-R BT.601) and square pixel aspect ratios. It operates from a single clock at twice the pixel clock rate determined by the operating mode. The HMP8154/HMP8156A’s video timing control is flexible. It may operate as the master generating the system’s video timing control signals or it may accept external timing controls. The polarity of the timing controls and the number of active pixels and lines are programmable. The HMP8154 provides optional vertical flicker reduction. When enabled, the encoder passes the pixel data after overlay processing through a three line flicker filter. larger than the analog output limit. The composite signal will be clipped but the S-video outputs (Y and C) will not be. The color difference signals are time multiplexed into one 8-bit bus beginning with a Cb sample. The Y and CbCr busses may be input in parallel (16-bit mode) or may be time multiplexed and input as a single bus (8-bit mode). The single bus may also contain SAV and EAV video timing reference codes (BT.656 mode). RGB Data The HMP8154/HMP8156A accepts 4:4:4 sampled RGB component video input data. The color signals may be (8,8,8) for 24-bit mode or (5,6,5) for 16-bit mode. In 24-bit mode, they are scaled 0 to 255, black to white. In 16-bit mode, the encoder left shifts the input so that it has the same scale as 24-bit input. The RGB data may be linear or gamma corrected; if enabled, the encoder will gamma correct the input data. Overlay Data The HMP8154/HMP8156A accepts 5 bits of pixel overlay input data and combines it with the input pixel data. The data specifies an overlay color and the fractions of the new and original colors to be summed. Blue Screen Generation In blue screen mode, the HMP8154/HMP8156A ignores the pixel input data and generates a solid, blue screen. The overlay inputs may be used to place information over the blue screen. Input Processing Color Space Conversion For linear RGB input formats, the encoder applies gammacorrection using a selectable gamma value of 1/2.2 or 1/2.8. The gamma-corrected RGB data from either the correction function in linear mode or the input port otherwise is converted to 4:4:4 sampled YCbCr data. For the YCbCr input formats, the encoder converts the 4:2:2 sampled data to 4:4:4 sampled data. The conversion is done by 2x upsampling the Cb and Cr data. The upsampling function uses linear interpolation. Pixel Data Input Formats The HMP8154 accepts pixel data via the P0-P23 input pins. The definition of each pixel input pin is determined by the input format selected in the input format register. The definition for each mode is shown in Table 1. YCbCr Pixel Data The HMP8154/HMP8156A accepts 4:2:2 sampled YCbCr input data. The luminance and color difference signals are each 8 bits, scaled 0 to 255. The nominal range for Y is 16 (black) to 235 (white). Y values less than 16 are clamped to 16; values greater than 235 are processed normally. The nominal range for Cb and Cr is 16 to 240 with 128 representing zero. Cb and Cr values outside their nominal range are processed normally. Note that when converted to the analog outputs, some combinations of YCbCr outside their nominal ranges would generate a composite video signal Overlay Processing The HMP8154/HMP8156A accepts overlay data via the OL0-OL2, M0, and M1 pins. Overlay mixing is done using the 4:4:4 YCbCr pixel data from the color space converter. The YCbCr data following overlay processing is used as input data by the video processing functions. The OL0-OL2 inputs select the color to be mixed with the pixel data. Overlay colors 1-7 are standard color bar colors. Overlay color 0 is special and disables mixing on a pixel-bypixel basis. The overlay color palette is shown in Table 2. 3 4343.4 November 4, 2005 HMP8154, HMP8156A TABLE 1. PIXEL DATA INPUT FORMATS PIN NAME P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 16-BIT 4:2:2 YCBCR Cb0, Cr0 Cb1, Cr1 Cb2, Cr2 Cb3, Cr3 Cb4, Cr4 Cb5, Cr5 Cb6, Cr6 Cb7, Cr7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y0, Cb0, Cr0 Y1, Cb1, Cr1 Y2, Cb2, Cr2 Y3, Cb3, Cr3 Y4, Cb4, Cr4 Y5, Cb5, Cr5 Y6, Cb6, Cr6 Y7, Cb7, Cr7 8-BIT 4:2:2 YCBCR BLUE SCREEN 16-BIT RGB (5, 6, 5) B0 B1 B2 B3 B4 G0 G1 G2 Ignored G3 G4 G5 R0 R1 R2 R3 R4 24-BIT RGB B0 B1 B2 B3 B4 B5 B6 B7 G0 G1 G2 G3 G4 G5 G6 G7 R0 R1 R2 R3 R4 R5 R6 R7 BT.656 Ignored YCbCr Data, SAV and EAV Sequences OL0 OL1 OL2 M0 M1 - TABLE 2. OVERLAY COLOR PALETTE OL2-OL0 000 001 010 011 100 101 110 111 COLOR TABLE 3. OVERLAY MIXING FACTORS M1, M0 % OVERLAY COLOR 0 12.5 87.5 100 % PIXEL COLOR 100 87.5 12.5 0 Pixel Data 75% Blue 75% Red 75% Magenta 75% Green 75% Cyan 75% Yellow 100% White 00 01 10 11 In external mixing mode, there is no minimum number of pixels an overlay color or pixel color must be selected. The mixing level may also vary at any rate. Note that overlay capability is not available when the 24-bit RGB input format is used. The encoder provides 4 methods for mixing the overlay data with the pixel data: disabled, external mixing, internal mixing and no mixing. The method used is selected in the input format control register. Overlay Mixing: Internal Mixing of overlay and pixel data may also be controlled internally, and the M1 and M0 input pins are ignored. A transition from pixel data to overlays, from overlays to pixel data, or between different overlay colors triggers the mixing function. An overlay color must be selected for a minimum of three pixels for proper overlay operation in this mode. Internal overlay mixing should not be used with the BT.656 input format. When going from pixel to overlay data, mixing starts one pixel before the selection of the overlay color (OL2-OL1 != 000). The first pixel output before the overlay uses 12.5% overlay color plus 87.5% pixel color. The next output is aligned with the selection of the overlay color and uses 87.5% overlay color plus 12.5% pixel color. Additional outputs use 100% overlay color. When going from overlay to pixel data, mixing starts one pixel before the selection of the pixel color (OL2-OL0 = 000). 4343.4 November 4, 2005 Overlay Mixing: Disabled When overlay mixing is disabled, the OL0-OL2, M0, and M1 inputs are ignored and the pixel data is not changed. Overlay Mixing: External When external overlay mixing is selected, mixing of overlay data and pixel data is controlled by the M1 and M0 inputs. M1 and M0 indicate the mixing level between the pixel inputs and the overlay inputs, on a pixel-by-pixel basis. M1 and M0 are ignored if OL2-OL0 = 000. Otherwise, they select the percentage of each color to sum as shown in Table 3. 4 HMP8154, HMP8156A The last pixel output of the overlay uses 87.5% overlay color plus 12.5% pixel color. The next output uses 12.5% overlay color plus 87.5% pixel color. Additional outputs use 100% pixel color. When going from one overlay color to another, mixing starts one pixel before the selection of the new overlay color, and uses 12.5% new overlay color plus 87.5% old overlay color. The next output is aligned with the selection of the new overlay color and uses 87.5% new overlay color plus 12.5% old overlay color. Additional outputs use 100% new overlay color. Flicker Filter Processing Following overlay processing, vertical flicker filtering may optionally be applied to the pixel data by the HMP8154. The HMP8156A does not provide flicker filter capability. In flicker filter mode, the HMP8154 accepts non-interlaced NTSC (PAL) full resolution video with 525 (625) lines per frame at 59.94 (50) frames per second. It generates standard interlaced video with 262.5 (312.5) lines per field at 59.94 (50) fields per second. Each frame of non-interlaced video is vertically low pass filtered and used to generate either an odd or even field of video. This mode of operation reduces flickering caused by image details that are less than two pixels high. Since an entire frame of input is used to generate one field of output, the input pixel data rate is doubled when the flicker filter is enabled. The encoder must receive two lines of data during each line time. For rectangular pixel NTSC and PAL video, the input rate is 27.0MHz during the active portion of each line instead of 13.5MHz. Because of the high input data rate, 8-bit YCbCr and BT.656 input formats and 2X upscaling of SIF input may not be used when the flicker filter is enabled. The HMP8154 uses internal line stores and a 3 tap FIR filter to reduce flickering. The filter coefficients are 0.25, 0.5, and 0.25. At the start and end of each field, the coefficients are modified to compensate for the insufficient number of lines available for processing. When filtering is enabled, there is an additional two line time delay through the encoder. After flicker filtering, the input is 4:4:4 YCbCr data ready for video processing. 2X upscaling is not available when the flicker filter is enabled. Overlay Mixing: No Mixing With no overlay mixing selected, whenever the OL0-OL2 inputs are non-zero, the overlay color is displayed. The M0 and M1 inputs are ignored, and no internal mixing is done. Essentially, this is a hard switch between overlay and pixel data. In this mode, there is no minimum number of pixels an overlay color or pixel color must be selected. 2X Upscaling Processing Following overlay processing, 2X upscaling may optionally be applied to the pixel data. In this mode, the HMP8154/HMP8156A accepts NTSC (PAL) SIF resolution video at 59.94 (50) frames per second and generates standard interlaced video with 262.5 (312.5) lines per field at 59.94 (50) fields per second. This mode of operation allows SIF video to be upscaled to full resolution and recorded on a VCR or displayed on a TV. SIP upscaling may be used to simplify PC to TV applications. The input pixel data rate is reduced by half when 2X upscaling is enabled. The color space conversion generates, and the overlay mixer uses, 2:2:2 YCbCr data instead of 4:4:4 data. For rectangular pixel NTSC and PAL video, the input rate is 6.75MHz during the active portion of each line instead of 13.5MHz. Example SIF input resolutions and resulting output resolutions are shown in Table 4. TABLE 4. TYPICAL RESOLUTIONS FOR 2X UPSCALING INPUT ACTIVE RESOLUTION 352 x 240 352 x 288 320 x 240 384 x 288 OUTPUT ACTIVE RESOLUTION 704 x 480 704 x 576 640 x 480 768 x 576 Pixel Input and Control Signal Timing The pixel input timing and the video control signal input/output timing of the HMP8154/HMP8156A depend on the part’s operating mode. The periods when the encoder samples its inputs and generates its outputs are summarized in Table 5. Figures 1-12 show the timing of CLK, CLK2, BLANK, and the pixel and overlay input data with respect to each other. BLANK may be an input or an output; the figures show both. When it is an input, BLANK must arrive coincident with the pixel and overlay input data; all are sampled at the same time. When BLANK is an output, its timing with respect to the pixel and overlay inputs depends on the blank timing select bit in the timing_I/O_1 register. If the bit is cleared, the HMP8154/HMP8156A deasserts BLANK one CLK cycle before it samples the pixel and overlay inputs. As shown in the timing figures, the encoder samples the inputs 1-7 CLK2 periods after negating BLANK, depending on the operating mode. If the bit is set, the encoder deasserts BLANK during the same CLK cycle in which it samples the input data. In effect, the input data must arrive one CLK cycle earlier than when the bit is cleared. This mode is not shown in the figures. 4343.4 November 4, 2005 The HMP8154/HMP8156A performs horizontal 2X upscaling by linear interpolation. The vertical scaling is done by line duplication. For typical line duplication, the same frame of SIF pixel input data is used for both the odd and even fields. Note that a frame of SIF size input has about the same number of lines as a field of full size input. After 2X upscaling, the input is 4:4:4 YCbCr data ready for video processing. Flicker filtering is not available when 2X upscaling is enabled. 5 HMP8154, HMP8156A TABLE 5. PIXEL INPUT AND CONTROL SIGNAL I/O TIMING MODE (NOTE 1) INPUT PORT SAMPLING PIXEL DATA Every rising edge of CLK2 OVERLAY DATA Same edge that latches Y VIDEO TIMING CONTROL (NOTE 2) INPUT SAMPLE Every rising edge of CLK2 OUTPUT ON Any rising edge of CLK2 CLK FREQUENCY INPUT Ignored OUTPUT One-half CLK2 INPUT FORMAT 8-Bit YCbCr Norm 2X Same edge that Rising edge of CLK2 when CLK is latches Y data low. Rising edge of Rising edge of CLK2 when CLK is CLK2 when CLK is high. low. Not Available One-half CLK2 FF 16-Bit YCbCr, 16-Bit RGB, or 24-Bit RGB Norm Rising edge of CLK2 when CLK is low Rising edge of CLK2 when CLK is high. Either rising CLK2 edge when CLK is high Every rising edge of CLK2 Not Allowed Any rising edge of CLK2 Any rising edge of CLK2 One-half CLK2 2X 2nd rising edge of CLK2 when CLK is low One-fourth CLK2 FF Every rising edge of CLK2 Every rising edge of CLK2 Same edge that latches Y Same edge that latches Y Ignored One-half CLK2 One-half CLK2 BT.656 Norm Ignored 2X FF NOTES: 1. Encoder operating modes: Norm = Full size input, Flicker filter disabled. 2X = SIF size input, Flicker filter disabled. FF = Full size input, Flicker filter enabled. (2X upscaling and flicker filtering are mutually exclusive.) Not Available Not Available 2. Video timing control signals include HSYNC, VSYNC, BLANK and FIELD. The sync and blanking I/O directions are independent; FIELD is always an output. Normal 8-Bit YCbCr Format When 8-bit YCbCr format is selected and 2X upscaling or flicker filtering is not enabled, the data is latched on each rising edge of CLK2. The pixel data must be [Cb Y Cr Y’ Cb Y Cr Y’ . . . ], with the first active data each scan line being Cb data. Overlay data is latched when the Y input data is latched. The pixel and overlay input timing is shown in Figure 1. As inputs, BLANK, HSYNC, and VSYNC are latched on each rising edge of CLK2. As outputs, BLANK, HSYNC, and VSYNC are output following the rising edge of CLK2. If the CLK pin is configured as an input, it is ignored. If configured as an output, it is one-half the CLK2 frequency. 8-Bit YCbCr Format with 2X Upscaling When 8-bit YCbCr format is selected and 2X upscaling is enabled, the data is latched on the rising edge of CLK2 while CLK is low. The pixel data must be [Cb Y Cr Y’ Cb Y Cr Y’. . . ], with the first active data each scan line being Cb data. Overlay data is latched on the rising edge of CLK2 that latches Y pixel input data. The pixel and overlay input timing is shown in Figure 2. As inputs, BLANK, HSYNC, and VSYNC are latched on the rising edge of CLK2 while CLK is low. As outputs, HSYNC, VSYNC, and BLANK are output following the rising edge of CLK2 while CLK is high. In this mode of operation, CLK is one-half the CLK2 frequency. 6 4343.4 November 4, 2005 HMP8154, HMP8156A CLK2 P8-P15 Cb 0 Y0 Cr 0 Y1 Cb 2 Y2 YN OL0-OL2, M1, M0 BLANK (INPUT) BLANK (OUTPUT) PIXEL 0 PIXEL 1 PIXEL 2 PIXEL N FIGURE 1. PIXEL AND OVERLAY INPUT TIMING - NORMAL 8-BIT YCBCR CLK2 CLK P8-P15 Cb 0 Y0 Cr 0 Y1 Cb 2 Y2 YN OL0-OL2, M1, M0 BLANK (INPUT) BLANK (OUTPUT) PIXEL 0 PIXEL 1 PIXEL 2 PIXEL N FIGURE 2. PIXEL AND OVERLAY INPUT TIMING - 8-BIT YCBCR WITH 2X UPSCALING Normal 16-Bit YCbCr, 16-Bit RGB, 24-Bit RGB Formats When 16-bit YCbCr, 16-bit RGB data, or 24-bit RGB format is selected without 2X upscaling or flicker filtering, the pixel data is latched on the rising edge of CLK2 while CLK is low. Overlay data is also latched on the rising edge of CLK2 while CLK is low. The pixel and overlay input timing is shown in Figures 3 - 5. As inputs, BLANK, HSYNC, and VSYNC are latched on the rising edge of CLK2 while CLK is low. As outputs, HSYNC, VSYNC, and BLANK are output following the rising edge of CLK2 while CLK is high. In these modes of operation, CLK is one-half the CLK2 frequency. 7 4343.4 November 4, 2005 HMP8154, HMP8156A CLK2 CLK P8-P15 Y0 Y1 Y2 Y3 Y4 Y5 YN P0-P7 Cb 0 Cr 0 Cb 2 Cr 2 Cb 4 Cr 4 Cr N-1 OL0-OL2, M1, M0 BLANK (INPUT) BLANK (OUTPUT) PIXEL 0 PIXEL 1 PIXEL 2 PIXEL 3 PIXEL 4 PIXEL 5 PIXEL N FIGURE 3. PIXEL AND OVERLAY INPUT TIMING - NORMAL 16-BIT YCBCR CLK2 CLK P0-P15 RGB 0 RGB 1 RGB 2 RGB 3 RGB 4 RGB 5 RGB N OL0-OL2, M1, M0 BLANK (INPUT) BLANK (OUTPUT) PIXEL 0 PIXEL 1 PIXEL 2 PIXEL 3 PIXEL 4 PIXEL 5 PIXEL N FIGURE 4. PIXEL AND OVERLAY INPUT TIMING - NORMAL 16-BIT RGB CLK2 CLK P0-P24 RGB 0 RGB 1 RGB 2 RGB 3 RGB 4 RGB 5 RGB N BLANK (INPUT) BLANK (OUTPUT) FIGURE 5. PIXEL AND OVERLAY INPUT TIMING - NORMAL 24-BIT RGB 8 4343.4 November 4, 2005 HMP8154, HMP8156A 16-Bit YCbCr, 16-Bit RGB, 24-Bit RGB Formats with 2X Upscaling When 16-bit YCbCr, 16-bit RGB data, or 24-bit RGB format is selected and 2X upscaling is enabled, data is latched on the rising edge of CLK2 while CLK is low. Overlay data is latched on the rising edge of CLK2 while CLK is low. The pixel and overlay input timing is shown in Figures 6-8. CLK2 As inputs, BLANK, HSYNC, and VSYNC are latched on the rising edge of CLK2 while CLK is low. As outputs, HSYNC, VSYNC, and BLANK are output following the rising edge of CLK2 while CLK is high. CLK is one-fourth the CLK2 frequency. CLK P8-P15 Y0 Y1 YN P0-P7 Cb 0 OL0-OL2, M1, M0 BLANK (INPUT) BLANK (OUTPUT) Cr 0 Cr N-1 PIXEL 0 PIXEL 1 PIXEL N FIGURE 6. PIXEL AND OVERLAY INPUT TIMING - 16-BIT YCBCR WITH 2X UPSAMPLING CLK2 CLK P0-P15 RGB 0 RGB 1 RGB N OL0-OL2, M1, M0 BLANK (INPUT) BLANK (OUTPUT) PIXEL 0 PIXEL 1 PIXEL N FIGURE 7. PIXEL AND OVERLAY INPUT TIMING - 16-BIT RGB WITH 2X UPSAMPLING CLK2 CLK P0-P24 RGB 0 RGB 1 RGB N BLANK (INPUT) BLANK (OUTPUT) FIGURE 8. PIXEL AND OVERLAY INPUT TIMING - 24-BIT RGB WITH 2X UPSAMPLING 9 4343.4 November 4, 2005 HMP8154, HMP8156A 16-Bit YCbCr, 16-Bit RGB, 24-Bit RGB Formats with Flicker Filtering When the 16-bit YCbCr, 16-bit RGB, or 24-bit RGB data format is selected and flicker filtering is enabled, pixel and overlay data is latched on every rising edge of CLK2. The pixel and overlay input timing is shown in Figures 9-11. As inputs, BLANK, HSYNC, and VSYNC are latched on each rising edge of CLK2. As outputs, BLANK, HSYNC, and VSYNC are output following the rising edge of CLK2. If the CLK pin is configured as an input, it is ignored. If configured as an output, it is one-half the CLK2 frequency. CLK2 P8-P15 Y0 Y1 Y2 Y3 Y4 Y5 YN P0-P7 Cb 0 Cr 0 Cb 2 Cr 2 Cb 4 Cr 4 Cr N-1 OL0-OL2, M1, M0 BLANK (INPUT) BLANK (OUTPUT) PIXEL 0 PIXEL 1 PIXEL 2 PIXEL 3 PIXEL 4 PIXEL 5 PIXEL N FIGURE 9. PIXEL AND OVERLAY INPUT TIMING - 16-BIT YCBCR WITH FLICKER FILTERING CLK2 P0-P15 RGB 0 RGB 1 RGB 2 RGB 3 RGB 4 RGB 5 RGB N OL0-OL2, M1, M0 BLANK (INPUT) BLANK (OUTPUT) PIXEL 0 PIXEL 1 PIXEL 2 PIXEL 3 PIXEL 4 PIXEL 5 PIXEL N FIGURE 10. PIXEL AND OVERLAY INPUT TIMING - 16-BIT RGB WITH FLICKER FILTERING CLK2 P0-P23 RGB 0 RGB 1 RGB 2 RGB 3 RGB 4 RGB 5 RGB N BLANK (INPUT) BLANK (OUTPUT) FIGURE 11. PIXEL AND OVERLAY INPUT TIMING - 24-BIT RGB WITH FLICKER FILTERING 10 4343.4 November 4, 2005 HMP8154, HMP8156A CLK2 P8-P15 Cb 2 Y2 Cr 2 Y3 Cb 4 Y4 "FF" "00" "00" "XY" "10" "80" "10" OL0-OL2, M1, M0 BLANK (OUTPUT) PIXEL 0 PIXEL 1 PIXEL N-2 PIXEL N-1 PIXEL N FIGURE 12. PIXEL AND OVERLAY INPUT TIMING - BT.656 8-Bit BT.656 Format When BT.656 format is selected, data is latched on each rising edge of CLK2. Overlay data is latched when the Y input data is latched. However, the overlay data must arrive three pixels after its corresponding Y data. The pixel and overlay input timing is shown in Figure 12. As inputs, the BLANK, HSYNC, and VSYNC pins are ignored since all timing is derived from the EAV and SAV sequences within the data stream. As outputs, BLANK, HSYNC and VSYNC are output following the rising edge of CLK2. If the CLK pin is configured as an input, it is ignored. If configured as an output, it is one-half the CLK2 frequency. Square pixel operation, overlay processing with internal mixing, flicker filtering, and SIF mode 2X upsampling are not supported for the BT.656 input format. Also, the HSYNC, VSYNC, and BLANK signals must be configured as outputs. odd field. At the start of an even field, the leading edge of VSYNC occurs in the middle of the line. When HSYNC and VSYNC are configured as inputs, the HMP8154/HMP8156A provides a programmable HSYNC window for determining FIELD. The window is specified with respect to the leading or trailing edge of VSYNC. The edge is selected in the field control register. When HSYNC is found inside the window, then the encoder sets FIELD to the value specified in the field control register. The HMP8154/HMP8156A provides programmable timing for the VSYNC input. At the active edge of VSYNC, the encoder resets its vertical half-line counter to the value specified by the field control register. This allows the input and output syncs to be offset, although the data must still be aligned. The FIELD signal is always an output and changes state near each leading edge of VSYNC. The delay between the syncs and FIELD depends on the encoder’s operating mode as summarized in Table 6. In modes in which the encoder uses CLK to gate its inputs and outputs, the FIELD signal may be delayed 0-12 additional CLK2 periods. Figure 13 illustrates the HSYNC, VSYNC, and FIELD general timing for (M, NSM) NTSC and (M, N) PAL. Figure 14 illustrates the general timing for (B, D, G, H, I, CN) PAL. In the figures, all the signals are shown active low (their reset state), and FIELD is low during odd fields. TABLE 6. FIELD OUTPUT TIMING OPERATING MODE SYNC I/O BLANK I/O CLK2 DIRECTION DIRECTION DELAY Input Input 148 COMMENTS FIELD lags VSYNC switching from odd to even. FIELD lags the earlier of VSYNC and HSYNC when syncs are aligned when switching from even to odd. FIELD lags VSYNC. FIELD leads VSYNC. Video Timing Control Regardless of the input mode, the output video timing of the HMP8154/HMP8156A is at 50 or 59.94 fields per second (interlaced). For normal and 2X upscaling modes, the pixel input timing is at 50 or 59.94 fields per second; with the flicker filter enabled, the input timing rate is twice as fast. The output video and pixel input timing is controlled by the BLANK, HSYNC, VSYNC, FIELD, and CLK2 pins. HSYNC, VSYNC, and Field Timing The leading edge of HSYNC indicates the beginning of a horizontal sync interval. If HSYNC is an output, it is asserted for about 4.7µs. If HSYNC is an input, it must be active for at least two CLK2 periods. The width of the horizontal composite sync tip is determined from the video standard and does not depend on the width of HSYNC. The leading edge of VSYNC indicates the beginning of a vertical sync interval. If VSYNC is an output, it is asserted for 3 scan lines in (M, NSM) NTSC and (M, N) PAL modes or 2.5 scan lines in (B, D, G, H, I, CN) PAL modes. If VSYNC is an input, it must be asserted for at least two CLK2 periods. When HSYNC and VSYNC are configured as outputs, their leading edges will occur simultaneously at the start of an Input Output Output Don’t Care 138 32 11 4343.4 November 4, 2005 HMP8154, HMP8156A There must be an even number of active and total pixels per line. In the 8-bit YCbCr modes, the number of active and total pixels per line must be a multiple of four. Note that if BLANK is an output, half-line blanking on the output video cannot be done. The HMP8154/HMP8156A never adds a 7.5 IRE blanking setup during the active line time on scan lines 1-21 and 263284 for (M, NSM) NTSC, scan lines 523-18 and 260-281 for (M) PAL, and scan lines 623-22 and 311-335 for (N) PAL, allowing the generation of video test signals, timecode, and other information by controlling the pixel inputs appropriately. HSYNC VSYNC FIELD FIGURE 13A. BEGINNING AN ODD FIELD HSYNC Normal Mode Blanking The relative timing of BLANK, HSYNC, and the output video depends on the blanking and sync I/O directions. The typical timing relation is shown in Figure 15. The delays which vary with operating mode are indicated. The width of the composite sync tip and the location and duration of the color burst are fixed based on the video format. . VSYNC FIELD FIGURE 13B. BEGINNING AN EVEN FIELD FIGURE 13. HSYNC, VSYNC, AND FIELD TIMING FOR (M, NSM) NTSC AND (M, N) PAL HSYNC HSYNC VSYNC COMPOSITE VIDEO OUT BLANK DATA PIPE DELAY FIELD START H BLANK SYNC DELAY FIGURE 14A. BEGINNING AN ODD FIELD FIGURE 15. HSYNC, BLANK, AND OUTPUT VIDEO TIMING, NORMAL MODE HSYNC VSYNC FIELD When BLANK is an output, the encoder asserts it during the inactive portions of active scan lines (horizontal blanking) and for all of each inactive scan line (vertical blanking). The inactive scan lines blanked each field are determined by the start_v_blank and end_v_blank registers. The inactive portion of active scan lines is determined by the start_h_blank and end_h_blank registers. FIGURE 14B. BEGINNING AN EVEN FIELD FIGURE 14. HSYNC, VSYNC, AND FIELD TIMING FOR (B, D, G, H, I, CN) PAL BLANK Timing The encoder uses the HSYNC, VSYNC, FIELD signals to generate a standard composite video waveform with no active video (black burst). The signal includes only sync tips, color burst, and optionally, a 7.5 IRE blanking setup. Based on the BLANK signal, the encoder adds the pixel and overlay input data to the video waveform. The encoder ignores the pixel and overlay input data when BLANK is asserted. Instead of the input data, the encoder generates the blanking level. The encoder also ignores the pixel and overlay inputs when generating closed captioning data on a specific line, even if BLANK is negated. 12 The zero count for horizontal blanking is 32 CLK2 cycles before the 50% point of the composite sync. From this zero point, the HMP8154/HMP8156A counts every other CLK2 cycle. When the count reaches the value in the start_h_blank register, the encoder negates BLANK. When the count reaches the value in the end_h_blank register, BLANK is asserted. There may be an additional 0-7 CLK2 delays in modes which use CLK. The data pipeline delay through the HMP8154/HMP8156A is 26 CLK2 cycles. In operating modes which use CLK to gate the inputs into the encoder, the delay may be an additional 0-7 CLK2 cycles. The delay from BLANK to the start or end of active video is an additional one-half CLK cycle when the blank timing select bit is cleared. The active video may also appear to end early or start late since the HMP8154/HMP8156A controls the blanking edge rates. 4343.4 November 4, 2005 HMP8154, HMP8156A The delay from the active edge of HSYNC to the 50% point of the composite sync is 4-39 CLK2 cycles depending on the HMP8154/HMP8156A operating mode. The delay is shortest when the encoder is the timing master; it is longest when in slave mode. intervals are not. The count values for BLANK transitions are shown in Figure 17. HSYNC Flicker Filter Blanking When the flicker filter is enabled, BLANK occurs twice per line. However, HSYNC does not change and still matches the horizontal syncs of the composite output. The default timing of BLANK with respect to HSYNC is shown in Figure 16. BLANK 0 TOTAL END_H_BLANK / 2 + TOTAL -- ACTIVE START_H_BLANK END_H_BLANK HSYNC END_H_BLANK / 2 BLANK FIGURE 17. FLICKER FILTER BLANK OUTPUT TIMING COUNTS. TOTAL DEPENDS ON FORMAT. ACTIVE = START_H_BLANK -- END_H_BLANK PIXEL DATA LINE # FIELD 0† 1 2† 3 CLK2 Input Timing The CLK2 input clocks all of the HMP8154/HMP8156A, including its video timing counters. For proper operation, all of the HMP8154/HMP8156A inputs must be synchronous with CLK2. The frequency of CLK2 depends on the device’s operating mode and the total number of pixels per line. The standard clock frequencies are shown in Table 7. Note that the color subcarrier is derived from the CLK2 input. Any jitter on CLK2 will be transferred to the color subcarrier, resulting in color changes. Just 400ps of jitter on CLK2 causes up to a 1 degree color subcarrier phase shift. Thus, CLK2 should be derived from a stable clock source, such as a crystal. The use of a PLL to generate CLK2 is not recommended. FIGURE 16A. BEGINNING AN EVEN FIELD HSYNC BLANK PIXEL DATA LINE # FIELD 0 1† 2 3† Video Processing Upsampling FIGURE 16B. BEGINNING AN ODD FIELD FIGURE 16. HSYNC AND BLANK TIMING WITH THE FLICKER FILTER ENABLED. VSYNC ALIGNS WITH EITHER EDGE OF FIELD. † UNBLANKED PERIOD WHICH DETERMINES ACTIVE VIDEO IN OUTPUT. Video processing begins with the 4:4:4 sampled YCbCr data from the input processor. After overlay mixing and optional 2X upscaling or flicker filtering, the HMP8154/HMP8156A upsamples the 4:4:4 data to generate 8:8:8 data. The encoder uses linear interpolation for the upsampling. Horizontal Filtering Only the first unblanked period during each line time determines when the active video will be output. Because of the half line offset between the H and V syncs, pixel data input begins (blanking ends) in the middle of the line time for odd fields. However, it is still the unblanked period immediately after HSYNC which generates the active region of the output video. During even fields, the unblanking pulses for the even numbered lines determine the output timing; during odd fields, it’s the odd numbered lines. When it is an output and the flicker filter is enabled, BLANK generation is similar to that found in normal mode. The main difference is that the encoder counts every CLK2 instead of every other CLK2. The start and end times for each line’s second unblanked interval are shifted slightly. The unblanked intervals are the same number of pixels but the blanked 13 Unless disabled, the HMP8154/HMP8156A lowpass filters the Y data to 6.0MHz. Lowpass filtering Y removes any aliasing artifacts due to the upsampling process, and simplifies the analog output filters. The Y 6.0MHz lowpass filter response is shown in Figure 18. At this point, the HMP8154/HMP8156A also scales the Y data to generate the proper output levels for the various video standards The HMP8154/HMP8156A lowpass filters the Cb and Cr data to 1.3MHz prior to modulation. The lowpass filtering removes any aliasing artifacts due to the upsampling process (simplifying the analog output filters) and also properly bandwidth-limits Cb and Cr prior to modulation. The chrominance filtering is not optional like luminance filtering. The Cb and Cr 1.3MHz lowpass filter response is shown in Figure 19. 4343.4 November 4, 2005 HMP8154, HMP8156A TABLE 7. TYPICAL VIDEO TIMING PARAMETERS PIXELS PER LINE VIDEO STANDARD TOTAL ACTIVE HBLANK REGISTER VALUES START END VBLANK REGISTER VALUES START END CLK2 (MHz) FULL INPUT RESOLUTION, RECTANGULAR PIXELS (M, NSM) NTSC (B, D, G, H, I) PAL (M) PAL (N) PAL (CN) PAL 858 864 858 864 864 720 720 720 720 720 842 (0x34a) 853 (0x355) 842 (0x34a) 853 (0x355) 853 (0x355) 122 (0x7a) 133 (0x85) 122 (0x7a) 133 (0x85) 133 (0x85) 259 (0x103) 310 (0x136) 259 (0x103) 309 (0x135) 310 (0x136) 19 (0x13) 22 (0x16) 19 (0x13) 21 (0x15) 22 (0x16) 27.0 27.0 27.0 27.0 27.0 FULL INPUT RESOLUTION, SQUARE PIXELS (M, NSM) NTSC (B, D, G, H, I) PAL (M) PAL (N) PAL (CN) PAL 780 944 780 944 944 640 768 640 768 768 758 (0x2f6) 923 (0x39b) 758 (0x2f6) 923 (0x39b) 923 (0x39b) 118 (0x76) 155 (0x9b) 118 (0x76) 155 (0x9b) 155 (0x9b) 259 (0x103) 310 (0x136) 259 (0x103) 309 (0x135) 310 (0x136) 19 (0x13) 22 (0x16) 19 (0x13) 21 (0x15) 22 (0x16) 24.54 29.5 24.54 29.5 29.5 SIF INPUT RESOLUTION, RECTANGULAR PIXELS (M, NSM) NTSC (B, D, G, H, I) PAL (M) PAL (N) PAL (CN) PAL 429 432 429 432 432 352 352 352 352 352 834 (0x342) 845 (0x34d) 842 (0x34a) 853 (0x355) 853 (0x355) 130 (0x82) 141 (0x8d) 122 (0x7a) 133 (0x85) 133 (0x85) 259 (0x103) 310 (0x136) 259 (0x103) 309 (0x135) 310 (0x136) 19 (0x13) 22 (0x16) 19 (0x13) 21 (0x15) 22 (0x16) 27.0 27.0 27.0 27.0 27.0 SIF INPUT RESOLUTION, SQUARE PIXELS (M, NSM) NTSC (B, D, G, H, I) PAL (M) PAL (N) PAL (CN) PAL 390 472 390 472 472 320 384 320 384 384 758 (0x2f6) 923 (0x39b) 758 (0x2f6) 923 (0x39by) 923 (0x39b) 118 (0x76) 155 (0x9b) 118 (0x76) 155 (0x9b) 155 (0x9b) 259 (0x103) 310 (0x136) 259 (0x103) 309 (0x135) 310 (0x136) 19 (0x13) 22 (0x16) 19 (0x13) 21 (0x15) 22 (0x16) 24.54 29.5 24.54 29.5 29.5 . 0 -10 ATTENUATION (dB) -20 -30 -40 -50 -60 0 2 4 6 8 10 12 14 FREQUENCY (MHz) PAL SQUARE PIXEL CLK2 = 29.50MHz NTSC OR PAL RECTANGULAR PIXEL CLK2 = 27.00MHz NTSC SQUARE PIXEL CLK2 = 24.54MHz ATTENUATION (dB) 0 -0.5 PAL SQUARE PIXEL CLK2 = 29.50MHz -1.0 -1.5 -2.0 NTSC SQUARE PIXEL CLK2 = 24.54MHz -2.5 -3.0 0 1 2 3 4 FREQUENCY (MHz) 5 6 7 NTSC OR PAL RECTANGULAR PIXEL CLK2 = 27.00MHz FIGURE 18A. FULL SPECTRUM FIGURE 18. Y LOWPASS FILTER RESPONSE . FIGURE 18B. PASS BAND 14 4343.4 November 4, 2005 HMP8154, HMP8156A 0 PAL SQUARE PIXEL CLK2 = 29.50MHz NTSC OR PAL RECTANGULAR PIXEL CLK2 = 27.00MHz NTSC SQUARE PIXEL CLK2 = 24.54MHz -10 ATTENUATION (dB) -20 Resetting the SCH phase every four fields (NTSC) or eight fields (PAL) avoids the accumulation of SCH phase error at the expense of requiring any NTSC/PAL decoder after the encoder be able to handle very minor “jumps” (up to 2o) in the SCH phase at the beginning of each four-field or eightfield sequence. Most NTSC/PAL decoders are able to handle this due to video editing requirements. -30 Composite Video Limiting The HMP8154/HMP8156A adds the luminance and modulated chrominance together with the sync, color burst, and optional blanking pedestal to form the composite video data. If enabled in the video processing register, the encoder limits the active video so that it is always greater than one-eighth of full scale. This corresponds to approximately one-half the sync height. This allows the generation of “safe” video in the event nonstandard YCbCr values are input to the device. -40 -50 -60 0 1 2 3 4 5 6 FREQUENCY (MHz) FIGURE 19A. FULL SPECTRUM 0 -0.5 -1.0 ATTENUATION (dB) -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 FREQUENCY (MHz) NTSC OR PAL RECTANGULAR PIXEL CLK2 = 27.00MHz PAL SQUARE PIXEL CLK2 = 29.50MHz Closed Captioning If enabled in the auxiliary data control register, the HMP8154/HMP8156A generates closed captioning data on specified scan lines. The captioning data stream includes clock run-in and start bits followed by the captioning data. During closed captioning encoding, the pixel and overlay inputs are ignored on the scan lines containing captioning information. The HMP8154/HMP8156A has two 16-bit registers containing the captioning information. Each 16-bit register is organized as two cascaded 8-bit registers. One 16-bit register (caption 21) is read out serially during line 18, 21 or 22; the other 16-bit register (caption 284) is read out serially during line 281, 284 or 335. The data registers are shifted out LSB first. The bytes may be written in any order but both must be written within one frame time for proper operation. If the registers are not updated, the encoder resends the previously loaded values. The HMP8154/HMP8156A provides a write status bit for each captioning line. The encoder clears the write status bit to ‘0’ when captioning is enabled and both bytes of the captioning data register have been written. The encoder sets the write status bit to ‘1’ after it outputs the data, indicating the registers are ready to receive new data. Captioning information may be enabled for either line, both lines, or no lines. The captioning modes are summarized in Table 8. NTSC SQUARE PIXEL CLK2 = 24.54MHz FIGURE 19B. PASS BAND FIGURE 19. Cb AND Cr LOWPASS FILTER RESPONSE Chrominance Modulation The HMP8154/HMP8156A uses a numerically controlled oscillator (NCO) clocked by CLK2 and a sine look up ROM to generate the color subcarrier. The subcarrier from the ROM is pre-scaled to generate the proper levels for the various video standards. Prescaling outside the CbCr data path minimizes color processing artifacts. The HMP8154/HMP8156A modulates the filtered 8:8:8 chrominance data with the synthesized subcarrier. Subcarrier Phase The SCH phase is 0 degrees after reset but then changes monotonically over time due to residue in the NCO. In an ideal system, zero SCH phase would be maintained forever. In reality, this is impossible to achieve due to pixel clock frequency tolerances. If enabled, the HMP8154/HMP8156A resets the NCO periodically to avoid an accumulation of SCH phase error. The reset occurs at the beginning of each field to burst phase sequence. The sequence repeats every 4 fields for NTSC or 8 fields for PAL. 15 Controlled Edges The NTSC and PAL video standards specify edge rates and rise and fall times for portions of the video waveform. The HMP8154/HMP8156A automatically implements controlled edge rates and rise and fall times on these edges: 1. 2. 3. 4. 5. 6. Analog horizontal sync (rising and falling edges) Analog vertical sync interval (rising and falling edges) Color burst envelope Blanking of analog active video Overlay with internal mixing Closed captioning information 4343.4 November 4, 2005 HMP8154, HMP8156A TABLE 8. CLOSED CAPTIONING MODES CLOSED CAPTIONING ENABLE BITS 00 01 None 21 (NTSC) 18 (M PAL) 22 (Other PAL) 284 (NTSC) 281 (M PAL) 335 (Other PAL) 21, 284 (NTSC) 18, 281 (M PAL) 22, 335 (Other PAL) CAPTIONING REGISTER OUTPUT LINE(S) 284A 284B Ignored Ignored 21A 21B Ignored Caption Data WRITE STATUS BIT 284 Always 1 Always 1 21 Always 1 0 = Loaded 1 = Output Always 1 10 Caption Data Ignored 0 = Loaded 1 = Output 0 = Loaded 1 = Output 11 Caption Data Caption Data 0 = Loaded 1 = Output Analog Outputs The HMP8154/HMP8156A converts the video data into analog signals using four 10-bit DACs running at the CLK2 rate. The DACs output a current proportional to the digital data. The full scale output current is determined by the reference voltage VREF and an external resistor RSET. The full scale output current is given by: IFULLSCALE (mA) = 3.9 * VREF (V)/RSET (kΩ) data into 8:8:8 RGB data. The transform matrix uses different coefficients to generate NTSC or PAL video levels. The analog RGB outputs have a range of 0.3-1.0V with an optional blanking pedestal. Composite sync information (0.00.3V) may be optionally added to the green output. Closed captioning data is not included on the RGB outputs. The HMP8154/HMP8156A also generates composite video when in RGB output mode. All four outputs are time aligned. The HMP8154/HMP8156A provides selectable pin outs for the RGB outputs. When the SCART compatibility bit is cleared, the analog composite video is output onto the NTSC/PAL 1 pin. Red information is output onto the NTSC/PAL 2 pin, blue information is output onto the C pin, and green information is output onto the Y pin. When the bit is set, the analog composite video is output onto the Y pin. Red information is output onto the C pin, blue video is output on the NTSC/PAL 2 pin, and the green signal is output on the NTSC/PAL 1 pin. The output pin assignments are summarized in Table 9. TABLE 9. OUTPUT PIN ASSIGNMENTS OUTPUT MODE (SCART SELECT BIT) PIN # 3 7 11 15 COMP. WITH Y/C (X) Luma Chroma Composite Composite COMP. W/ RGB (0) Green Blue Composite Red COMP. W/ RGB (1) Composite Red Green Blue (EQ 1.) VREF must be chosen such that it is within the part’s operating range; RSET must be chosen such that the maximum output current is not exceeded. If the VREF pin is not connected, the HMP8154/HMP8156A provides an internal reference voltage. Otherwise, the applied voltage overdrives the internal reference. If an external reference is used, it must decoupled from any power supply noise. An example external reference circuit is shown in the Applications section. The HMP8154/HMP8156A generates 1VP-P nominal video signals across 37.5Ω loads corresponding to doubly terminated 75Ω lines. The encoder may also drive larger loads. The full scale output current and load must be chosen such that the maximum output voltage is not exceeded. Output DAC Filtering Since the DACs run at 2X the pixel sample rate, the sin(x)/x rolloff of the outputs is greatly reduced, and there are fewer high frequency artifacts in the output spectrum. This allows using simple analog output filters. The analog output filter should be flat to Fs/4 and have good rejection at 3Fs/4. Example filters are shown in the Applications section. PIN NAME Y C NTSC/PAL 1 NTSC/PAL 2 Composite + Y/C Output Mode The HMP8154/HMP8156A provides three output modes: S-video, RGB, and power down. When S-video outputs are selected, the encoder outputs the luminance, modulated chrominance, and two copies of the composite video signals. All four outputs are time aligned. Power Down Modes To reduce power dissipation, any of the four output DACs may be turned off. Each DAC has an independent enable bit. Each output may be disabled in the host control register. When the power down mode is enabled, all of the DACs and internal voltage reference are powered down (forcing their outputs to zero) and the data pipeline registers are disabled. The host processor may still read from and write to the internal control registers. 4343.4 November 4, 2005 Composite + RGB Output Mode When analog RGB video is selected, the HMP8154/HMP8156A transforms the filtered 8:8:8 YCbCr 16 HMP8154, HMP8156A Host Interfaces Reset The HMP8154/HMP8156A resets to its default operating mode on power up, when the reset pin is asserted for at least four CLK cycles, or when the software reset bit of the host control register is set. During the reset cycle, the encoder returns its internal registers to their reset state and deactivates the I2C interface. I2C Interface The HMP8154/HMP8156A provides a standard I2C interface and supports fast-mode (up to 400 Kbps) transfers. The device acts as a slave for receiving and transmitting data only. It will not respond to general calls or initiate a transfer. The encoder’s slave address is either 0100 000xB when the SA input pin is low or 0100 001xB when it is high. (The ‘x’ bit in the address is the I2C read flag.) The I2C interface consists of the SDA and SCL pins. When the interface is not active, SCL and SDA must be pulled high using external 4-6kΩ pull-up resistors. The I2C clock and data timing is shown in Figures 20 and 21. During I2C write cycles, the first data byte after the slave address specifies the sub address, and is written into the address register. Only the seven LSBs of the subaddress are used; the MSB is ignored. Any remaining data bytes in the I2C write cycle are written to the control registers, beginning with the register specified by the address register. The 7-bit address register is incremented after each data byte in the I2C write cycle. Data written to reserved bits within registers or reserved registers is ignored. During I2C read cycles, data from the control register specified by the address register is output. The address register is incremented after each data byte in the I2C read cycle. Reserved bits within registers return a value of “0”. Reserved registers return a value of 00H . The HMP8154/HMP8156A’s operating modes are determined by the contents of its internal registers which are accessed via the I2C interface. All internal registers may be written or read by the host processor at any time. However, some of the bits and words are read only or reserved and data written to these bits is ignored. Table 10 lists the HMP8154/HMP8156A’s internal registers. Their bit descriptions are listed in Tables 11-30. TABLE 10. CONTROL REGISTER NAMES SUB ADDRESS (HEX) 00 01 02 03 04 05 06 07-0E 0F 10 11 12 13 14-1F 20 21 22 23 24 25 26 27 28-2F 30-7F CONTROL REGISTER Product ID Output Format Input Format Video Processing Timing I/O 1 Timing I/O 2 Aux Data Enable Reserved Host Control Closed Caption_21A Closed Caption_21B Closed Caption_284A Closed Caption_284B Reserved Start H_Blank Low Start H_Blank High End H_Blank Start V_Blank Low Start V_Blank High End V_Blank Field Control 1 Field Control 2 Reserved Test and Unused RESET CONDITION 54H 00H 06H A0H 00H 00H 00H 0CH 80H 80H 80H 80H 4AH 03H 7AH 03H 01H 13H 80H 00H - SDA SCL S START CONDITION 1-7 ADDRESS 8 R/W 9 ACK 1-7 DATA 8 9 ACK P STOP CONDITION FIGURE 20. I2C SERIAL TIMING FLOW DATA WRITE S CHIP ADDR 0x40 OR 0x42 DATA READ S CHIP ADDR 0x40 OR 0x42 A SUB ADDR A A SUB ADDR A DATA REGISTER POINTED TO BY SUBADDR S CHIP ADDR 0x41 OR 0x43 A DATA A P S = START CYCLE P = STOP CYCLE A = ACKNOWLEDGE NA = NO ACKNOWLEDGE FROM MASTER DATA NA P FROM ENCODER OPTIONAL FRAME MAY BE REPEATED n TIMES A DATA REGISTER POINTED TO BY SUBADDR A OPTIONAL FRAME MAY BE REPEATED n TIMES FIGURE 21. REGISTER WRITE PROGRAMMING FLOW 17 4343.4 November 4, 2005 HMP8154, HMP8156A TABLE 11. PRODUCT ID REGISTER SUB ADDRESS = 00H BIT NUMBER 7-0 FUNCTION Product ID DESCRIPTION This 8-bit register specifies the last two digits of the product number. It is a read-only register. Data written to it is ignored. RESET STATE 54H TABLE 12. OUTPUT FORMAT REGISTER SUB ADDRESS = 01H BIT NUMBER 7-5 FUNCTION Video Timing Standard DESCRIPTION 000 = (M) NTSC 001 = (M) NTSC with a 0 IRE setup; also called (NSM) NTSC 010 = (B, D, G, H, I) PAL 011 = (M) PAL 100 = (N) PAL 101 = combination (N) PAL; also called (CN) PAL 110 = reserved 111 = reserved 00 = Composite + Y/C 01 = reserved 10 = Composite + RGB (no sync on green) 11 = Composite + RGB (with sync on green) RESET STATE 000B 4-3 Output Format 00B 2-0 Reserved 000B TABLE 13. INPUT FORMAT REGISTER SUB ADDRESS = 02H BIT NUMBER 7-5 FUNCTION Input Format 000 = 16-bit 4:2:2 YCbCr 001 = 8-bit 4:2:2 YCbCr 010 = 8-bit BT.656 011 = 16-bit linear RGB 100 = 16-bit gamma-corrected RGB 101 = 24-bit linear RGB 110 = 24-bit gamma-corrected RGB 111 = Blue screen DESCRIPTION RESET STATE 000B 4 Gamma Select Reserved Overlay Mixing Mode These bits are ignored except during linear RGB input modes. 0 = 1 / 2.2 1 = 1 / 2.8 0B 3 2-1 0B These bits must be set to “11” in 24-bit RGB input modes. Internal mixing should not be selected in BT.656 input mode. 00 = No mixing 01 = Internal mixing 10 = External mixing 11 = Disable overlays This bit must be set to “0” during BT.656 input mode and when the flicker filter is enabled. 0 = Full resolution (2X upscaling disabled) 1 = SIF resolution (2X upscaling enabled) 11B 0 Input Resolution 0B 18 4343.4 November 4, 2005 HMP8154, HMP8156A TABLE 14. VIDEO PROCESSING REGISTER SUB ADDRESS = 03H BIT NUMBER 7 6 5 4 3 2 FUNCTION Luminance Processing Composite Video Limiting SCH Phase Mode RGB Pedestal Enable RGB pin Assignment select First Active Line Select Flicker Filter Processing 0 = None 1 = Y Lowpass filtering enabled 0 = None 1 = Lower limit of composite active video is about half the sync height 0 = Never reset SCH phase 1 = Reset SCH phase every 4 (NTSC) or 8 (PAL) fields 0 = Don’t add blanking pedestal to RGB output 1 = add blanking pedestal to RGB output 0 = use HMP8156 assignments 1 = SCART connector compatible This bit is ignored unless flicker filtering is enabled. This bit is ignored on the HMP8156. 0 = First line of active video in odd fields is on an odd line number 1 = First line of active video in odd fields is on an even line number These bits must be “00” during 8-bit YCbCr and BT.656 input modes, and SIF input resolution mode. These bits are always “00” on the HMP8156A. 00 = No flicker filtering 01 = reserved 10 = reserved 11 = 3-line flicker filtering enabled DESCRIPTION RESET STATE 1B 0B 1B 0B 0B 0B 1-0 00B TABLE 15. TIMING I/O REGISTER #1 SUB ADDRESS = 04H BIT NUMBER 7 FUNCTION BLANK Timing Select DESCRIPTION This bit is ignored unless BLANK is configured to be an output. 0 = Data for the first active pixel of the scan line must arrive the CLK cycle after the encoder negates BLANK. 1 = Data for the first active pixel of the scan line must arrive immediately after the encoder negates BLANK. RESET STATE 0B 6 5 4 3 Reserved BLANK Output Control BLANK Polarity HSYNC and VSYNC Output Control HSYNC Polarity VSYNC Polarity FIELD Polarity 0 = BLANK is an input 1 = BLANK is an output 0 = Active low (low during blanking) 1 = Active high (high during blanking) 0 = HSYNC and VSYNC are inputs 1 = HSYNC and VSYNC are outputs 0 = Active low (low during horizontal sync) 1 = Active high (high during horizontal sync) 0 = Active low (low during vertical sync) 1 = Active high (high during vertical sync) 0 = Active low (low during odd fields) 1 = Active high (high during odd fields) 0B 0B 0B 0B 2 1 0 0B 0B 0B 19 4343.4 November 4, 2005 HMP8154, HMP8156A TABLE 16. TIMING I/O REGISTER #2 SUB ADDRESS = 05H BIT NUMBER 7-5 4 3 FUNCTION Reserved CLK Output Control Aspect Ratio Mode 0 = CLK is an input 1 = CLK is an output This bit must be set to “0” during BT.656 input mode. 0 = Rectangular (BT.601) pixels 1 = Square pixels DESCRIPTION RESET STATE 000B 0B 0B 2-0 Reserved 00B TABLE 17. AUXILIARY DATA ENABLE REGISTER SUB ADDRESS = 06H BIT NUMBER 7-6 FUNCTION Closed Captioning Enable DESCRIPTION 00 = Closed caption disabled 01 = Closed caption enabled for odd fields: line 21 for NTSC, line 18 for (M) PAL, or line 22 for (B, D, G, H, I, N, CN) PAL 10 = Closed caption enabled for even fields: line 284 for NTSC, line 281 for (M) PAL, or line 335 for (B, D, G, H, I, N, CN) PAL 11 = Closed caption enabled for both odd and even fields RESET STATE 00B 5-0 Reserved 000000B TABLE 18. HOST CONTROL REGISTER SUB ADDRESS = 0FH BIT NUMBER 7 6 5 4 FUNCTION Software Reset Power Down Enable NTSC/PAL 2 Output Mode Closed Caption Line 21 Write Status Closed Caption Line 284 Write Status NTSC/PAL 1 Output Mode Y/G Output Mode C/B Output Mode DESCRIPTION Setting this bit to “1” initiates a software reset. It is automatically reset to a “0” after the reset sequence is complete. 0 = Normal operation 1 = Power down mode 0 = Enabled 1 = Disabled 0 = Caption_21A and Caption_21B data registers contain unused data 1 = Data has been output, host processor may now write to the registers 0 = Caption_284A and Caption_284B data registers contain unused data 1 = Data has been output, host processor may now write to the registers 0 = Enabled 1 = Disabled 0 = Enabled 1 = Disabled 0 = Enabled 1 = Disabled RESET STATE 0B 0B 0B 1B 3 1B 2 1 0 0B 0B 0B 20 4343.4 November 4, 2005 HMP8154, HMP8156A TABLE 19. CLOSED CAPTION_21A DATA REGISTER SUB ADDRESS = 10H BIT NUMBER 7-0 FUNCTION Line 21 Caption Data (First Byte) DESCRIPTION This register is cascaded with the closed caption_21B data register and they are read out serially as 16 bits during line 18, 21, or 22 if line 21 captioning is enabled. Bit D0 of the 21A data register is shifted out first. TABLE 20. CLOSED CAPTION_21B DATA REGISTER SUB ADDRESS = 11H BIT NUMBER 7-0 FUNCTION Line 21 Caption Data (Second Byte) DESCRIPTION This register is cascaded with the closed caption_21A data register and they are read out serially as 16 bits during line 18, 21, or 22 if line 21 captioning is enabled. Bit D0 of the 21A data register is shifted out first. TABLE 21. CLOSED CAPTION_284A DATA REGISTER SUB ADDRESS = 12H BIT NUMBER 7-0 FUNCTION Line 284 Caption Data (First Byte) DESCRIPTION This register is cascaded with the closed caption_284B data register and they are read out serially as 16 bits during line 281, 284, or 335 if line 284 captioning is enabled. Bit D0 of the 284A data register is shifted out first. TABLE 22. CLOSED CAPTION_284B DATA REGISTER SUB ADDRESS = 13H BIT NUMBER 7-0 FUNCTION Line 284 Caption Data (Second Byte) DESCRIPTION This register is cascaded with the closed caption_284A data register and they are read out serially as 16 bits during line 281, 284, or 335 if line 284 captioning is enabled. Bit D0 of the 284A data register is shifted out first. TABLE 23. START H_BLANK LOW REGISTER SUB ADDRESS = 20H BIT NUMBER 7-0 FUNCTION Assert BLANK Output Signal (Horizontal) DESCRIPTION This 8-bit register is cascaded with Start H_Blank High Register to form a 10-bit start_horizontal_blank register. It specifies the horizontal count (in 1X clock cycles) at which to start ignoring pixel data each scan line. The leading edge of HSYNC is count 020H. This register is ignored unless BLANK is configured as an output. TABLE 24. START H_BLANK HIGH REGISTER SUB ADDRESS = 21H BIT NUMBER 7-2 1-0 FUNCTION Reserved Assert BLANK Output Signal (Horizontal) This 2-bit register is cascaded with Start H_Blank Low Register to form a 10-bit start_horizontal_blank register. It specifies the horizontal count (in 1x clock cycles) at which to start ignoring pixel data each scan line. The leading edge of HSYNC is count 020H. This register is ignored unless BLANK is configured as an output. DESCRIPTION RESET STATE 000000B 11B RESET STATE 4AH RESET STATE 80H RESET STATE 80H RESET STATE 80H RESET STATE 80H 21 4343.4 November 4, 2005 HMP8154, HMP8156A TABLE 25. END H_BLANK REGISTER SUB ADDRESS = 22H BIT NUMBER 7-0 FUNCTION Negate BLANK Output Signal (Horizontal) DESCRIPTION This 8-bit register specifies the horizontal count (in 1X clock cycles) at which to start inputting pixel data each scan line. The leading edge of HSYNC is count 000H. This register is ignored unless BLANK is configured as an output. RESET STATE 7AH TABLE 26. START V_BLANK LOW REGISTER SUB ADDRESS = 23H BIT NUMBER 7-0 FUNCTION Assert BLANK Output Signal (Vertical) DESCRIPTION This 8-bit register is cascaded with Start V_Blank High Register to form a 9-bit start_vertical_blank register. During normal operation, it specifies the line number (n) to start ignoring pixel input data (and what line number to start blanking the output video) each odd field; for even fields, it occurs on line (n + 262) or (n + 313). During SIF input mode, the register value (n) specifies the line number to start ignoring pixel input data each noninterlaced input frame. The output video will be blanked starting on line number (n) each odd field; for even fields, it occurs on line (n + 262) or (n + 313). The leading edge of VSYNC at the start of an odd field is count 000H (note that this does not follow standard NTSC or PAL line numbering). This register is ignored unless BLANK is configured as an output. RESET STATE 03H TABLE 27. START V_BLANK HIGH REGISTER SUB ADDRESS = 24H BIT NUMBER 7-1 0 FUNCTION Reserved Assert BLANK Output Signal (Vertical) This 1-bit register is cascaded with Start V_Blank Low Register to form a 9-bit start_vertical_blank register. This register is ignored unless BLANK is configured as an output. DESCRIPTION RESET STATE 0000000B 1B TABLE 28. END V_BLANK REGISTER SUB ADDRESS = 25H BIT NUMBER 7-0 FUNCTION Negate BLANK Output Signal (Vertical) DESCRIPTION During normal operation, this 8-bit register specifies the line number (n) to start inputting pixel input data (and what line number to start generating active output video) each odd field; for even fields, it occurs on line (n + 262) or (n + 313). During SIF input mode, the register value (n) specifies the line number to start inputting pixel input data each noninterlaced input frame. The output video will be active starting on line number (n) each odd field; for even fields, it occurs on line (n + 262) or (n + 313). The leading edge of VSYNC at the start of an odd field is count 000H (note that this does not follow standard NTSC or PAL line numbering). This register is ignored unless BLANK is configured as an output. RESET STATE 13H 22 4343.4 November 4, 2005 HMP8154, HMP8156A TABLE 29. FIELD CONTROL REGISTER 1 SUB ADDRESS = 26H BIT NUMBER 7-0 FUNCTION Field Detect Window Size Low DESCRIPTION This 8-bit register is cascaded with Field Detect Window Size High to form a 9-bit Field Detect Window Size value. The value specifies the number of 1X clock cycles in the detection window before and after the selected edge of VSYNC. It may range from 0 to 511. If the leading edge of HSYNC occurs within the window, it is the start of an odd or even field, as specified by the FIELD Detect Select bit. This register is ignored unless HSYNC and VSYNC are configured as inputs. RESET STATE 80H TABLE 30. FIELD CONTROL REGISTER 2 SUB ADDRESS = 27H BIT NUMBER 7-4 2 FUNCTION Half Line Count Reset Value VSYNC Edge Select DESCRIPTION These bits specify the value to load to the vertical half line counter when the selected edge of VSYNC. The value is ignored when HSYNC and VSYNC are configured as outputs. This bit specifies whether the encoder uses the leading or trailing edge of VSYNC to determine the field and to reset the half line counter. It is ignored unless HSYNC and VSYNC are configured as inputs. 0 = leading edge 1 = trailing edge This bit specifies whether an odd or even field is starting when the leading edge of HSYNC occurs within the FIELD Detect Window. It is ignored unless HSYNC and VSYNC are configured as inputs. 0 = odd field 1 = even field This bit is cascaded with Field Detect Window Size Low to form a 9-bit Field Detect Window Size value. This bit is ignored unless HSYNC and VSYNC are configured as inputs. RESET STATE 00000B 0B 1 FIELD Detect Select 0B 0 Field Detect Window Size High 0B 23 4343.4 November 4, 2005 HMP8154, HMP8156A Pinout HMP8154/HMP8156A (PQFP) TOP VIEW COMP 1 COMP 2 FS_ADJUST VREF GND GND P0 VAA GND P1 P2 VAA VAA Y/G GND VAA GND C/B GND VAA GND NTSC/PAL1 GND VAA GND NTSC/PAL2 GND 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GND SCL SA SDA RESV P23 P22 VAA RESET GND P21 M1/P20 M0/P19 OL2/P18 OL1/P17 OL0/P16 P8 P9 P10 P11 P12 P13 GND CLK2 VAA CLK P14 P15 VSYNC HSYNC FIELD BLANK Pin Descriptions PIN NAME P0-P15 PIN NUMBER 58, 55-43, 38, 37 32-27, 23, 22 21 34 INPUT/ OUTPUT I DESCRIPTION Pixel input pins. See Table 1. Any pixel inputs not used should be connected to GND. P16-P23 RESV FIELD I I O Overlay or pixel inputs. See Table 1. Any overlay or pixel inputs not used should be connected to GND. This pin is reserved and should be connected to VCC or GND. FIELD output. The field output indicates that the encoder is outputting the odd or even video field. The polarity of FIELD is programmable. Horizontal sync input/output. As an input, this pin must be asserted during the horizontal sync intervals. If it occurs early, the line time will be shortened. If it occurs late, the line time will be lengthened by holding the outputs at the front porch level. As an output, it is asserted during the horizontal sync intervals. The polarity of HSYNC is programmable. If not driven, the circuit for this pin should include a 4-12kΩ pull up resistor connected to VAA. Vertical sync input/output. As an input, this pin must be asserted during the vertical sync intervals. If it occurs early, the field time will be shortened. If it occurs late, the field time will be lengthened by holding the outputs at the blanking level. As an output, it is asserted during the vertical sync intervals. The polarity of VSYNC is programmable. If not driven, the circuit for this pin should include a 4-12kΩ pull up resistor connected to VAA. Composite blanking input/output. As an input, this pin must be asserted during the horizontal and vertical blanking intervals. As an output, it is asserted during the horizontal and vertical blanking intervals. The polarity of BLANK is programmable. If not driven, the circuit for this pin should include a 4-12kΩ pull up resistor connected to VAA. HSYNC 35 I/O VSYNC 36 I/O BLANK 33 I/O 24 P3 P4 P5 P6 P7 4343.4 November 4, 2005 HMP8154, HMP8156A Pin Descriptions PIN NAME CLK (Continued) INPUT/ OUTPUT I/O PIN NUMBER 39 DESCRIPTION 1X pixel clock input/output. As an input, this clock must be free-running and synchronous to the clock signal on the CLK2 pin. As an output, this pin may drive a maximum of one LS TTL load. CLK is generated by dividing CLK2 by two or four, depending on the mode. If not driven, the circuit for this pin should include a 4-12kΩ pull up resistor connected to VAA. 2X pixel clock input. This clock must be a continuous, free-running clock. I2C interface clock input. The circuit for this pin should include a 4-6kΩ pull up resistor connected to VAA. I2C interface address select input. I2C interface data input/output. The circuit for this pin should include a 4-6kΩ pull-up resistor connected to VAA. Reset control input. A logical zero for a minimum of four CLK cycles resets the device. RESET must be a logical one for normal operation. Luminance analog current output. This output contains luminance video, sync, blanking, and closed captioning information. In analog RGB output mode, green or composite analog video is generated. It is capable of driving a 37.5Ω load. If not used, it should be connected to GND. Chrominance analog current output. This output contains chrominance video, and blanking information. In analog RGB output mode, blue or red analog video is generated. It is capable of driving a 37.5Ω load. If not used, it should be connected to GND. Composite video analog current output. This output contains composite video, sync, blanking, and closed captioning information. In analog RGB output mode, composite or green analog video is generated. It is capable of driving a 37.5Ω load. If not used, it should be connected to GND. Composite video analog current output. This output contains composite video, sync, blanking, and closed captioning information. In analog RGB output mode, red or blue analog video is generated. It is capable of driving a 37.5Ω load. If not used, it should be connected to GND. Voltage reference. An optional external 1.235V reference may be used to drive this pin. If left floating, the internal voltage reference is used. Full scale adjust control. A resistor (RSET) connected between this pin and GND sets the full-scale output current of each of the DACs. Compensation pin. A 0.1µF ceramic chip capacitor should be connected between this pin and VAA, as close to the device as possible. Compensation pin. Connection to this pin is optional. A 0.1µF ceramic chip capacitor may be connected between this pin and VAA. If used, the capacitor should be placed as close to the device as possible. +5V power. A 0.1µF ceramic capacitor, in parallel with a 0.01µF chip capacitor, should be used between each group of VAA pins and GND. These should be as close to the device as possible. Ground CLK2 SCL 41 18 I I SA SDA 19 20 I I/O RESET 25 I Y (G) 3 O C (B) 7 O NTSC/PAL 1 11 O NTSC/PAL 2 (R) 15 O VREF 61 I/O FS_ADJUST 62 COMP 1 64 COMP 2 63 VAA GND 25 4343.4 November 4, 2005 HMP8154, HMP8156A Absolute Maximum Ratings VAA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6V All Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6V Thermal Information Thermal Resistance (Typical, Note 3) θJA oC/W PQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Vapor Phase Soldering, 1 Minute . . . . . . . . . . . . . . . . . . . . . .220oC (PQFP - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. NOTE: 3. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER VAA = +5V ±5%, RSET = 133Ω, VREF Unconnected, TA = 25oC, Unless Otherwise Specified TEST CONDITION MIN TYP MAX UNITS DC PARAMETERS, DIGITAL INPUTS EXCEPT CLK2, SDA, SCL Input Logic Low Voltage, VIL Input Logic High Voltage, VIH Input Logic Low Current, IIL Input Logic High Current, IIH Input Capacitance, CIN DC PARAMETERS, CLK2 INPUT Input Logic Low Voltage, VIL Input Logic High Voltage, VIH Input Logic Low Current, IIL Input Logic High Current, IIH Input Capacitance, CIN DC PARAMETERS, SDA AND SCL INPUTS Input Logic Low Voltage, VIL Input Logic High Voltage, VIH Input Logic Low Current, IIL Input Logic High Current, IIH Input Capacitance, CIN DC PARAMETERS, DIGITAL OUTPUTS (Except SDA) Output Logic Low Voltage, VOL Output Logic High Voltage, VOH Output Capacitance, COUT DC PARAMETERS, SDA OUTPUTS Output Logic Low Voltage, VOL DC PARAMETERS, ANALOG OUTPUTS DAC Resolution Integral Nonlinearity, INL Differential Nonlinearity, DNL Output Current Output Impedance IOUT = 0mA IOUT = 34mA Output Capacitance IOUT = 0mA, CLK = 13.5MHz 10 10 ±0.5 ±0.2 2M 300K 25 10 ±2.0 ±1.0 34.8 Bits LSB LSB mA Ω Ω pF IOL = 3mA 0.4 V IOL = 2mA IOH = -2mA 2.4 8 0.4 V V pF VIN = 0V VIN = VAA 0.7 x VAA 8 0.3 x VAA -10 10 V V µA µA pF VIN = 0V VIN = VAA 0.7 x VAA 8 0.3 x VAA -10 10 V V µA µA pF VIN = 0V VIN = VAA 2.0 8 0.8 -10 10 V V µA µA pF 26 4343.4 November 4, 2005 HMP8154, HMP8156A Electrical Specifications PARAMETER Output Compliance Range Video Level Error Internal Voltage Reference External Voltage Reference DAC to DAC Matching VREF Output Voltage VREF Output Current VREF Input Voltage VREF Input Current AC PARAMETERS, ANALOG OUTPUTS Differential Gain Error Differential Phase Error SNR (Weighted) Hue Accuracy Color Saturation Accuracy Luminance Nonlinearity Residual Subcarrier SCH Phase Analog Output Skew, TASK Analog Output Delay, TAD DAC-DAC Crosstalk Glitch Energy Using analog output filter shown in Figure 38A. Includes clock and data feedthrough SCH Phase Reset enabled Using analog output filter shown in Figure 38A. 1 1 70 2 2 1 -60 ±1.5 -60 35 3 12 % Degree dB Degree % % dB Degree ns ns dB pV-s Pin connected to external reference shown in Figure 37. Pin not driven, using internal reference (Note 4) VREF unconnected, RSET = 133Ω VREF = 1.230V (Figure 37), RSET = 140Ω 1.13 -50 1.112 -500 1.195 1.230 ±10 ±10 5 1.32 50 1.358 500 % % % V µA V µA VAA = +5V ±5%, RSET = 133Ω, VREF Unconnected, TA = 25oC, Unless Otherwise Specified (Continued) TEST CONDITION MIN 0 TYP MAX 1.4 UNITS V AC PARAMETERS, DIGITAL INPUTS AND OUTPUTS EXCEPT SCL AND SDA Setup Time, TS Hold Time, TH CLK2 Frequency CLK2 High Time, CLK2H CLK2 Low Time, CLK2L CLK2 to Output Delay, TD RESET* Pulse Width Low, TRES AC PARAMETERS, SCL AND SDA (I2C INTERFACE) All AC parameters meet the fast-mode I2C Bus Interface specification. POWER SUPPLY CHARACTERISTICS DAC PSRR at DC Power Supply Range, VAA Normal Supply Current, IAA Power-Down Supply Current, IAA Power Dissipation NOTES: 4. Output level is dependent on the voltage on VREF, the value of RSET, and the load. 5. If using an external voltage reference, it is not powered down. The internal voltage reference is always powered down. 6. The supply voltage rejection is the relative variation of the full-scale output driving a 37.5Ω load for a ±0.5% supply variation: PSRR = 20 x log (∆VAA / ∆VOUT). Note 5 Note 6 4.75 64 5.0 1100 5.25 260 750 1300 dB V mA µA mW 8 0 13.6 13.6 2 4 30.0 20.3 20.3 12 ns ns MHz ns ns ns CLK Cycles 27 4343.4 November 4, 2005 HMP8154, HMP8156A Typical Performance Curves 0.0 -5.0 -10.0 -15.0 -20.0 -25.0 -30.0 -35.0 -40.0 -45.0 -50.0 -55.0 -60.0 -65.0 -70.0 -75.0 -80.0 -85.0 -90.0 -95.0 -100.0 FIELD = 1 LINE = 47 AMPLITUDE (0dB = 714mVP-P) BANDWIDTH 10kHz TO FULL Wfm ---> PEDESTAL NOISE LEVEL = -79.9dB RMS APL = 44.3% SYSTEM LINE L 47 F1 ANGLE (DEG) 0.0 GAIN x1.000 0.000dB 525 LINE NTSC BURST FROM SOURCE 1.0 AVERAGE 2.0 3.0 (MHz) 4.0 5.0 SETUP 7.5% FIGURE 22. NOISE SPECTRUM (NTSC) FIGURE 23. NTSC COLOR BAR VECTOR SCOPE FIGURE 24. NTSC FCC COLOR BAR 28 4343.4 November 4, 2005 HMP8154, HMP8156A Typical Performance Curves 105.0 104.5 104.0 103.5 103.0 102.5 102.0 101.5 101.0 100.5 100.0 99.5 99.0 98.5 98.0 97.5 97.0 96.5 96.0 95.5 95.0 FIELD = 1 LINE = 47 LUMINANCE NON LINEARITY (%) (Continued) wfm ---> 5 STEP PEAK-TO-PEAK = 2.1 LINE FREQUENCY ERROR 100.0 99.1 97.9 -0.4 -0.2 99.1 99.8 0.00 (%) 0.0 (%) 0.2 0.4 LINE FREQUENCY 15.734 (kHz) FIELD FREQUENCY 59.94 (Hz) 1ST AVERAGE 2ND 3RD 4TH 5TH AVERAGE OFF FIGURE 25. LUMINANCE NON LINEARITY (NTSC) LINE JITTER (LINE 20 TO 250) 2nsP-P FIGURE 26. LINE FREQUENCY (NTSC) 525 LINE NTSC MEAN SCH 0.8 DEGREES AVERAGE FIGURE 27. H SYNC JITTER IN A FRAME (NTSC) FIGURE 28. SCH PHASE MEASUREMENT (NTSC) APL = 40.0% SYSTEM LINE L 72 ANGLE (DEG) 0.0 GAIN x1.000 0.000dB 625 LINE PAL BURST FROM SOURCE DISPLAY +V AND -V AVERAGE FIGURE 29. NOISE SPECTRUM (PAL) FIGURE 30. PAL COLOR BAR VECTOR SCOPE 29 4343.4 November 4, 2005 HMP8154, HMP8156A Typical Performance Curves LINE = 72 (Continued) Wfm ---> COLOR BAR FIGURE 31. COLORBAR (PAL) 105.0 104.5 104.0 103.5 103.0 102.5 102.0 101.5 101.0 100.5 100.0 99.5 99.0 98.5 98.0 97.5 97.0 96.5 96.0 95.5 95.0 LINE = 72 LUMINANCE NON LINEARITY (%) wfm ---> 5 STEP PEAK-TO-PEAK = 1.4 LINE FREQUENCY ERROR 0.00 (%) 100.0 97.9 99.1 99.1 99.8 -0.4 -0.2 0.0 (%) 0.2 0.4 LINE FREQUENCY 15.625 (kHz) FIELD FREQUENCY 50.00 (Hz) AVERAGE OFF 1ST AVERAGE 2ND 3RD 4TH 5TH FIGURE 32. LUMINANCE NON LINEARITY (PAL) FIGURE 33. LINE FREQUENCY (PAL) 30 4343.4 November 4, 2005 HMP8154, HMP8156A Typical Performance Curves (Continued) FIGURE 34. H SYNC JITTER IN A FRAME (PAL) FIGURE 35. SCH PHASE MEASUREMENT (PAL) Application Information Vertical Blanking Information Encoding VBI data such as teletext may be encoded on any line by driving the pixel inputs with appropriate data. For YCbCr input modes, Cb and Cr should equal 128 to disable the color information. For RGB input modes, R, G, and B should always have the same value to disable the color information. Vertical blanking must be negated on the first scan line containing VBI information. If there are unused scan lines between the VBI data and active video, BLANK must remain on and the pixel inputs should be set to the black level. Traces containing digital signals should not be routed over, under, or adjacent to the analog output traces to minimize crosstalk. If this is not possible, coupling can be minimized by routing the digital signals at a 90 degree angle to the analog signals. The analog output traces should also not cross over or under the VCC power plane to maximize high-frequency power supply rejection. Power and Ground Planes A common ground plane for all devices, including the HMP8154/HMP8156A, is recommended. However, placing the encoder on an electrically connected GND peninsula reduces noise levels. All GND pins on the HMP8154/HMP8156A must be connected to the ground plane. Typical power and ground planes are shown in Figure 36. The small connection between the ground areas should be made wide enough so that most of the encoders digital inputs can be routed over or under it. It is especially important that the CLK and CLK2 signals cross through the connection. The HMP8154/HMP8156A should have its own power plane that is isolated from the common power plane of the board, with a gap between the two power planes of at least 1/8 inch. All VAA pins of the HMP8154/HMP8156A must be connected to this isolated power plane. The HMP8154/HMP8156A power plane should be connected to the board’s normal VCC power plane at a single point though a low-resistance ferrite bead, such as a Ferroxcube 56590653B, Fair-Rite 2743001111, or TDK BF45-4001. The ferrite bead provides resistance to switching currents, improving the performance of HMP8154/HMP8156A. A single, large capacitor should also be used between the HMP8154/HMP8156A power plane and the ground plane to control low-frequency power supply ripple. Video Insertion Test Signalsy Video test signals may be generated by driving the pixel inputs with appropriate data. Most of the video test signals require using YCbCr pixel data. Vertical blanking must be negated on the first scan line containing video test signals. If there are unused scan lines between test signal data and active video, BLANK must remain off and the pixel inputs should be set to the black level. PCB Considerations A PCB board with a minimum of 4 layers is recommended, with layers 1 and 4 (top and bottom) for signals and layers 2 and 3 for power and ground. The PCB layout should implement the lowest possible noise on the power and ground planes by providing excellent decoupling. PCB trace lengths between groups of VAA and GND pins should be as short as possible. Component Placement The optimum layout places the HMP8154/HMP8156A at the edge of the PCB and as close as possible to the video output connector. External components should be positioned as close as possible to the appropriate pin, ideally such that traces can be connected point to point. Chip capacitors are recommended where possible, with radial lead ceramic capacitors the second-best choice. 31 4343.4 November 4, 2005 HMP8154, HMP8156A FERRITE BEAD BULK AREA CAPACITOR VCC 8154/8156A LP FILTERS ANALOG CONN. VAA PCB FIGURE 36A. VCC AND VAA PLANES GND 8154/8156A LP FILTERS ANALOG CONN. PCB FIGURE 36B. COMMON GROUND PLANE FIGURE 36. EXAMPLE POWER AND GROUND PLANES For proper operation, power supply decoupling is required. It should be done using a 0.1µF ceramic capacitor in parallel with a 0.01µF chip capacitor for each group of VAA pins to ground. These capacitors should be located as close to the VAA and GND pins as possible, using short, wide traces. If a separate linear regulator is used to provide power to the HMP8154/HMP8156A power plane, the power-up sequence should be designed to ensure latchup will not occur. A separate linear regulator is recommended if the power supply noise on 32 the VAA pins exceeds 200mV. About 10% of the noise (that is less than 1MHz) on the VAA pins will couple onto the analog outputs. External Reference Voltage If an external reference voltage is used, its circuitry should receive power from the same plane as the HMP8154/ HMP8156A. The external VREF must also be stable and well decoupled from the power plane. An example VREF circuit using a band gap reference diode is shown in Figure 37. 4343.4 November 4, 2005 HMP8154, HMP8156A VAA 6.8K 1.235V ICL8069 + 4.7µF 0.01µF Analog Output Filters The various video standards specify the frequency response of the video signal. The HMP8154/HMP8156A uses 2X oversampling DACs to simplify the reconstruction filter required. Example post filters are shown in Figure 38. The analog output filters should be as close as possible to the HMP8154/HMP8156A. FIGURE 37. EXTERNAL REFERENCE VOLTAGE CIRCUIT 1.0µH 2.2µH 1.0µH 75 82pF 330pF 330pF 39pF RL 75 FIGURE 38A. HIGH QUALITY FILTER 2.7µH 75 560pF 560pF RL 75 FIGURE 38B. LOW COST FILTER FIGURE 38. EXAMPLE POST-FILTER CIRCUITS Evaluation Kits The HMP8154EVAL1 is a small (index card size) printed circuit board containing the encoder, voltage references and bypassing, analog output filters, and input/output connectors. The board allows the encoder’s operation and performance to be observed and measured. The HMP8154EVAL1 board has a 50 pin, two row receptacle which allows connection into an existing system. The connector provides access to all of the encoder’s digital inputs and outputs. The HMP8156EVAL2 is the Intersil designed mother board for the HMP8154EVAL1. The mother board is a standard size PC add in card with an ISA bus interface and application software. The HMP8156EVAL2 kit is a complete system which allows demonstrating all of both encoders’ operating modes. It has analog video inputs for composite, S-video, and component RGB signals. The analog signals are converted/decoded to the digital domain and input to the encoder. The board also provides a 3 megabyte video RAM for image capture and display and a BT.656 connector and interface. For simpler operation, the HMP8154EVAL1 may also be driven by external power supplies, a BT.656 signal generator, and a PC parallel port. The evaluation kit includes application software to program the part using its I2C bus connected to the printer port. The board includes the standard 25 pin BT.656 connector and interface. 33 4343.4 November 4, 2005 HMP8154, HMP8156A Metric Plastic Quad Flatpack Packages (MQFP) D D1 -D- Q64.14x14 (JEDEC MS-022BE ISSUE B) 64 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE INCHES SYMBOL A A1 A2 MIN 0.004 0.100 0.012 0.012 0.672 0.546 0.673 0.547 0.029 64 0.032 BSC MAX 0.124 0.010 0.108 0.018 0.016 0.682 0.556 0.681 0.555 0.040 MILLIMETERS MIN 0.10 2.55 0.30 0.30 17.08 13.88 17.10 13.90 0.73 64 0.80 BSC MAX 3.15 0.25 2.75 0.45 0.40 17.32 14.12 17.30 14.10 1.03 NOTES 6 3 4, 5 3 4, 5 7 Rev. 1 4/99 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- . 4. Dimensions D1 and E1 to be determined at datum plane -H- . 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. “N” is the number of terminal positions. 0.13/0.23 0.005/0.009 -AE E1 -B- b b1 D D1 E e PIN 1 SEATING A PLANE 0.076 0.003 12o-16o 0.40 0.016 MIN 0o MIN 0o-7o A2 A1 0.20 M 0.008 C A-B S -CDS b b1 0.13/0.17 0.005/0.007 BASE METAL WITH PLATING E1 L N e -H- L 12o-16o All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 34 4343.4 November 4, 2005