HMPVIDEVALISA

HMP8115 April 1998 NTSC/PAL Video Decoder Description The HMP8115 is a high quality NTSC and PAL decoder with internal A/D converters. It is compatible with NTSC M, PAL B, D, G, H, I, M, N, and combination N (NC) video standards. Both composite and S-video (Y/C) input formats are supported. A 2-line comb filter plus a user-selectable chrominance trap filter provide high quality Y/C separation. User adjustments include brightness, contrast, saturation, hue, and sharpness. Data during the vertical blanking interval (VBI), such as closed captioning, widescreen signalling and teletext, may be captured and output as BT.656 ancillary data. Closed captioning and widescreen signalling information may also be read out via the I2C interface. Features • (M) NTSC and (B, D, G, H, I, M, N, NC) PAL Operation - Optional Auto Detect of Video Standard - ITU-R BT.601 (CCIR601) and Square Pixel Operation • Digital Output Formats - VMI Compatible - 8-Bit, 16-Bit 4:2:2 YCbCr - 15-Bit (5,5,5), 16-Bit (5,6,5) RGB - Linear or Gamma-Corrected - 8-Bit BT.656 • Analog Input Formats - Three Analog Composite Inputs - Analog Y/C (S-Video) Input • “Sliced” VBI Data Capture Capabilities - Closed Captioning - Widescreen Signalling (WSS) - BT.653 System B, C and D Teletext - NABTS (North American Broadcast Teletext) - WST (World System Teletext) • 2-Line (1H) Comb Filter Y/C Separator • Fast I2C Interface • Two 8-Bit ADCs Ordering Information PART NUMBER HMP8115CN HMPVIDEVAL/ISA NOTES: 1. PQFP is also known as QFP and MQFP. 2. Evaluation Board and Reference Design descriptions are in the Applications section. TEMP. RANGE (oC) 0 to 70 PACKAGE 80 Ld PQFP PKG. NO. Q80.14x20 Evaluation Board: ISA Frame Grabber Applications • Multimedia PCs • Video Conferencing • Video Compression Systems • Video Security Systems • LCD Projectors and Overhead Panels • Related Products - NTSC/PAL Encoders: HMP815x, HMP817x - NTSC/PAL Decoders: HMP8112A • Related Literature - AN9644: Composite Video Separation Techniques - AN9716: Widescreen Signalling - AN9717: YCbCr to RGB Considerations - AN9728: BT.656 Video Interface for ICs - AN9738: VMI Video Interface for ICs CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 File Number 4283.5 1 HMP8115 Table of Contents PAGE Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Video Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ANALOG VIDEO INPUTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ANTI-ALIASING FILTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S-VIDEO CHROMA GAIN CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digitization of Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A/D CONVERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGC AND DC RESTORATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INPUT SIGNAL DETECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VERTICAL SYNC AND FIELD DETECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Y/C SEPARATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INPUT SAMPLE RATE CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COMB FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CHROMA DEMODULATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OUTPUT SAMPLE RATE CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLK2 INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Processing of Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UV TO CbCr CONVERSION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIGITAL COLOR GAIN CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COLOR KILLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Y PROCESSING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CbCr PROCESSING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . YCbCr OUTPUT FORMAT PROCESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RGB OUTPUT FORMAT PROCESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUILT-IN VIDEO GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pixel Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HSYNC AND VSYNC TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIELD TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BLANK AND DVALID TIMING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PIXEL OUTPUT PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-BIT YCbCr OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-BIT YCbCr, 15-BIT RGB, OR 16-RGB OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-BIT BT.656 OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLOSED CAPTIONING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WIDESCREEN SIGNALLING (WSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BT.656 ANCILLARY DATA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BT.656 CLOSED CAPTIONING AND WIDE SCREEN SIGNALLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TELETEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REAL TIME CONTROL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HMP8115 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCB LAYOUT CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EVALUATION BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RELATED APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 7 7 7 7 7 7 8 8 8 9 9 9 9 10 11 11 12 14 15 15 16 17 17 18 20 21 22 35 36 38 38 38 38 40 2 Functional Block Diagram EXTERNAL ANTIALIASING FILTER VBI STATUS BITS YOUT + VBI DETECTION AND DECODING LOGIC 8-BIT ADC YIN NTSC-PAL1 NTSC-PAL2 INPUT MUX NTSC-PAL3/Y DIGITAL COMPARATORS WHITE PEAK LEVEL BLACK LEVEL Y/C SEPARATION COLOR TRAP SYNC LEVEL COLOR DEMODULATION L_CAP LAGC_CAP AGC AND CLAMP LOGIC USER ADJUST COLOR ADJUST OUTPUT SAMPLE RATE CONVERTER HMP8115 3 DIGITAL COMPARATOR CLAMP + 8-BIT ADC CHROMA PLL VSYNC DETECT SCL SDA MICROPROCESSOR INTERFACE AND CONTROL FIELD VSYNC RESET INTREQ GAIN_CTRL C_CAP CLAMP LOGIC AND GAIN CONTROL INPUT SAMPLE RATE CONVERTER USER ADJUST. EXTERNAL ANTIALIASING FILTER C HSYNC DETECT RGB LOGIC LINE LOCK PLL VBIVALID BLANK HSYNC LOCKED DVALID P[15:0] OUTPUT TIMING AND FIFO Functional Block Diagram (Continued) FIELD VSYNC GENLOCK LOSS CLK (24.54, 27.0 OR 29.5MHz) HUE ADJUST VSYNC DETECT 4FSC CLOCK CHROMA PLL NCO CHROMA PLL LOOP FILTER CHROMA PHASE DETECTOR HSYNC DETECT HSYNC CLK TO 4FSC RATIO AGC ADJUST SATURATION ADJUST CR[7:0] C M U X C,CVBS DATA C,CVBS DATA C DATA LINE DELAY COMB FILTER U,V U, V TO CbCr COLOR SPACE CONVERTER AND COLOR KILLER LP FILTER LINE LOCKED PLL LOOP FILTER LINE LOCKED NCO LOCKED CHROMA DEMODULATOR HMP8115 CbCr 4 Y,CVBS Y DATA VBI DETECTION AND DECODING LOGIC INPUT SAMPLE RATE CONVERTER ENABLE Y DATA HORIZONTAL M Y DATA AND VERTICAL Y DATA U SHARPNESS X ADJUST CHROMA TRAP OUTPUT SAMPLE RATE CONVERTER SYNC STRIPPER, BRIGHTNESS, AND CONTRAST ADJUST Y ENABLE SHARPNESS ADJUST M U X LP FILTER STANDARD SELECT RGB LOGIC MUX MUX ENABLE P[15:0] HSYNC,VSYNC, BLANK, FIELD, DVALID, VBIVALID OUTPUT TIMING AND FIFO HMP8115 Introduction The HMP8115 is designed to decode baseband composite or S-video NTSC and PAL signals, and convert them to either digital YCbCr or RGB data. In addition to performing the basic decoding operations, the HMP8115 includes hardware to decode different types of VBI data and to generate digital video patterns for a blue screen, black screen and full screen color bars. The digital PLLs are designed to synchronize to all NTSC and PAL standards. A chroma PLL is used to maintain chroma lock for demodulation of the color information; a linelocked PLL is used to maintain vertical spatial alignment. The PLLs are designed to maintain lock even in the event of VCR headswitches and multipath noise. The HMP8115 contains two 8-bit A/D converters and an I2C interface for programming internal registers. inside the decoder as determined by bits 7 and 6 of the COLOR PROCESSING register 06H. In addition to the internal AGC, the designer can also apply some gain to the chroma before it reaches the internal AGC logic. This gain is controlled by pin 28. The voltage at this pin determines the gain of the chroma before it gets digitized by the chroma A/D with a typical gain performance as shown in Figure 2. 7 6 5 LINEAR GAIN 4 3 2 TEMPERATURE = 25oC VCC = 5V External Video Processing Before a video signal can be digitized the decoder has some external processing considerations that need to be addressed. This section discusses those external aspects of the HMP8115. 1 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 CONTROL VOLTAGE ON THE GAIN_CTRL PIN ANALOG VIDEO INPUTS The HMP8115 supports either three composite or two composite and one S-video input. Three analog video inputs (NTSC/PAL 1-3) are used to select which one of three composite video sources are to be decoded. To support S-video applications, the Y channel drives the NTSC/PAL 3 analog input, and the C channel drives the C analog input. The analog inputs must be AC-coupled to the video signals, as shown in the Applications section. FIGURE 2. CHROMINANCE AMPLIFIER GAIN Digitization of Video Prior to A/D conversion, the video signal is DC restored and gained to generate known video levels into the digital processing logic. This process is addressed in the “AGC and DC Restoration” section. After digitization, sample rate converters and a comb filter are used to perform color separation and demodulation. A/D CONVERSION Video data is sampled at the CLK2 frequency then processed by the input sample rate converter. The output levels of the ADC after AGC processing are: (M) NTSC (M, N) PAL white black blank sync 224 76 64 0 (B, D, G, H, I, NC) PAL 213 64 64 0 ANTI-ALIASING FILTERS An external anti-alias filter is required to achieve optimum performance and prevent high frequency components from being aliased back into the video image. For the NTSC/PAL 1-3 inputs, a single filter is connected between the YOUT and YIN pins. For the C input, the antialiasing filter should be connected before the C input. A recommended filter is shown in Figure 1. R1 YOUT 332 C1 33pF L1 8.2µH C2 82pF YIN R2 4.02K AGC AND DC RESTORATION The AGC amplifier attenuates or amplifies the analog video signal to ensure that the sync tip level generates code 0. The difference from the ideal sync tip level of 0 is used to control the amount of attenuation or gain of the analog video signal. The capacitor on the LAGC_CAP pin is used to store the voltage which sets the gain level of the input video amplifier. DC restoration positions the video signal such that the DC level of the back porch generates an average code 64. The back porch is sampled to determine the average value. The capacitor on the L_CAP pin is used to store the voltage FIGURE 1. RECOMMENDED ANTI-ALIASING FILTER S-VIDEO CHROMA GAIN CONTROL The Chroma portion of S-video is AC coupled through an anti-aliasing filter as shown in the applications section. Unlike the composite/luma inputs, the Automatic Gain Control (AGC) for the chroma portion of S-video is done digitally 5 HMP8115 which sets the DC offset level into the input video amplifier. During the S-video mode of operation the capacitor on the C_CAP pin performs the same function as the L_CAP capacitor, except the chroma video amplifier’s DC offset is set so that the chroma A/D generates a code of 128 during the back porch. The internal timing windows for AGC and DC Restoration are show in Figure 3. Y/C SEPARATION A composite video signal has the luma (Y) and chroma (C) information mixed in the same video signal. The Y/C separation process is responsible for separating the composite video signal into these two components. The HMP8115 utilizes a comb filter to minimize the artifacts that are associated with the Y/C separation process. INPUT SAMPLE RATE CONVERTER The input sample rate converter is used to convert video data sampled at the CLK2 rate to a virtual 4xfSC sample rate for comb filtering and color demodulation. An interpolating filter is used to generate the 4xfSC samples as illustrated in Figure 4. INCOMING VIDEO SAMPLES DC RESTORE VIDEO INPUT TIME AGC RESAMPLED VIDEO FIGURE 3. AGC AND DC RESTORE INTERNAL TIMING TIME 4xfSC INPUT SIGNAL DETECTION It is assumed there is no video input if a horizontal sync is not detected for 16 consecutive lines. When no video has been detected, nominal video timing is generated for the previously detected or programmed standard. A maskable interrupt is included to flag when no video has been detected (bit 6 of the INTERRUPT MASK register 0FH) allowing for blue/black/color bar output modes to be enabled if desired. The vertical sync interrupt can be used in determining when a video signal is present at the currently selected video mux input. Bit 0 of register 0FH is used to enable vertical sync interrupts. FIGURE 4. SAMPLE RATE CONVERSION COMB FILTER A 2-line comb filter, using a single line delay, is used to perform part of the Y/C separation process. During S-video operation, the Y signal bypasses the comb filter; the C signal is processed by the comb filter since it is an integral part of the chroma demodulator. During PAL operation, the chroma trap filter should also be enabled for improved performance. Since a single line store is used, the chroma will normally have a half-line vertical offset from the luma data. This may be eliminated, vertically aligning the chroma and luma samples, at the expense of vertical resolution of the luma. Bit 0 of the OUTPUT FORMAT register 02H controls this option. VERTICAL SYNC AND FIELD DETECTION The vertical sync and field detect circuit uses a low time counter to detect the vertical sync sequence in the video data stream. The low time counter accumulates the low time encountered during any sync pulse, including serration and equalization pulses. When the low time count exceeds the vertical sync detect threshold, VSYNC is asserted immediately. FIELD is asserted at the same time that VSYNC is asserted. FIELD is asserted low for odd fields and high for even fields. Field is determined from the location in the video line where VSYNC is detected. If VSYNC is detected in the first half of the line, the field is odd. If VSYNC is detected in the second half of a line, the field is even. In the case of lost vertical sync or excessive noise that would prevent the detection of vertical sync, the FIELD output will continue to toggle. Lost vertical sync is declared if after 337 lines, a vertical sync period was not detected for 1 or 3 (selectable) successive fields as specified by bit 2 of the GENLOCK CONTROL register 04H. When this occurs, the PLLs are initialized to the acquisition state. CHROMA DEMODULATION The output of the comb filter is further processed using a patented frequency domain transform to complete the Y/C separation and demodulate the chromanance. Demodulation is done at a virtual 4xfSC sample rate using the interpolated data samples to generate U and V data. The demodulation process decimates by 2 the U/V sample rate. OUTPUT SAMPLE RATE CONVERTER The output sample rate converter converts the Y, U and V data from a virtual 4xfSC sample rate to the desired output sample rate (i.e., 13.5MHz). It also vertically aligns the samples based on the horizontal sync information embedded in the digital video data stream. The output sample rate is determined by the selected video standard and whether 6 HMP8115 square or rectangular pixels are output. The output format is 4:2:2 for all modes except the RGB modes which use a 4:4:4 output format. with the two previous lines having a color burst to limit lineto-line variations. A gain of 0.5x to 4x is used for Cb and Cr. If “fixed gain control” is selected, the amplitude of the color difference signals (CbCr) is multiplied by a constant, regardless of variations in the color burst amplitude. The constant gain value is specified by the COLOR GAIN register 1CH. A gain of 0.5x to 4x is used for Cb and Cr. Limiting the gain to 4x limits the amount of amplified noise. If “freeze automatic gain control” is selected, the amplitude of the color difference signals (CbCr) is multiplied by a constant. This constant is the value the AGC circuitry generated when the “freeze automatic gain” command was selected. CLK2 INPUT Note that the color subcarrier is derived from CLK2. Any jitter on CLK2 will be transferred to the color subcarrier, resulting in color changes. Thus, CLK2 should be derived from a stable clock source, such as a crystal. The use of a PLL to generate CLK2 is not recommended. CLK2 must have a 50ppm accuracy and at least a 60/40% duty cycle to ensure proper operation. The CLK2 clock rate must be one of the following frequencies: 24.54MHz 27.00MHz 29.50MHz The frequency of CLK2 must be 2x the desired output sample rate. The values in Table 1 below indicate the CLK2 clock rate based on the video standard and pixel mode. The output sample rate for the given video standard and pixel mode is half the CLK2 clock rate. TABLE 1. VIDEO STANDARD CLOCK RATE SELECTION SUMMARY ALLOWABLE CLK2 FREQUENCIES (MHz) VIDEO FORMAT (M) NTSC (B, D, G, H, I, N) PAL (M) PAL (NC) PAL RECTANGULAR PIXEL MODE 27.00 27.00 27.00 27.00 SQUARE PIXEL MODE 24.54 29.50 24.54 29.50 COLOR KILLER If “enable color killer” is selected, the color output is turned off when the running average of the color burst amplitude is below approximately 25% of nominal for four consecutive fields. When the running average of the color burst amplitude is above approximately 25% of nominal for four consecutive fields, the color output is turned on. The color output is also turned off when excessive phase error of the chroma PLL is present. If “force color off” is selected, color information is never present on the outputs. If “force color on” is selected, color information is present on the outputs regardless of the color burst amplitude or chroma PLL phase error. Y PROCESSING The black level is subtracted from the luminance data to remove sync and any blanking pedestal information. Negative values of Y are supported at this point to allow proper decoding of “below black” luminance levels. Scaling is done to position black at 8-bit code 0 and white at 8-bit code 219. A chroma trap filter may be used to remove any residual color subcarrier from the luminance data. The center frequency of the chroma trap is automatically determined from the video standard being decoded. The chroma trap should be disabled during S-video operation to maintain maximum luminance bandwidth. Alternately, a 3MHz lowpass filter may be used to remove high-frequency Y data. This may make a noisy image more pleasing to the user, although softer. Coring of the high-frequency Y data may be done to reduce low-level high frequency noise. Coring of the Y data may also be done to reduce low-level noise around black. This forces Y data with the following values to a value of 0: coring = 1: ± 1 coring = 2: ± 1, ± 2 coring = 3: ± 1, ± 2. ± 3 High-frequency components of the luminance signal may be “peaked” to control the sharpness of the image. Maximum gain may be selected to occur at either 2.6MHz or the color Digital Processing of Video Once the luma and chroma have been separated the HMP8115 then performs programmable modifications (i.e. contrast, coring, color space conversions, color AGC, etc.) to the decoded video signal. UV TO CbCr CONVERSION The baseband U and V signals are scaled and offset to generate a nominal range of 16-240 for both the Cb and Cr data. DIGITAL COLOR GAIN CONTROL There are four types of color gain control modes available: no gain control, automatic gain control, fixed gain control, and freeze automatic gain control. If “no gain control” is selected, the amplitude of the color difference signals (CbCr) is not modified, regardless of variations in the color burst amplitude. Thus, a gain of 1x is always used for Cb and Cr. If “automatic gain control” is selected, the amplitude of the color difference signals (CbCr) is compensated for variations in the color burst amplitude. The burst amplitude is averaged 7 HMP8115 subcarrier frequency. This may be used to make the displayed image more pleasing to the user. It should not be used if the output video will be compressed, as the circuit introduces high-frequency components that will reduce the compression ratio. The brightness control adds or subtracts a user-specified DC offset to the Y data. The contrast control multiplies the Y data by a user-specified amount. These may be used to make the displayed image more pleasing to the user. Finally, a value of 16 is added to generate a nominal range of 16 (black) to 235 (white). The 15-bit R′G′B′ data may be converted to 15-bit linear RGB, using the following equations. Although the PAL specifications specify a gamma of 2.8, a gamma of 2.2 is normally used. The HMP8115 allows the selection of the gamma to be either 2.2 or 2.8, independent of the video standard. for gamma = 2.2: for R′G′B′ < 0.0812*31 R = (31)((R′/31)/4.5) G = (31)((G′/31)/4.5) B = (31)((B′/31)/4.5) for R′G′B′ >= 0.0812*31 R = (31)(((R′/31) + 0.099)/1.099)2.2 G = (31)(((G′/31) + 0.099)/1.099)2.2 B = (31)(((B′/31) + 0.099)/1.099)2.2 for gamma = 2.8: R = (31)(R′/31)2.8 G = (31)(G′/31)2.8 B = (31)(B′/31)2.8 16-Bit R′G′B′ The following YCbCr to R′G′B′ equations are used to maintain the proper black and white levels: R′ = 0.142(Y - 16) + 0.194(Cr - 128) G′ = 0.288(Y - 16) - 0.201(Cr - 128) - 0.097(Cb - 128) B′ = 0.142(Y - 16) + 0.245(Cb - 128) The resulting 16-bit R′G′B′ data has a range of 0 to 31 for R′ and B′, and a range of 0 to 63 for G′. Values less than 0 are made 0; R′ and B′ values greater than 31 are made 31, G′ values greater than 63 are made 63. The 16-bit R′G′B′ data may be converted to 16-bit linear RGB, using the following equations. Although the PAL specifications specify a gamma of 2.8, a gamma of 2.2 is normally used. The HMP8115 allows the selection of the gamma to be either 2.2 or 2.8, independent of the video standard. for gamma = 2.2: CbCr PROCESSING The CbCr data is lowpass filtered to either 0.85 or 1.5MHz. Coring of the CbCr data may be done to reduce low-level noise around zero. This forces CbCr data with the following values to a value of 128. coring = 1: 127, 129 coring = 2: 126, 127, 129, 130 coring = 3: 125, 126, 127, 129, 130, 131 The saturation control multiplies the CbCr data by a userspecified amount. This may be used to make the displayed image more pleasing to the user. The CbCr data may also be optionally multiplied by the contrast value to avoid color shifts when changing contrast. The hue control provides a user-specified phase offset to the color subcarrier during decoding. This may be used to correct slight hue errors due to transmission. YCbCr OUTPUT FORMAT PROCESSING Y has a nominal range of 16 to 235. Cb and Cr have a nominal range of 16 to 240, with 128 corresponding to zero. Values less than 1 are made 1 and values greater than 254 are made 254. While BLANK is asserted, Y is forced to have a value of 16, with Cb and Cr forced to have a value of 128, unless VBI data is present. RGB OUTPUT FORMAT PROCESSING The 4:2:2 YCbCr data is converted to 4:4:4 YCbCr data and then converted to either 15-bit or 16-bit gamma-corrected RGB (R′G′B′) data. While BLANK is asserted, RGB data is forced to a value of 0. 15-Bit R′G′B′ The following YCbCr to R′G′B′ equations are used to maintain the proper black and white levels: R′ = 0.142(Y - 16) + 0.194(Cr - 128) G′ = 0.142(Y - 16) - 0.099(Cr - 128) - 0.048(Cb - 128) B′ = 0.142(Y - 16) + 0.245(Cb - 128) The resulting 15-bit R′G′B′ data has a range of 0 to 31. Values less than 0 are made 0 and values greater than 31 are made 31. for R′B′ < 0.0812*31, G′ < 0.0812*63 R = (31)((R′/31)/4.5) G = (63)((G′/63)/4.5) B = (31)((B′/31)/4.5) for R′B′ >= 0.0812*31, G′ >= 0.0812*63 R = (31)(((R′/31) + 0.099)/1.099)2.2 G = (63)(((G′/63) + 0.099)/1.099)2.2 B = (31)(((B′/31) + 0.099)/1.099)2.2 for gamma = 2.8: R = (31)(R′/31)2.8 G = (63)(G′/63)2.8 B = (31)(B′/31)2.8 8 HMP8115 BUILT-IN VIDEO GENERATION When the blue screen, black screen or color bar output is selected, a full-screen of blue, black or 75% colorbar output is generated using the currently selected output format. The type of screen to be generated is determined by bits 2 and 1 of the OUTPUT FORMAT register 02H. When built-in video generation is not desired, the bits need to be set for normal operation to pass decoded video. If a video source is input, it will be used to provide the video timing. If an input video source is not detected, internallygenerated video timing will be used. a fixed latency due to internal pipeline processing. The pulse width of the HSYNC is defined by the END HSYNC register 36H, where the trailing edge of HSYNC has a programmable delay of 0-510 CLK2 cycles from the leading edge. The leading edge of VSYNC is asserted approximately half way through the first serration pulse of each field. For an odd field, the trailing edge of VSYNC is 5±1 CLK2 cycles after the trailing edge of the HSYNC that follows the last equalization pulse. Refer to Figures 5 and 7. For an even field, the trailing edge of VSYNC is 5±1 CLK2 cycles leading the leading edge of the HSYNC that follows the last equalization pulse. Refer to Figures 6 and 8. Pixel Port Timing The the timing and format of the output data and control signals is presented in the following sections. FIELD TIMING When field information can be determined from the input video source, the FIELD output pin reflects the video source field state. When field information cannot be determined from the input video source, the FIELD output pin alternates its state at the beginning of each field. FIELD changes state 5±1 CLK2 cycles before the leading edge of VSYNC. HSYNC AND VSYNC TIMING The HSYNC and VSYNC output timing is VMI v1.4 compatible. Figures 5-8 illustrate the video timing. The leading edge of HSYNC is synchronous to the video input signal and has NTSC(M) LINE # PAL(M) LINE # VIDEO INPUT 524 521 525 522 1 523 2 524 3 525 4 1 5 2 6 3 7 4 8 5 9 6 10 7 HSYNC VSYNC FIELD ‘EVEN’ FIELD ‘ODD’ FIELD NOTE: 3. The trailing edge of VSYNC is 5±1 clocks after the trailing edge of HSYNC to be VMI compatible and to indicate a transition to an odd field. FIGURE 5. NTSC(M) AND PAL(M) HSYNC, VSYNC AND FIELD TIMING DURING AN EVEN TO ODD FIELD TRANSITION NTSC(M) LINE # PAL(M) LINE # VIDEO INPUT 262 259 263 260 264 261 265 262 266 263 267 264 268 265 269 266 270 267 271 268 272 269 273 270 HSYNC VSYNC FIELD ‘ODD’ FIELD ‘EVEN’ FIELD NOTE: 4. The trailing edge of VSYNC is 5±1 clocks after the leading edge of HSYNC to be VMI compatible and to indicate a transition to an even field. FIGURE 6. NTSC(M) AND PAL(M) HSYNC, VSYNC AND FIELD TIMING DURING AN ODD TO EVEN FIELD TRANSITION 9 HMP8115 LINE # VIDEO INPUT 621 622 623 624 625 1 2 3 4 5 6 7 HSYNC VSYNC FIELD ‘EVEN’ FIELD ‘ODD’ FIELD NOTE: 5. The trailing edge of VSYNC is 5±1 clocks after the trailing edge of HSYNC is to be VMI compatible and to indicate a transition to an odd field. FIGURE 7. PAL(B,D,G,H,I,N,NC) HSYNC, VSYNC AND FIELD TIMING DURING AN EVEN TO ODD FIELD TRANSITION LINE # VIDEO INPUT 309 310 311 312 313 314 315 316 317 318 319 320 HSYNC VSYNC FIELD ‘ODD’ FIELD ‘EVEN’ FIELD NOTE: 6. The trailing edge of VSYNC is 5±1 clocks after the leading edge of HSYNC to be VMI compatible and to indicate a transition to an even field. FIGURE 8. PAL(B,D,G,H,I,N,NC) HSYNC, VSYNC AND FIELD TIMING DURING AN ODD TO EVEN FIELD TRANSITION BLANK AND DVALID TIMING DVALID is asserted when P15-P0 contain valid data. The timing and behavior of DVALID is dependent on the output video format and the programmed values for bit 4 (DVLD_DCYC) and bit 5 (DVLD_LTC) of the GENLOCK CONTROL register 04H. Refer to the specific output video format sections that follow for the specific behavior for DVALID. BLANK is used to determine if the HMP8115 is generating active video data. BLANK should be used in conjunction with DVALID to capture digital data from the decoder. BLANK, DVALID and the video data are output after the internal pipeline latency and synchronous with the rising edge of CLK2. During active scan lines BLANK is negated when the horizontal pixel count matches the value in the END H_BLANK register 32H. A count of 00H corresponds to the 50% point of the leading edge of the sync tip after leaving the part. BLANK is asserted when the horizontal pixel count matches the value in the START H_BLANK register 31H/30H. Note that horizontally, BLANK is programmable with two pixel resolution. START V_BLANK register 34H/33H and END V_BLANK register 35H determine which scan lines are blanked for each field. During inactive scan lines, BLANK is asserted during the entire scan line. Half-line blanking of the output video cannot be done. Reference Figure 9 for active video timing and use Table 2 for typical blanking programming values. TABLE 2. TYPICAL VALUES FOR HBLANK AND VBLANK REGISTERS VIDEO STANDARD (MSB/LSB) RECTANGULAR PIXELS NTSC (M), PAL (M) PAL (B, D, G, H, I,N, NC) SQUARE PIXELS NTSC (M), PAL (M) PAL (B, D, G, H, I,N, NC) 640 768 780 944 779 (030BH) 943 (03AFH) 758 (02F6H) 922 (039AH) 118 (76H) 154 (9AH) 259 (0103H) 310 (0136H) 19 (13H) 22 (16H) 720 720 858 864 857 (0359H) 863 (035FH) 842 (034AH) 852 (0354H) 122 (7AH) 132 (84H) 259 (0103H) 310 (0136H) 19 (13H) 22 (16H) ACTIVE PIXELS/ LINE TOTAL PIXELS/ LINE LAST PIXEL COUNT START H_BLANK (31H/30H) END H_BLANK (32H) START V_BLANK (34H/33H) END V_BLANK (35H) 10 HMP8115 NTSC M PAL B, D, G, H, I, N, NC LINES 1 - 22 NOT ACTIVE LINES 1 - 22 NOT ACTIVE ODD FIELD SYNC AND BACK PORCH 240 ACTIVE LINES PER FIELD (LINES 23-262) VERTICAL BLANKING 480 ACTIVE LINES/FRAME (NTSC, PAL M) 288 ACTIVE LINES PER FIELD (LINES 23 - 310) LINES 263 - 284 NOT ACTIVE 240 ACTIVE LINES PER FIELD (LINES 285 - 524) LINE 525 NOT ACTIVE TOTAL PIXELS ACTIVE PIXELS FRONT PORCH EVEN FIELD LINES 311 - 335 NOT ACTIVE 288 ACTIVE LINES PER FIELD (LINES 336 - 623) LINES 624-625 NOT ACTIVE TOTAL PIXELS ACTIVE PIXELS 576 ACTIVE LINES/FRAME (PAL) NUMBER OF PIXELS RECTANGULAR (SQUARE) NTSC 858 (780) 720 (640) PAL 864 (944) 720 (768) NOTE: 7. The line numbering for PAL (M) followings NTSC (M) line count minus 3 per the video standards. FIGURE 9. TYPICAL ACTIVE VIDEO REGIONS TABLE 3. PIXEL OUTPUT FORMATS PIN NAME P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 8-BIT, 4:2:2, YCbCr 0 0 0 0 0 0 0 0 Y0, Cb0, Cr0 Y1, Cb1, Cr1 Y2, Cb2, Cr2 Y3, Cb3, Cr3 Y4, Cb4, Cr4 Y5, Cb5, Cr5 Y6, Cb6, Cr6 Y7, Cb7, Cr7 16-BIT, 4:2:2, YCbCr Cb0, Cr0 Cb1, Cr1 Cb2, Cr2 Cb3, Cr3 Cb4, Cr4 Cb5, Cr5 Cb6, Cr6 Cb7, Cr7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 15-BIT, RGB, (5,5,5) B0 B1 B2 B3 B4 G0 G1 G2 G3 G4 R0 R1 R2 R3 R4 0 16-BIT, RGB, (5,6,5) B0 B1 B2 B3 B4 G0 G1 G2 G3 G4 G5 R0 R1 R2 R3 R4 BT.656 0 0 0 0 0 0 0 0 YCbCr Data, Ancillary Data, SAV and EAV Sequences PIXEL OUTPUT PORT Pixel data is output via the P0-P15 pins. Refer to Table 3 for the output pin definition as a function of the output mode. 8-BIT YCbCr OUTPUT The DVALID output pin may be configured to operate in one of two ways. The configuration is determined by the DVLD_LTC bit (bit 4) of the GENLOCK CONTROL register 04H. If DVLD_LTC=0, the DVALID output is continuously asserted during the entire active video time on active scan lines if CLK2 is exactly 2x the desired output sample rate. DVALID being asserted indicates valid pixel data is present on the P15-P8 pixel outputs. DVALID is never asserted during the blanking intervals. Refer to Figure 10. If DLVD_LTC=1, DVALID has the same internal timing as the first mode, but is ANDed with the CLK2 signal, and the result is output onto the DVALID pin. This results in a gated CLK2 signal being output during the active video time on active scan lines. Refer to Figure 11. If 8-bit YCbCr data is generated, it is output following each rising edge of CLK2. The YCbCr data is multiplexed as [Cb Y Cr Y′ Cb Y Cr Y′...], with the first active data each scan line containing Cb data. The pixel output timing is shown in Figures 10 and 11. BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD are output following the rising edge of CLK2. When BLANK is asserted and VBIVALID is deasserted, the YCbCr outputs have a value of 16 for Y and 128 for Cb and Cr. 11 HMP8115 CLK DVALID BLANK P[15-8] Cb0 tDVLD Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Cb4 Y4 NOTE: 8. Y0 is the first active luminance pixel data of a line. Cb0 and Cr0 are first active chrominance pixel data in a line. Cb and Cr will alternate every cycle due to the 4:2:2 subsampling. Pixel data is not output during the blanking period, but the values on the ports are forced to blanking levels. FIGURE 10. OUTPUT TIMING FOR 8-BIT YCbCr MODE (DVLD_LTC = 0) CLK DVALID BLANK P[15-8] Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Cb4 Y4 NOTES: tDVLD 9. Y0 is the first active luminance pixel data of a line. Cb0 and Cr0 are first active chrominance pixel data in a line. Cb and Cr will alternate every cycle due to the 4:2:2 subsampling. Pixel data is not output during the blanking period, but the values on the ports are forced to blanking levels. 10. When DVLD_LTC is set to 1, the polarity of DVALID needs to be set to active low, otherwise DVALID will stay low during active video and be gated with the clock only during the blanking interval. FIGURE 11. OUTPUT TIMING FOR 8-BIT YCbCr MODE (DVLD_LTC = 1) 16-BIT YCbCr, 15-BIT RGB, OR 16-RGB OUTPUT In these output modes, DVALID may be configured to operate in one of four modes as controlled by the DVLD_LTC and DVLD_DCYC bits of the GENLOCK CONTROL register (04H). Bit 4 is the DVLD_LTC bit and bit 5 is the DVLD_DCYC bit. If DVLD_LTC=0 and DVLD_DCYC=0, DVALID is present only during the active video time on active scan lines. Thus, DVALID being asserted indicates valid pixel data is present on the P0-P15 pixel outputs. DVALID is never asserted during the blanking intervals. In this mode DVALID will have a 50% duty cycle only during the active video times. The timing diagrams for this mode can be found in Figures 12 and 13. If DVLD_LTC=0 and DVLD_DCYC=1, DVALID behaves the same as the first mode, with the exception that DVALID does not have a 50% duty cycle. This mode is intended for backward compatibility with HMP8112(A) timing dependencies in which DVALID did not have a 50% duty cycle timing and other timing variations. The timing diagrams for this mode can be found in Figures 14 and 15. If DVLD_LTC=1 and DVLD_DCYC=0, DVALID is present the entire line time on all scan lines. DVALID may occasionally be negated for two consecutive CLK2 cycles just prior to active video. In this mode DVALID is guaranteed have a 50% duty cycle only during the active video times. The timing for this mode differs from the timing shown in Figures 12 and 13 only in that DVALID will also be asserted during the blanking portion of the video line time as described above. If DVLD_LTC=1 and DVLD_DCYC=1, DVALID is present during the entire line time on all scan lines. DVALID is asserted during the blanking intervals as needed to ensure a constant number of total samples per line. The timing for this mode differs from the timing shown in Figures 14 and 15 only in that DVALID will also be asserted during the blanking portion of the video line time as described above. 12 HMP8115 If 16-bit YCbCr, 15-bit RGB data, or 16-bit RGB data is generated, it is output following the rising edge of CLK2 while DVALID is asserted. Either linear or gamma-corrected RGB data may be output. The pixel output timing is shown in Figures 12 to 15. BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD are output following the rising edge of CLK2. When BLANK is asserted and VBIVALID is deasserted, the YCbCr outputs have a value of 16 for Y and 128 for Cb and Cr; the RGB outputs have a value of 0. CLK DVALID BLANK P15-P8 Y0 Y1 Y2 Y3 Y4 P7-P0 Cb0 tDVLD Cr0 Cb2 Cr2 Cb4 NOTES: 11. Y0 is the first active luminance pixel data of a line. Cb0 and Cr0 are first active chrominance pixel data in a line. Cb and Cr will alternate every cycle due to the 4:2:2 subsampling. 12. BLANK is asserted per Figure 9. FIGURE 12. OUTPUT TIMING FOR 16-BIT YCbCr MODE (DVLD_LTC = 0, DVLD_DCYC = 0) CLK DVALID P15-P11 [P14-P10] R0 R1 R2 R3 R4 P10-P5 [P9-P5] G0 G1 G2 G3 G4 P4-P0 B0 B1 B2 B3 B4 tDVLD NOTE: 13. BLANK is asserted per Figure 9. FIGURE 13. OUTPUT TIMING FOR 16-BIT [15-BIT] RGB MODE (DVLD_LTC = 0, DVLD_DCYC = 0) 13 HMP8115 CLK DVALID P15-P8 Y0 Y1 Y2 Y3 Y4 P7-P0 Cb0 tDVLD Cr0 Cb2 Cr2 Cb4 NOTES: 14. Y0 is the first active luminance pixel of a line. Cb0 and Cr0 are first active chrominance pixels in a line. Cb and Cr will alternate every cycle due to the 4:2:2 subsampling. 15. BLANK is asserted per Figure 9. 16. DVALID is asserted for every valid pixel during both active and blanking regions. DVALID is not a 50% duty cycle synchronous output and will appear to jitter as the Output Sample Rate converter adjusts the output timing for various data rates and clock frequency inputs. FIGURE 14. OUTPUT TIMING FOR 16-BIT YCbCr MODE (DVLD_LTC = 0, DVLD_DCYC = 1) CLK DVALID BLANK P15-P11 [P14-P10] P10-P5 [P9-P5] P4-P0 R0 R1 R2 R3 R4 G0 G0 G2 G2 G4 B0 B1 B2 B3 B4 NOTES: 17. BLANK is asserted per Figure 9. tDVLD 18. DAVLID is asserted for every valid pixel during both active and blanking regions. DVALID is not a 50% duty cycle synchronous output and will appear to jitter as the Output Sample Rate converter adjusts the output timing for various data rates and clock frequency inputs. FIGURE 15. OUTPUT TIMING FOR 16-BIT [15-BIT] RGB MODE (DVLD_LTC = 0, DVLD_DCYC = 1) 8-BIT BT.656 OUTPUT If BT.656 data is generated, it is output following each rising edge of CLK2. The BT.656 EAV and SAV formats are shown in Table 4 and the pixel output timing is shown in Figure 16. The EAV and SAV timing is determined by the programmed horizontal and vertical blank timing BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD are output following the rising edge of CLK2. For proper operation, CLK2 must be exactly 2x the desired output sample rate. The DVALID output is continuously asserted during the entire active video time. During the blanking intervals, the YCbCr outputs have a value of 16 for Y and 128 for Cb and Cr, unless ancillary data is present. Due to the use of digital PLLs and source video timing the total # of samples per line may not equal exactly 1716 (NTSC) or 1728 (PAL). The active video portion of the BT.656 data stream is always exactly 1440 continuous samples. Any line-to-line timing difference from nominal # of samples per line, plus or minus, is accommodated in the horizontal blanking interval. 14 HMP8115 . CLK DVALID BLANK P[15-8] FF 00 00 Status Cb0 Y0 Cr0 Y1 Cb2 Y2 tDVLD NOTES: 19. Y0 is the first active luminance pixel data of a line. Cb0 and Cr0 are first active chrominance pixel data in a line. Cb and Cr will alternate every cycle due to the 4:2:2 subsampling. Pixel data is not output during the blanking period. 20. Notice that DVALID is not asserted during the preamble and that BLANK is still asserted. 21. See Table 4 for Status bit definitions. FIGURE 16. OUTPUT TIMING FOR 8-BIT BT.656 MODE TABLE 4. BT.656 EAV AND SAV SEQUENCES PIXEL INPUT P15 1 Preamble 0 0 Status Word NOTES: 22. P3 = V xor H; P2 = F xor H; P1 = F xor V; P0 = F xor V xor H 23. F: “0” = field 1; “1” = field 2 24. V: “1” during vertical blanking 25. H: “0” at SAV (start of active video); “1” at EAV (end of active video) 1 P14 1 0 0 F P13 1 0 0 V P12 1 0 0 H P11 1 0 0 P3 P10 1 0 0 P2 P9 1 0 0 P1 P8 1 0 0 P0 Advanced Features In addition to digitizing an analog video signal the HMP8115 has hardware to process different types of Vertical Blanking Interval (VBI) data as described in the following sections. Detection of Closed Captioning The closed caption decoder monitors the appropriate scan lines looking for the clock run-in and start bits used by captioning. If found, it locks to the clock run-in, the caption data is sampled and loaded into shift registers, and the data is then transferred to the caption data registers. If the clock run-in and start bits are not found, it is assumed the scan line contains video data unless other VBI information is detected, such as teletext. Once the clock run-in and start bits are found on the appropriate scan line for four consecutive odd fields, the Closed Captioning odd field Detect status bit is set to “1”. It is reset to “0” when the clock run-in and start bits are not found on the appropriate scan lines for four consecutive odd fields. Once the clock run-in and start bits are found on the appropriate scan line for four consecutive even fields, the Closed Captioning even field Detect status bit is set to “1”. It is reset to “0” when the clock run-in and start bits are not found on the appropriate scan lines for four consecutive even fields. “SLICED” VBI DATA CAPTURE The HMP8115 implements “sliced” data capture of select types of VBI data. The VBI decoders incorporate detection hysteresis to prevent them from rapidly turning on and off due to noise and transmission errors. In order to handle realworld signals, the VBI decoders also compensate for DC offsets and amplitude variations. CLOSED CAPTIONING During closed captioning capture, the scan lines containing captioning information are monitored. If closed captioning is enabled and captioning data is present, the caption data is loaded into the caption data registers. 15 HMP8115 Reading the Caption Data The caption data registers may be accessed in two ways: via the I2C interface or as BT.656 ancillary data. Captioning Disabled on Both Lines In this case, any caption data present is ignored. The Caption odd field Read status bit and the Caption even field Read status bit are always a “0”. Odd Field Captioning In this case, any caption data present on line 284 (or line 281 or 335 in the PAL modes) is ignored. Caption data present on line 21 (or line 18 or 22 in the PAL modes) is captured into a shift register then transferred to CLOSED CAPTION_ODD_A register 20H and CLOSED CAPTION_ODD_B register 21H. The Caption even field Read status bit is always a “0”. The Caption odd field Read status bit is set to “1” after data has been transferred from the shift register to the CLOSED CAPTION_ODD_A and CLOSED CAPTION_ODD_B registers. It is set to “0” after the data has been read out. Even Field Captioning In this case, any caption data present on line 21 (or line 18 or 22 in the PAL modes) is ignored. Caption data present on line 284 (or line 281 or 335 in the PAL modes) is captured into a shift register then transferred to CLOSED CAPTION_EVEN_A register 22H and CLOSED CAPTION_EVEN_B register 23H. The Caption odd field Read status bit is always a “0”. The Caption even field Read status bit is set to “1” after data has been transferred from the shift register to the CLOSED CAPTION_EVEN_A and CLOSED CAPTION_EVEN_B registers. It is set to “0” after the data has been read out. Odd and Even Field Captioning Caption data present on line 21 (or line 18 or 22 in the PAL modes) is captured into a shift register then transferred to the CLOSED CAPTION_ODD_A and CLOSED CAPTION_ODD_B registers. Caption data present on line 284 (or line 281 or 335 in the PAL modes) is captured into a shift register then transferred to the CLOSED CAPTION_EVEN_A and CLOSED CAPTION_EVEN_B registers. The Caption odd field Read status bit is set to “1” after data has been transferred from the shift register to the CLOSED CAPTION_ODD_A and CLOSED CAPTION_ODD_B registers. It is set to “0” after the data has been read out. The Caption even field Read status bit is set to “1” after data has been transferred from the shift register to the CLOSED CAPTION_EVEN_A and CLOSED CAPTION_EVEN_B registers. It is set to “0” after the data has been read out. Detection of WSS The WSS decoder monitors the appropriate scan lines looking for the run-in and start codes used by WSS. If found, it locks to the run-in code, the WSS data is sampled and loaded into shift registers, and the data is then transferred to the WSS data registers. If the run-in and start codes are not found, it is assumed the scan line contains video data unless other VBI information is detected, such as teletext. Once the run-in and start codes are found on the appropriate scan line for four consecutive odd fields, the WSS Line 20 Detect status bit is set to “1”. It is reset to “0” when the run-in and start codes are not found on the appropriate scan lines for four consecutive odd fields. Once the run-in and start codes are found on the appropriate scan line for four consecutive even fields, the WSS Line 283 Detect status bit is set to “1”. It is reset to “0” when the clock run-in and start bits are not found on the appropriate scan lines for four consecutive even fields. Reading the WSS Data The WSS data registers may be accessed in two ways: via the I2C interface or as BT.656 ancillary data. WSS Disabled on Both Lines In this case, any WSS data present is ignored. The WSS odd field Read status bit and the WSS even field Read status bit are always a “0”. Odd Field WSS In this case, any WSS data present on line 283 (or line 280 or 336 in the PAL modes) is ignored. WSS data present on line 20 (or line 17 or 23 in the PAL modes) is captured into a shift register then transferred to the WSS_ODD_A and WSS_ODD_B data registers. The WSS even field Read status bit is always a “0”. The WSS odd field Read status bit is set to “1” after data has been transferred from the shift register to the WSS_ODD_A and WSS_ODD_B registers. It is set to “0” after the data has been read out. Even Field WSS In this case, any WSS data present on line 20 (or line 17 or 23 in the PAL modes) is ignored. WSS data present on line 283 (or line 280 or 336 in the PAL modes) is captured into a shift register then transferred to the WSS_EVEN_A and WSS_EVEN_B data registers. The WSS odd field Read status bit is always a “0”. The WSS even field Read status bit is set to “1” after data has been transferred from the shift register to the WSS_EVEN_A and WSS_EVEN_B registers. It is set to “0” after the data has been read out. WIDESCREEN SIGNALLING (WSS) During WSS capture (ITU-R BT.1119 and EIAJ CPX-1204), the scan lines containing WSS information are monitored. If WSS is enabled and WSS data is present, the WSS data is loaded into the WSS data registers. 16 HMP8115 Odd and Even WSS WSS data present on line 20 (or line 17 or 23 in the PAL modes) is captured into a shift register then transferred to the WSS_ODD_A and WSS_ODD_B registers. WSS data present on line 283 (or line 280 or 336 in the PAL modes) is captured into a shift register then transferred to the WSS_EVEN_A and WSS_EVEN_B registers. The WSS odd field Read status bit is set to “1” after data has been transferred from the shift register to the WSS_ODD_A and WSS_ODD_B registers. It is set to “0” after the data has been read out. The WSS even field Read status bit is set to “1” after data has been transferred from the shift register to the WSS_EVEN_A and WSS_EVEN_B registers. It is set to “0” after the data has been read out. Real-Time Control Interface (RTCI) information. Teletext and RTCI data is only available as BT.656 ancillary data. VBIVALID OUTPUT TIMING The VBIVALID output is asserted when outputting closed captioning, widescreen signalling, teletext or RTCI data as BT.656 ancillary data. It is asserted during the entire BT.656 ancillary data packet time, including the preamble. BT.656 CLOSED CAPTIONING AND WIDE SCREEN SIGNALLING Table 5 illustrates the format when outputting the caption data registers as BT.656 ancillary data. The ancillary data is present during the horizontal blanking interval after the line containing the captioning information. Table 6 illustrates the format when outputting the WSS data registers as BT.656 ancillary data. The ancillary data is present during the horizontal blanking interval after the line containing the WSS information. BT.656 ANCILLARY DATA Through the BT.656 interface the HMP8115 can generate non-active video data which contains CC, WSS, teletext or CLK VBIVALID P[15-8] 00 FF FF DATA ID BLK # # BYTES/4 BYTE #1 BYTE #2 BYTE #3 BYTE #4 NOTES: tDVLD 26. BT.656 VBI ancillary starts with a 00H, FFH and FFH sequence which is opposite to the SAV/EAV sequence of FFH, 00H and 00H. 27. During active VBI data intervals, DVALID is deasserted and BLANK is asserted. FIGURE 17. OUTPUT TIMING FOR BT.656 VBI DATA TRANSFERS (CC, WSS, TELETEXT, RTCI) TABLE 5. READING THE CLOSED CAPTION DATA AS BT.656 ANCILLARY DATA PIXEL OUTPUT Preamble P15 0 1 1 Data ID Data Block Number Data Word Count Caption Data P14 P14 P14 P14 P14 P14 P14 CRC NOTES: 28. ep = even parity for P8-P13. 29. CRC = Sum of P8-P14 of Data ID through last user data word. Preset to all zeros, carry is ignored. P14 P14 0 1 1 ep ep ep ep ep ep ep bit 6 P13 0 1 1 1 0 0 0 0 0 0 bit 5 P12 0 1 1 1 0 0 0 0 0 0 bit 4 P11 0 1 1 0 0 0 bit 15 bit 11 bit 7 bit 3 bit 3 P10 0 1 1 0 0 0 bit 14 bit 10 bit 6 bit 2 bit 2 P9 0 1 1 0 0 0 bit 13 bit 9 bit 5 bit 1 bit 1 P8 0 1 1 0 = odd field data 1 = even field data 1 1 bit 12 bit 8 bit 4 bit 0 bit 0 17 HMP8115 TABLE 6. OUTPUTTING THE SLICED WSS DATA AS BT.656 ANCILLARY DATA PIXEL OUTPUT Preamble P15 0 1 1 Data ID Data Block Number Data Word Count WSS Data P14 P14 P14 P14 P14 P14 P14 WSS CRC Data P14 P14 P14 P14 CRC NOTES: 30. ep = even parity for P8-P13. 31. WSS CRC data = “00 0000” during PAL operation. 32. CRC = Sum of P8-P14 of Data ID through last user data word. Preset to all zeros, carry is ignored. P14 P14 0 1 1 ep ep ep ep ep ep ep ep ep ep ep bit 6 P13 0 1 1 1 0 0 0 0 0 0 0 0 0 0 bit 5 P12 0 1 1 1 0 0 0 0 0 0 0 0 0 0 bit 4 P11 0 1 1 0 0 0 0 bit 11 bit 7 bit 3 0 bit 3 0 0 bit 3 P10 0 1 1 0 0 0 0 bit 10 bit 6 bit 2 0 bit 2 0 0 bit 2 P9 0 1 1 1 0 1 bit 13 bit 9 bit 5 bit 1 bit 5 bit 1 0 0 bit 1 P8 0 1 1 0 =odd field data 1 =even field data 1 0 bit 12 bit 8 bit 4 bit 0 bit 4 bit 0 0 0 bit 0 TELETEXT The HMP8115 supports ITU-R BT.653 625-line and 525-line teletext system B, C and D capture. NABTS (North American Broadcast Teletext Specification) is the same as BT.653 525line system C, which is also used to transmit Intel Intercast™ information. WST (World System Teletext) is the same as BT.653 system B. Figure 18 shows the basic structure of a video signal that contains teletext data. The scan lines containing teletext information are monitored. If teletext is enabled and teletext data is present, the teletext data is output as BT.656 ancillary data. Detection of Teletext The teletext decoder monitors the scan lines, looking for the 16-bit clock run-in (sometimes referred to as the clock synchronization code) used by teletext. If found, it locks to the clock run-in, the teletext data is sampled and loaded into shift registers, and the data is then transferred to internal holding registers. If the clock run-in is not found, it is assumed the scan line contains video data unless other VBI information is detected, such as WSS. If a teletext clock run-in is found before line 23 or line 289 for NTSC and (M) PAL, or line 336 for (B, D, G, H, I, N, NC) PAL, the VBI Teletext Detect status bit is immediately set to “1”. If not found by these lines, the status bit is immediately reset to “0”. Accessing the Teletext Data The teletext data must be output as BT.656 ancillary data. The I2C interface does not have the bandwidth to output teletext information when needed. Table 7 illustrates the teletext BT.656 ancillary data format and Figure 17 depicts the portion of the incoming teletext signal which is sliced and output as part of the ancillary data stream. The teletext data is present during the horizontal blanking interval after the line containing the teletext information. The actual BT.656 bytes that contain teletext data only contain 4 bits of the actual data packet. Note that only the data packet of Figure 18 is sent as ancillary data; the clock run-in is not included in the data stream. Intercast™ is a trademark of Intel Corporation. 18 HMP8115 CLOCK RUN-IN DATA PACKET Bit 0 MSB NOTES: 33. The MSB is bit number: 271 for system C, 279 for system B 525-line and 343 for system B 625-line. 34. The clock run-in is 16 bits wide for both systems and is not included in the BT.656 ancillary data stream. 35. The bit rate is 5.727272 Mbits/second for system B and C on 525/60 systems and 6.9375 and 5.734375 Mbits/second respectively for 625/50 systems. FIGURE 18. TELETEXT VBI VIDEO SIGNAL TABLE 7. OUTPUTTING THE SLICED TELETEXT DATA AS BT.656 ANCILLARY DATA PIXEL INPUT Preamble P15 0 1 1 Data ID Data Block Number Data Word Count Teletext Data (B, 625-line = 43 bytes) (B, 525-line = 35 bytes) (C = 34 bytes) P14 P14 P14 P14 P14 0 1 1 ep ep ep ep P13 0 1 1 1 0 0 0 = 525-line 1 = 625-line 0 P12 0 1 1 1 0 1 0 = system B 1 = system C 0 : P14 P14 Reserved P14 P14 CRC NOTES: 36. ep = even parity for P8-P13. 37. CRC = Sum of P8-P14 of Data ID through last user data word. Preset to all zeros, carry is ignored. 38. For 525-line system B, bits 280-343 are “0”. 39. For system C, bits 272-343 are “0”. P14 ep ep ep ep bit 6 0 0 0 0 bit 5 0 0 0 0 bit 4 bit 7 bit 3 0 0 bit 3 bit 6 bit 2 0 0 bit 2 bit 5 bit 1 0 0 bit 1 bit 4 bit 0 0 0 bit 0 P11 0 1 1 0 0 0 bit 343 P10 0 1 1 1 0 1 bit 342 P9 0 1 1 0 0 1 bit 341 P8 0 1 1 0 1 0 bit 340 P14 ep bit 339 bit 338 bit 337 bit 336 19 HMP8115 REAL TIME CONTROL INTERFACE The Real Time Control Interface (RTCI) outputs timing information for a NTSC/PAL encoder as BT.656 ancillary data. This allows the encoder to generate “clean” output video. RTCI information via BT.656 ancillary data is shown in Table 8. If enabled, this transfer occurs once per line and is completed before the start of the SAV sequence. The PSW bit is always a “0” for NTSC encoding. During PAL encoding, it indicates the sign of V (“0” = negative; “1” = positive) for that scan line. TABLE 8. OUTPUTTING RTCI AS BT.656 ANCILLARY DATA PIXEL INPUT Preamble P15 0 1 1 Data ID Data Block Number Data Word Count HPLL Increment P14 P14 P14 P14 P14 P14 P14 FSCPLL Increment P14 P14 P14 0 1 1 ep ep ep ep ep ep ep ep ep P13 0 1 1 1 0 0 0 0 0 0 PSW F2 = 0 P12 0 1 1 1 0 0 0 0 0 0 0 F1 = 0 : P14 P14 CRC NOTES: 40. ep = even parity for P8-P13. 41. CRC = Sum of P8-P14 of Data ID through last user data word. Preset to all zeros, carry is ignored. P14 ep ep bit 6 0 0 bit 5 0 0 bit 4 bit 7 bit 3 bit 3 bit 6 bit 2 bit 2 bit 5 bit 1 bit 1 bit 4 bit 0 bit 0 P11 0 1 1 0 0 0 0 0 0 0 bit 31 bit 27 P10 0 1 1 1 0 0 0 0 0 0 bit 30 bit 26 P9 0 1 1 0 0 1 0 0 0 0 bit 29 bit 25 P8 0 1 1 1 1 1 0 0 0 0 bit 28 bit 24 20 HMP8115 Host Interface All internal registers may be written to or read by the host processor at any time, except for those bits identified as read-only. The bit descriptions of the control registers are listed in Tables 9-48. The HMP8115 supports the fast-mode (up to 400 kbps) I2C interface consisting of the SDA and SCL pins. The device acts as a slave for receiving and transmitting data over the serial interface. When the interface is not active, SCL and SDA must be pulled high using external 4kΩ pull-up resistors. The slave address for the HMP8115 is 88H. Data is placed on the SDA line when the SCL line is low and held stable when the SCL line is pulled high. Changing the state of the SDA line while SCL is high will be interpreted as either an I2C bus START or STOP condition as indicated by Figure 20. During I2C write cycles, the first data byte after the slave address is treated as the control register sub address and is written into the internal address register. Any remaining data bytes sent during an I2C write cycle are written to the control registers, beginning with the register specified by the address register as given in the first byte. The address register is then autoincremented after each additional data byte sent on the I2C bus during a write cycle. Writes to reserved bits within registers or reserved registers are ignored. In order to perform a read from a specific control register within the HMP8115, an I2C bus write must first be performed to properly setup the address register. Then an I2C bus read can be performed to read from the desired control register(s). As a result of needing the write cycle for a read cycle there are actually two START conditions as shown in Figure 21. The address register is then autoincremented after each byte read during the I2C read cycle. Reserved registers return a value of 00H . tBUF SDA tSU:DATA tHD:DATA SCL tLOW tHIGH tR tF tSU:STOP FIGURE 19. I2C TIMING DIAGRAM SDA SCL S START CONDITION 1-7 ADDRESS 8 R/W 9 ACK 1-7 DATA 8 9 ACK P STOP CONDITION FIGURE 20. I2C SERIAL DATA FLOW DATA WRITE 1000 1000 S CHIP ADDR 0x88 A SUB ADDR A DATA REGISTER POINTED TO BY SUB ADDR A DATA A P FROM HMP8115 OPTIONAL FRAME MAY BE REPEATED n TIMES FROM MASTER S = START CYCLE P = STOP CYCLE A = ACKNOWLEDGE NA = NO ACKNOWLEDGE DATA READ S 1000 1000 (R/W) CHIP ADDR 0x88 A SUB ADDR A S CHIP ADDR 0x89 A DATA REGISTER POINTED TO BY SUB ADDR A DATA NA P OPTIONAL FRAME MAY BE REPEATED n TIMES FIGURE 21. REGISTER WRITE/READ FLOW 21 HMP8115 HMP8115 Control Registers TABLE 9. 8115 REGISTER SUMMARY SUBADDRESS 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H-17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH-2FH RESET/ DEFAULT VALUE 15H 18H 00H 00H 01H 00H 52H 04H 00H 00H 00H 00H 00H 00H 00H 80H 00H 80H 40H 10H 00H 80H 80H 80H 80H 00H 00H 00H 00H 00H 00H Defaults to Autodetect of input video standard Defaults to 16-bit YCbCr format Defaults to outputs disabled Defaults to 27MHz CLK2, Rectangular Pixel mode Defaults to input signal select = NTSC/PAL1 USE VALUE CONTROL REGISTER PRODUCT ID INPUT FORMAT OUTPUT FORMAT OUTPUT CONTROL GENLOCK CONTROL ANALOG INPUT CONTROL COLOR PROCESSING RESERVED LUMA PROCESSING Reserved SLICED VBI DATA ENABLE SLICED VBI DATA OUTPUT VBI DATA STATUS Reserved VIDEO STATUS INTERRUPT MASK INTERRUPT STATUS Reserved BRIGHTNESS CONTRAST HUE SATURATION COLOR GAIN Reserved SHARPNESS HOST CONTROL CLOSED CAPTION_ODD_A CLOSED CAPTION_ODD_B CLOSED CAPTION_EVEN_A CLOSED CAPTION_EVEN_B WSS_ODD_A WSS_ODD_B WSS_CRC_ODD WSS_EVEN_A WSS_EVEN_B WSS_CRC_EVEN Reserved COMMENTS 22 HMP8115 TABLE 9. 8115 REGISTER SUMMARY (Continued) SUBADDRESS 30H 31H 32H 33H 34H 35H 36H 37H 38H-3FH 40H-7FH RESET/ DEFAULT VALUE 4AH 03H 7AH 02H 01H 12H 40H FFH TABLE 10. PRODUCT ID REGISTER SUB ADDRESS = 00H BIT NO. 7-0 FUNCTION Product ID DESCRIPTION This 8-bit register specifies the last two digits of the product number. It is a read-only register. Data written to it is ignored. TABLE 11. INPUT FORMAT REGISTER SUB ADDRESS = 01H BIT NO. 7 6-5 FUNCTION Reserved Video Timing Standard These bits are read only unless D4 = “0”. 00 = (M) NTSC 01 = (B, D, G, H, I, N) PAL 10 = (M) PAL 11 = Combination (N) PAL; also called (NC) PAL 0 = Manual selection of video timing standard 1 = Auto detect of video timing standard Typically, this bit should be a “1” during (M) NTSC and (M, N) PAL operation. Otherwise, it should be a “0”. 0 = Video source has a 0 IRE blanking pedestal 1 = Video source has a 7.5 IRE blanking pedestal DESCRIPTION RESET STATE 0B 00B RESET STATE 15H USE VALUE Table 2 Table 2 Table 2 Table 2 Table 2 Table 2 Table 2 20H Recommend HSYNC DETECT WINDOW= 20H CONTROL REGISTER START H_BLANK LOW START H_BLANK HIGH END H_BLANK START V_BLANK LOW START V_BLANK HIGH END V_BLANK END HSYNC HSYNC DETECT WINDOW Reserved Test and Unused COMMENTS 4 3 Auto Detect Video Standard Setup Select 1B 1B 2-0 Reserved 000B 23 HMP8115 TABLE 12. OUTPUT FORMAT REGISTER SUB ADDRESS = 02H BIT NO. 7-5 FUNCTION Output Color Format 000 = 16-bit 4:2:2 YCbCr 001 = 8-bit 4:2:2 YCbCr 010 = 8-bit BT.656 011 = 15-bit RGB 100 = 16-bit RGB 101 = reserved 110 = reserved 111 = reserved These bits are ignored except during RGB output modes. 00 = Linear RGB (gamma of input source = 2.2) 01 = Linear RGB (gamma of input source = 2.8) 10 = Gamma-corrected RGB (gamma = gamma of input source) 11 = reserved 00 = Normal operation 01 = Output blue field 10 = Output black field 11 = Output 75% color bars This bit specifies whether or not the chrominance pixels have a halfline pixel offset from their associated luminance pixels. 0 = Half-line offset 1 = Aligned TABLE 13. OUTPUT CONTROL REGISTER SUB ADDRESS = 03H BIT NO. 7 FUNCTION Video Data Output Enable Video Timing Output Enable DESCRIPTION This bit is used to enable the P0-P15 outputs. 0 = Outputs 3-stated 1 = Outputs enabled This bit is used to enable the HSYNC, VSYNC, BLANK, FIELD, VBIVALID, DVALID, and INTREQ outputs. 0 = Outputs 3-stated 1 = Outputs enabled 0 = Active low (low during odd fields) 1 = Active high (high during odd fields) 0 = Active low (low during blanking) 1 = Active high (high during blanking) 0 = Active low (low during horizontal sync) 1 = Active high (high during horizontal sync) 0 = Active low (low during vertical sync) 1 = Active high (high during vertical sync) 0 = Active low (low during valid pixel data) 1 = Active high (high during valid pixel data) 0 = Active low (low during VBI data) 1 = Active high (high during VBI data) RESET STATE 0B DESCRIPTION RESET STATE 000B 4-3 RGB Gamma Select 00B 2-1 Output Color Select Vertical Pixel Siting 00B 0 0B 6 0B 5 4 3 2 1 0 FIELD Polarity Polarity BLANK HSYNC Polarity VSYNC Polarity DVALID Polarity VBIVALID Polarity 0B 0B 0B 0B 0B 0B 24 HMP8115 TABLE 14. GENLOCK CONTROL REGISTER SUB ADDRESS = 04H BIT NO. 7 6 FUNCTION Aspect Ratio Mode Freeze Output Timing Enable 0 = Rectangular (BT.601) pixels 1 = Square pixels Setting this bit to a “1” freezes the output timing at the end of the field. Resetting this bit to a “0” resumes normal operation at the start of the next field. 0 = Normal operation 1 = Freeze output timing This bit is ignored during the 8-bit YCbCr and BT.656 output modes. During 16-bit YCbCr, 15-bit RGB, or 16-bit RGB output modes, this bit is defined as: 0 = DVALID has 50/50 duty cycle at the pixel output datarate 1 = DVALID goes active based on linelock. This will cause DVALID to not have a 50/50 duty cycle. This bit is intended to be used in maintaining backward compatibilty with the HMP8112A DVALID output timing. During 16-bit YCbCr, 15-bit RGB, or 16-bit RGB output modes, this bit is defined as: 0 = DVALID present only during active video time on active scan lines 1 = DVALID present the entire scan line time on all scan lines During the 8-bit YCbCr and BT.656 output modes, this bit defines the DVALID output signal as: 0 = Normal timing 1 = DVALID signal ANDed with CLK2 This bit specifies the number of missing horizontal sync pulses before the device goes into the horizontal lock acquisition mode. In mode “0”, the default value of the HPLL Adjust register should be used. In mode “1”, the typical values the HPLL Adjust register should be 10H to 20H. 0 = 12 pulses 1 = 1 pulse This bit specifies the number of missing vertical sync pulses before the device goes into the vertical lock acquisition mode. 0 = 3 pulses 1 = 1 pulse This bit indicates the frequency of the CLK2 input clock. 00 = 24.54MHz 01 = 27.0MHz 10 = 29.5MHz 11 = Reserved TABLE 15. ANALOG INPUT CONTROL REGISTER SUB ADDRESS = 05H BIT NO. 7-3 2-0 FUNCTION Reserved Video Signal Input Select 000 = NTSC/PAL 1 001 = NTSC/PAL 2 010 = NTSC/PAL 3 011 = S-video 100 = reserved 101 = reserved 110 = reserved 111 = reserved DESCRIPTION RESET STATE 00000B 000B DESCRIPTION RESET STATE 0B 0B 5 DVALID Duty Cycle Control (DVLD_DCYC) 0B 4 DVALID Line Timing Control (DVLD_LTC) 0B 3 Missing HSYNC Detect Select 0B 2 Missing VSYNC Detect Select 0B 1-0 CLK2 Frequency 01B 25 HMP8115 TABLE 16. COLOR PROCESSING REGISTER SUB ADDRESS = 06H BIT NO. 7-6 FUNCTION Color Gain Control Select DESCRIPTION If a value of “10”, the color gain adjust register is used to specify the amount of color gain to be applied. 00 = No gain control (gain = 1x) 01 = Automatic gain control 10 = Fixed gain control 11 = Freeze automatic gain control 00 = Force color on 01 = Enable color killer 10 = reserved 11 = Force color off Coring may be used to reduce low-level noise around zero (code 128) in the CbCr signals. 00 = No coring 01 = 1 code coring 10 = 2 code coring 11 = 3 code coring This bit specifies whether the contrast control affects just the Y data (“0”) or both the Y and CbCr data (“1”). To avoid color shifts when changing contrast, this bit should be a “1”. 0 = Contrast controls only Y data 1 = Contrast controls Y and CbCr data This bit selects the bandwidth of the CbCr data. 0 = 850kHz 1 = 1.5MHz TABLE 17. LUMA PROCESSING REGISTER SUB ADDRESS = 08H BIT NO. 7-6 FUNCTION Y Filtering Select DESCRIPTION The chroma trap filter may be used to remove any residual color subcarrier information from the Y channel. During S-video operation, it should be disabled. During PAL operation, it should be enabled. The 3MHz lowpass filter may be used to remove high-frequency noise. 00 = No filtering 01 = Enable chroma trap filter 10 = Enable 3.0MHz lowpass filter 11 = reserved Coring may be used to reduce low-level noise around black in the Y signal. 00 = No coring 01 = 1 code coring 10 = 2 code coring 11 = 3 code coring Coring may be used to reduce high-frequency low-level noise in the Y signal. 00 = No coring 01 = 1 code coring 10 = 2 code coring 11 = 3 code coring If a value of “01” or “10”, the sharpness adjust register is used to specify the amount of sharpness to be applied. 00 = Bypass sharpness control 01 = Maximum gain at 2.6MHz 10 = Maximum gain at color subcarrier frequency 11 = reserved RESET STATE 00B RESET STATE 01B 5-4 Color Killer Select 01B 3-2 Color Coring Select 00B 1 Contrast Control Select 1B 0 Color Lowpass Filter Select 0B 5-4 Black Level Y Coring Select 00B 3-2 High Frequency Y Coring Select 01B 1-0 Sharpness Frequency Select 00B 26 HMP8115 TABLE 18. SLICED VBI DATA ENABLE REGISTER SUB ADDRESS = 0AH BIT NO. 7-6 FUNCTION Sliced Closed Captioning Enable DESCRIPTION 00 = Closed caption disabled 01 = Closed caption enabled for odd fields: line 21 for NTSC, line 18 for (M) PAL, or line 22 for (B, D, G, H, I, N, NC) PAL 10 = Closed caption enabled for even fields: line 284 for NTSC, line 281 for (M) PAL, or line 335 for (B, D, G, H, I, N, NC) PAL 11 = Closed caption enabled for both odd and even fields 00 = WSS disabled 01 = WSS enabled for odd fields: line 20 for NTSC; line 17 for (M) PAL, or line 23 for (B, D, G, H, I, N, NC) PAL 10 = WSS enabled for even fields: line 283 for NTSC, line 280 for (M) PAL, or line 336 for (B, D, G, H, I, N, NC) PAL 11 = WSS enabled for both odd and even fields 00 = Teletext disabled 01 = Teletext system B enabled 10 = Teletext system C enabled 11 = reserved RESET STATE 00B 5-4 Sliced WSS Enable 00B 3-2 Sliced Teletext Enable Reserved 00B 1-0 00B TABLE 19. SLICED VBI DATA OUTPUT REGISTER SUB ADDRESS = 0BH BIT NO. 7 FUNCTION Sliced Closed Caption BT.656 Output Enable Sliced WSS BT.656 Output Enable DESCRIPTION This bit specifies whether or not to output the caption data registers as BT.656 ancillary data. It is ignored unless captioning is enabled. Access via the I2C interface is always available. 0 = Do not output as BT.656 ancillary data 1 = Output as BT.656 ancillary data This bit specifies whether or not to output the WSS data registers as BT.656 ancillary data. It is ignored unless WSS is enabled. Access via the I2C interface is always available. 0 = Do not output as BT.656 ancillary data 1 = Output as BT.656 ancillary data This bit specifies whether or not to output teletext data as BT.656 ancillary data. It is ignored unless teletext is enabled. 0 = Do not output as BT.656 ancillary 1 = Output as BT.656 ancillary data RESET STATE 0B 6 0B 5 Sliced Teletext BT.656 Output Enable Reserved RTCI BT.656 Output Enable 0B 4-1 0 0000B This bit specifies whether or not to output RTCI data as BT.656 ancillary data. 0 = Do not output as BT.656 ancillary 1 = Output as BT.656 ancillary data 0B 27 HMP8115 TABLE 20. VBI DATA STATUS REGISTER SUB ADDRESS = 0CH BIT NO. 7 FUNCTION Closed Captioning Odd Field Detect Status Closed Captioning Even Field Detect Status WSS Odd Field Detect Status WSS Even Field Detect Status VBI Teletext Detect Status Reserved TABLE 21. VIDEO STATUS REGISTER SUB ADDRESS = 0EH BIT NO. 7 FUNCTION Vertical Lock Status Horizontal Lock Status Color Lock Status Input Video Detect Status Reserved DESCRIPTION This bit is read-only. Data written to this bit is ignored. 0 = Not vertically locked 1 = Vertically locked This bit is read-only. Data written to this bit is ignored. 0 = Not horizontally locked 1 = Horizontally locked This bit is read-only. Data written to this bit is ignored. 0 = Not color locked 1 = Color locked This bit is read-only. Data written to this bit is ignored. 0 = Input video not detected on selected video input 1 = Input video detected on selected video input RESET STATE 0B DESCRIPTION This bit is read-only. Data written to this bit is ignored. 0 = Closed captioning not detected 1 = Closed captioning detected This bit is read-only. Data written to this bit is ignored. 0 = Closed captioning not detected 1 = Closed captioning detected This bit is read-only. Data written to this bit is ignored. 0 = WSS not detected 1 = WSS detected This bit is read-only. Data written to this bit is ignored. 0 = WSS not detected 1 = WSS detected This bit is read-only. Data written to this bit is ignored. 0 = Teletext not detected during vertical blanking interval 1 = Teletext detected during vertical blanking interval RESET STATE 0B 6 0B 5 0B 4 0B 3 0B 2-0 000B 6 0B 5 0B 4 0B 3-0 0000B 28 HMP8115 TABLE 22. INTERRUPT MASK REGISTER SUB ADDRESS = 0FH BIT NO. 7 FUNCTION Genlock Loss Interrupt Mask Input Signal Loss Interrupt Mask DESCRIPTION If this bit is a “1”, an interrupt is generated when genlock is lost. 0 = Interrupt disabled 1 = Interrupt enabled If this bit is a “1”, an interrupt is generated when a video signal is no longer detected on the selected video input. 0 = Interrupt disabled 1 = Interrupt enabled If this bit is a “1”, an interrupt is generated when the Caption_ODD_A and Caption_ODD_B or the Caption_EVEN_A and Caption_EVEN_B data registers contain new data. 0 = Interrupt disabled 1 = Interrupt enabled If this bit is a “1”, an interrupt is generated when the WSS_ODD_A and WSS_ODD_B or the WSS_EVEN_A and WSS_EVEN_B data registers contain new data. 0 = Interrupt disabled 1 = Interrupt enabled If this bit is a “1”, an interrupt is generated when teletext information is first detected at the beginning of each field. 0 = Interrupt disabled 1 = Interrupt enabled RESET STATE 0B 6 0B 5 Closed Caption Interrupt Mask 0B 4 WSS Interrupt Mask 0B 3 Teletext Interrupt Mask 0B 2-1 0 Reserved Vertical Sync Interrupt Mask If this bit is a “1”, an interrupt is generated at the beginning of each field. 0 = Interrupt disabled 1 = Interrupt enabled TABLE 23. INTERRUPT STATUS REGISTER SUB ADDRESS = 10H 00B 0B BIT NO. 7 6 5 FUNCTION Genlock Loss Interrupt Status Input Signal Loss Interrupt Status Closed Caption Interrupt Status WSS Interrupt Status Teletext Interrupt Status Reserved Vertical Sync Interrupt Status DESCRIPTION If this bit is a “1”, the reason for the interrupt request was that genlock was lost. To clear the interrupt request, a “1” must be written to this bit. If this bit is a “1”, the reason for the interrupt request was that the input video source is no longer present. To clear the interrupt request, a “1” must be written to this bit. If this bit is a “1”, the reason for the interrupt request was that the Caption_ODD_A and Caption_ODD_B or the Caption_EVEN_A and Caption_EVEN_B data registers contain new data. To clear the interrupt request, a “1” must be written to this bit. If this bit is a “1”, the reason for the interrupt request was that the WSS_ODD_A and WSS_ODD_B or the WSS_EVEN_A and WSS_EVEN_B data registers contain new data. To clear the interrupt request, a “1” must be written to this bit. If this bit is a “1”, the reason for the interrupt request was that teletext data has been detected in the current field. To clear the interrupt request, a “1” must be written to this bit. RESET STATE 0B 0B 0B 4 0B 3 2-1 0 0B 00B If this bit is a “1”, the reason for the interrupt request was that a new field was started. To clear the interrupt request, a “1” must be written to this bit. 0B 29 HMP8115 TABLE 24. BRIGHTNESS REGISTER SUB ADDRESS = 18H BIT NO. 7 6-0 FUNCTION Reserved Brightness Adjust These bits control the brightness. They may have a value of +63 (“011 1111”) to -64 (“100 0000”), with positive values increasing brightness. A value of 0 (“000 0000”) has no effect on the data. TABLE 25. CONTRAST REGISTER SUB ADDRESS = 19H BIT NO. 7-0 FUNCTION Contrast Adjust DESCRIPTION These bits control the contrast. They may have a value of 0x (“0000 0000”) to 1.992x (“1111 1111”). A value of 1x (“1000 0000”) has no effect on the data. TABLE 26. HUE REGISTER SUB ADDRESS = 1AH BIT NO. 7-0 FUNCTION Hue Adjust DESCRIPTION These bits control the color hue. They may have a value of +30 degrees (“0111 1111”) to -30 degrees (“1111 1111”). A value of 0 degrees (“0000 0000”) has no effect on the color data. TABLE 27. SATURATION REGISTER SUB ADDRESS = 1BH BIT NO. 7-0 FUNCTION Saturation Adjust DESCRIPTION These bits control the color saturation. They may have a value of 0x (“0000 0000”) to 1.992x (“1111 1111”). A value of 1x (“1000 0000”) has no effect on the color data. A value of 0x (“0000 0000”) disables the color information. TABLE 28. COLOR GAIN REGISTER SUB ADDRESS = 1CH BIT NO. 7-0 FUNCTION Color Gain Adjust DESCRIPTION These bits control the amount of gain control for the color difference (CbCr) signals. They may have a value of 0.5x (“0010 0000”) to 3.98x (“1111 1111”). A value of 1x (“0100 0000”) has no effect on the data. This register is ignored unless the color gain control mode selection is “fixed gain control”. TABLE 29. SHARPNESS REGISTER SUB ADDRESS = 1EH BIT NO. 7-6 5-0 FUNCTION Reserved Sharpness Adjust These bits control the amount of gain control of high frequency luminance signals (either 2.6MHz or Fsc). They may have a value of +12dB (“11 1111”) to -12dB (“00 0100”). A value of 0dB (“01 0000”) has no effect on the data. This register is ignored if the sharpness mode selection is “disable sharpness control” or “reserved”. DESCRIPTION RESET STATE 00B 010000B RESET STATE 40H RESET STATE 80H RESET STATE 00H RESET STATE 80H DESCRIPTION RESET STATE 0B 0000000B 30 HMP8115 TABLE 30. HOST CONTROL REGISTER SUB ADDRESS = 1FH BIT NO. 7 FUNCTION Software Reset DESCRIPTION When this bit is set to 1, the entire device except the I2C bus is reset to a known state exactly like the RESET input going active. The software reset will initialize all register bits to their reset state. Once set this bit is self clearing after only 4 CLK periods. This bit is cleared on power-up by the external RESET pin. RESET STATE 0B 6 5 Reserved Closed Caption Odd Field Read Status Closed Caption Even Field Read Status WSS Odd Field Read Status WSS Even Field Read Status Reserved TABLE 31. CLOSED CAPTION_ODD_A DATA REGISTER SUB ADDRESS = 20H This bit is read-only. Data written to this bit is ignored. The bit is cleared when the caption data has been read out via the I2C interface or as BT.656 ancillary data. 0 = No new caption data 1 = Caption_ODD_A and Caption_ODD_B data registers contain new data. This bit is read-only. Data written to this bit is ignored. The bit is cleared when the caption data has been read out via the I2C interface or as BT.656 ancillary data. 0 = No new caption data 1 = Caption_EVEN_A and Caption_EVEN_B data registers contain new data. This bit is read-only. Data written to this bit is ignored. The bit is cleared when the WSS data has been read out via the I2C interface or as BT.656 ancillary data. 0 = No new WSS data 1 = WSS_ODD_A and WSS_ODD_B data registers contain new data. This bit is read-only. Data written to this bit is ignored. The bit is cleared when the WSS data has been read out via the I2C interface or as BT.656 ancillary data. 0 = No new WSS data 1 = WSS_EVEN_A and WSS_EVEN_B data registers contain new data. 0B 0B 4 0B 3 0B 2 0B 1-0 00B BIT NO. 7-0 FUNCTION Odd Field Caption Data DESCRIPTION If odd field captioning is enabled and present, this register is loaded with the first eight bits of caption data on line 18, 21, or 22. Bit 0 corresponds to the first bit of caption information. Data written to this register is ignored. TABLE 32. CLOSED CAPTION_ODD_B DATA REGISTER SUB ADDRESS = 21H RESET STATE 80H BIT NO. 15-8 FUNCTION Odd Field Caption Data DESCRIPTION If odd field captioning is enabled and present, this register is loaded with the second eight bits of caption data on line 18, 21, or 22. Data written to this register is ignored. TABLE 33. CLOSED CAPTION_EVEN_A DATA REGISTER SUB ADDRESS = 22H RESET STATE 80H BIT NO. 7-0 FUNCTION Even Field Caption Data DESCRIPTION If even field captioning is enabled and present, this register is loaded with the first eight bits of caption data on line 281, 284, or 335. Bit 0 corresponds to the first bit of caption information. Data written to this register is ignored. RESET STATE 80H 31 HMP8115 TABLE 34. CLOSED CAPTION_EVEN_B DATA REGISTER SUB ADDRESS = 23H BIT NO. 15-8 FUNCTION Even Field Caption Data DESCRIPTION If even field captioning is enabled and present, this register is loaded with the second eight bits of caption data on line 281, 284, or 335. Data written to this register is ignored. TABLE 35. WSS_ODD_A DATA REGISTER SUB ADDRESS = 24H BIT NO. 7-0 FUNCTION Odd Field WSS Data DESCRIPTION If odd field WSS is enabled and present, this register is loaded with the first eight bits of WSS information on line 17, 20, or 23. Bit 0 corresponds to the first bit of WSS information. Data written to this register is ignored. TABLE 36. WSS_ODD_B DATA REGISTER SUB ADDRESS = 25H BIT NO. 15-14 13-8 FUNCTION Reserved Odd Field WSS Data If odd field WSS is enabled and present, this register is loaded with the second six bits of WSS information on line 17, 20, or 23. Data written to this register is ignored. TABLE 37. WSS_CRC_ODD DATA REGISTER SUB ADDRESS = 26H BIT NO. 7-6 5-0 FUNCTION Reserved Odd Field WSS CRC Data If odd field WSS is enabled and present during NTSC operation, this register is loaded with the six bits of CRC information on line 20. It is always a “000000” during PAL operation. Data written to this register is ignored. TABLE 38. WSS_EVEN_A DATA REGISTER SUB ADDRESS = 27H BIT NO. 7-0 FUNCTION Even Field WSS Data DESCRIPTION If even field WSS is enabled and present, this register is loaded with the first eight bits of WSS information on line 280, 283, or 336. Bit 0 corresponds to the first bit of WSS information. Data written to this register is ignored. TABLE 39. WSS_EVEN_B DATA REGISTER SUB ADDRESS = 28H BIT NO. 15-14 13-8 FUNCTION Reserved Even Field WSS Data If even field WSS is enabled and present, this register is loaded with the second six bits of WSS information on line 280, 283, or 336. Data written to this register is ignored. DESCRIPTION RESET STATE 00B 000000B RESET STATE 00H DESCRIPTION RESET STATE 00B 000000B DESCRIPTION RESET STATE 00B 000000B RESET STATE 00H RESET STATE 80H 32 HMP8115 TABLE 40. WSS_CRC_EVEN DATA REGISTER SUB ADDRESS = 29H BIT NO. 7-6 5-0 FUNCTION Reserved Even Field WSS CRC Data If even field WSS is enabled and present during NTSC operation, this register is loaded with the six bits of CRC information on line 283. It is always a “000000” during PAL operation. Data written to this register is ignored. TABLE 41. START H_BLANK LOW REGISTER SUB ADDRESS = 30H BIT NO. 7-0 FUNCTION Assert BLANK Output Signal DESCRIPTION This 8-bit register is cascaded with Start H_Blank High Register to form a 10-bit start_horizontal_blank REGISTER. It specifies the horizontal count (in 1x clock cycles) at which to assert BLANK each scan line. Bit 0 is always a “0”, so the start of horizontal blanking may only be done with two pixel resolution. The leading edge of HSYNC is count 000H. TABLE 42. START H_BLANK HIGH REGISTER SUB ADDRESS = 31H BIT NO. 15-10 9-8 FUNCTION Reserved Assert BLANK Output Signal This 2-bit register is cascaded with Start H_Blank Low Register to form a 10-bit start_horizontal_blank register. It specifies the horizontal count (in 1x clock cycles) at which to assert BLANK each scan line. The leading edge of HSYNC is count 000H. TABLE 43. END H_BLANK REGISTER SUB ADDRESS = 32H BIT NO. 7-0 FUNCTION Negate BLANK Output Signal DESCRIPTION This 8-bit register specifies the horizontal count (in 1x clock cycles) at which to negate BLANKeach scan line. Bit 0 is always a “0”, so the end of horizontal blanking may only be done with two pixel resolution. The leading edge of HSYNC is count 000H. TABLE 44. START V_BLANK LOW REGISTER SUB ADDRESS = 33H BIT NO. 7-0 FUNCTION Assert BLANK Output Signal DESCRIPTION This 8-bit register is cascaded with Start V_Blank High Register to form a 9-bit start_vertical_blank register. It specifies the line number to assert BLANK each field. For NTSC operation, it occurs on line (n + 5) on odd fields and line (n + 268) on even fields. For PAL operation, it occurs on line (n + 5) on odd fields and line (n + 318) on even fields. RESET STATE 02H RESET STATE 7AH DESCRIPTION RESET STATE 000000B 11B RESET STATE 4AH DESCRIPTION RESET STATE 00B 000000B 33 HMP8115 TABLE 45. START V_BLANK HIGH REGISTER SUB ADDRESS = 34H BIT NO. 15-9 8 FUNCTION Reserved Assert BLANK Output Signal This 1-bit register is cascaded with Start V_Blank Low Register to form a 9-bit start_vertical_blank register. TABLE 46. END V_BLANK REGISTER SUB ADDRESS = 35H BIT NO. 7-0 FUNCTION Negate BLANK Output Signal DESCRIPTION This 8-bit register specifies the line number to negate BLANK each field. For NTSC operation, it occurs on line (n + 5) on odd fields and line (n + 268) on even fields. For PAL operation, it occurs on line (n + 5) on odd fields and line (n + 318) on even fields. TABLE 47. END HSYNC REGISTER SUB ADDRESS = 36H BIT NO. 7-0 FUNCTION Negate HSYNC Output Signal DESCRIPTION This 8-bit register specifies the horizontal count at which to negate HSYNC each scan line. Values may range from 0 (0000 0000) to 510 (1111 1111) CLK2 cycles. The leading edge of HSYNC is count 00H. TABLE 48. HSYNC DETECT WINDOW REGISTER SUB ADDRESS = 37H BIT NO. 7-0 FUNCTION Horizontal Sync Detect Window DESCRIPTION This 8-bit register specifies the width of the window (in 1x clock samples) to look for horizontal sync pulses each line. The window is centered about where the horizontal sync pulse should be located. If the horizontal sync pulse falls inside this window, the digital PLL will lock to it. If the horizontal sync pulse falls outside this window, the digital PLL is immediately reset to have the same timing. Recommend using a value of 20H to optimize the response time of the digital PLL. RESET STATE FFH RESET STATE 40H RESET STATE 12H DESCRIPTION RESET STATE 0000000B 1B 34 HMP8115 Pinout 80 LEAD PQFP TOP VIEW GND VCC DEC_T LAGC_CAP LCAP VCC NC NC GND HSYNC VSYNC GND VCC FIELD DVALID BLANK 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 AGND VAA AGND NC NTSC/PAL3 NTSC/PAL2 NTSC/PAL1 YIN YOUT AGND AGND VAA CLK2 VAA AGND AGND A/D_TEST NC C NC AGND AGND AGND AGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND VCC WPE GAIN_CNTL CCAP DEC_L VCC NC GND RESET GND GND VCC CLK2 GND SDA 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P15 P14 GND VBIVALID P13 VCC P12 P11 P10 P9 P8 GND VCC P7 P6 P5 P4 P3 GND P2 INTREQ P1 P0 SCL 35 HMP8115 Pin Description PIN NAME P0-P15 PIN NUMBER 42, 43, 45, 47-51, 54-58, 60, 63, 64 71 INPUT/ OUTPUT O Pixel output pins. See Table 3. DESCRIPTION HSYNC O Horizontal sync output. HSYNC is asserted during the horizontal sync intervals. The polarity of HSYNC is programmable. This pin is three-stated after a RESET or software reset and should be pulled high through a 10K resistor. Vertical sync output. VSYNC is asserted during the vertical sync intervals. The polarity of VSYNC is programmable. This pin is three-stated after a RESET or software reset and should be pulled high through a 10K resistor. FIELD output. The polarity of FIELD is programmable. This pin is three-stated after a RESET or software reset and should be pulled high through a 10K resistor. Composite blanking output. BLANK is asserted during the horizontal and vertical blanking intervals. The polarity of is programmable. This pin is three-stated after a RESET or software reset and should be pulled high through a 10K resistor. Data valid output. DVALID is asserted during CLK2 cycles that contain valid pixel data. This pin is three-stated after a RESET or software reset and should be pulled high through a 10K resistor. 2x pixel clock inputs. All CLK2 pins must be connected together. This clock must be a continuous, free-running clock. Reset control input. A logical zero for a minimum of four CLK2 cycles resets the device. RESET must be a logical one for normal operation. I2C interface data input/output. I2C interface clock input. White Peak Enable. When enabled (“1”), the video gain is reduced when the A/D output code exceeds 248. When disabled (“0”), the video amplifier will clip when the A/D output code reaches code 255. Vertical Blanking Interval Valid output. VBIVALID is asserted during CLK2 cycles that contain valid VBI (Vertical Blanking Interval) data such as Closed Captioning, Teletext, and Wide Screen Signalling data. The polarity of VBIVALID is programmable. This pin is three-stated after a RESET or software reset and should be pulled high through a 10K resistor. Interrupt Request Output. This is an open-drain output and requires an external 10K pull-up resistor to VCC. Composite Video Input. This input must be AC-coupled to the video signal (using a 1µF capacitor) and terminated with a 75Ω resistor, as shown in the Applications section. These components should be as close to this pin as possible for best performance. If not used, this pin should be connected to AGND through a 0.1µF capacitor. Composite Video Input. This input must be AC-coupled to the video signal (using a 1µF capacitor) and terminated with a 75Ω resistor, as shown in the Applications section. These components should be as close to this pin as possible for best performance. If not used, this pin should be connected to AGND through a 0.1µF capacitor. Composite video or Luminance (Y) video input. This input must be AC-coupled to the video signal (using a 1µF capacitor) and terminated with a 75Ω resistor, as shown in the Applications section. These components should be as close to this pin as possible for best performance. If not used, this pin should be connected to AGND through a 0.1µF capacitor. VSYNC 70 O FIELD 67 O BLANK 65 O DVALID 66 O CLK2 38, 13 I RESET 34 I SDA SCL WPE 40 41 27 I/O I I VBIVALID 61 O INTREQ 44 O NTSC/PAL 1 7 I NTSC/PAL 2 6 I NTSC/PAL 3 (Y) 5 I 36 HMP8115 Pin Description PIN NAME C (Continued) PIN NUMBER 19 INPUT/ OUTPUT I DESCRIPTION Chrominance (C) video input. This input must be AC-coupled to the video signal (using a 1µF capacitor) and terminated with a 75Ω resistor, as shown in the Applications section. These components, and the corresponding anti-aliasing lowpass filter, should be as close to this pin as possible for best performance. If not used, this pin should be connected to AGND through a 0.1µF capacitor. Analog output of the video multiplexer. This output should be lowpass filtered and input via the YIN pin, as shown in the Applications section. The anti-aliasing lowpass filter should be as close to YOUT and YIN as possible for best performance. Analog input to the ADC. Gain Control Input. A DC voltage is used to set the video amplifier’s gain, as shown in Figure 2. The reference circuit should be as close to this pin as possible for best performance. Decoupling for A/D Converter Reference. A 0.1µF capacitor should be connected between this pin and AGND, as shown in the Applications section. This capacitor should be as close to this pin as possible for best performance. Decoupling for A/D Converter Reference. A 0.1µF capacitor should be connected between this pin and AGND, as shown in the Applications section. This capacitor should be as close to this pin as possible for best performance. Capacitor connection for Luminance AGC Circuit. Controls the AGC loop time constant. A 0.01µF capacitor should be connected between this pin and AGND, as shown in the Applications section. This capacitor should be as close to this pin as possible for best performance. Capacitor connection for Luminance Clamp Circuit. Controls the clamp loop time constant. A 0.047µF capacitor should be connected between this pin and AGND, as shown in the Applications section. This capacitor should be as close to this pin as possible for best performance. Capacitor connection for Chrominance Clamp Circuit. Controls the clamp loop time constant. A 0.047µF capacitor should be connected between this pin and AGND, as shown in the Applications section. This capacitor should be as close to this pin as possible for best performance. Digital power supply pins. All VCC pins must be connected together. Digital ground pins. All GND pins must be connected together. YOUT 9 O YIN GAIN_CTRL 8 28 I I DEC_T 78 I DEC_L 30 I LAGC_CAP 77 I LCAP 76 I CCAP 29 I VCC GND 26, 31,37, 52, 59, 68, 75, 79 25, 33, 35, 36, 39, 46, 53, 62, 69, 72, 80 2, 12,14 1, 3, 10, 11, 15,16, 21, 22, 23, 24 17 4, 18, 20, 32, 73, 74 I I VAA AGND I I Analog power supply pins. All VAA pins must be connected together. Analog ground pins. All AGND pins must be connected together. A/D TEST NC O A/D test pin. This pin must be left floating for proper operation. No Connect pins. These pins must be left floating for proper operation. 37 HMP8115 Applications Information PCB LAYOUT CONSIDERATIONS A PCB board with a minimum of 4 layers is recommended, with layers 1 and 4 (top and bottom) for signals and layers 2 and 3 for power and ground. The PCB layout should implement the lowest possible noise on the power and ground planes by providing excellent decoupling. The optimum layout places the HMP8115 as close as possible to the power supply connector and the video input connector. Component Placement External components should be positioned as close as possible to the appropriate pin, ideally such that traces can be connected point to point. Chip capacitors are recommended where possible, with radial lead ceramic capacitors the second-best choice. Power supply decoupling should be done using a 0.1µF ceramic capacitor in parallel with a 0.01µF chip capacitor for each group of VAA and VCC pins to ground. These capacitors should be located as close to the power and ground pins as possible, using short, wide traces. Digital Ground Plane All GND pins on the HMP8115 should be connected to the digital ground plane of the board. Analog Ground Plane A separate analog ground plane for the HMP8115 is recommended. All AGND pins on the HMP8115 should be connected to the analog ground plane. This analog ground plane should be connected to the board’s digital ground plane at a single point. Analog Power Plane The HMP8115 should have its own VAA power plane that is isolated from the common power plane of the board, with a gap between the two power planes of at least 1/8 inch. All VAA pins on the HMP8115 must be connected to this analog power plane. The analog power plane should be connected to the board’s normal VCC power plane at a single point though a low-resistance ferrite bead, such as a Ferroxcube 5659065-3B, Fair-Rite 2743001111, or TDK BF45-4001. The ferrite bead provides resistance to switching currents, improving the performance of HMP8115. A single 47µF capacitor should also be used between the analog power plane and the ground plane to control low-frequency power supply ripple. If a separate linear regulator is used to provide power to the analog power plane, the power-up sequence should be designed to ensure latchup will not occur. A separate linear regulator is recommended if the power supply noise on the VAA pins exceeds 200mV. Analog Signals Traces containing digital signals should not be routed over, under, or adjacent to the analog output traces to minimize crosstalk. If this is not possible, coupling can be minimized by routing the digital signals at a 90 degree angle to the analog signals. The analog input traces should also not overlay the VAA power plane to maximize high-frequency power supply rejection. EVALUATION BOARD HMPVIDEVAL/ISA The HMPVIDEVAL/ISA evaluation board allows connecting the HMP8115 into a PC ISA slot for evaluation. It includes the HMP8115 NTSC/PAL decoder, 3MB of VRAM, and a NTSC/PAL encoder. The board accepts composite or S-video input and displays video on a standard TV. The ISA bus and evaluation software allow easy performance evaluation of the HMP8115 using tools such as the Tektronix VM700 video test system. RELATED APPLICATION NOTES Application Notes are also available on the Intersil Multimedia web site at http://www.semi.harris.com/mmedia. AN9644: Composite Video Separation Techniques AN9716: Widescreen Signalling (WSS) AN9717: YCbCr to RGB Considerations AN9728: BT.656 Video Interface for ICs AN9738: Video Module Interface (VMI) for ICs 38 HMP8115 U1 NTSC-PAL1 NTSC-PAL2 NTSC-PAL3/Y R3 75 R2 75 R1 75 ANTI-ALIAS FILTER CHROMA R4 75 C4 1.0µF ANTI-ALIAS FILTER 8 9 77 C5 0.01µF 76 C6 0.047µF C7 0.047µF 29 YIN YOUT LAGC_CAP LCAP CCAP 19 C C1 C2 C3 1.0µF 6 1.0µF 1.0µF 7 NTSC/PAL 1 NTSC/PAL 2 P7 P6 P5 P4 P3 P2 P1 P0 P15 P14 P13 P12 P11 P10 P9 P8 BLANK DVALID FIELD HSYNC VSYNC VBIVALID INTREQ 78 C8 0.1µF C9 0.01µF C10 0.1µF 30 C11 0.01µF VAA R5 1K R6 750 28 DEC_T DEC_L RESET SDA SCL CLK2 CLK2 TEST 51 50 49 48 47 45 43 42 64 63 60 58 57 56 55 54 65 66 67 71 70 61 44 34 40 41 38 13 36 RESET VCC P[7..0] 5 NTSC/PAL 3 P[15..8] VCC VCC RP1 10K R16 4K R17 4K BLANK DVALID FIELD HSYNC VSYNC VBIVALID INTREQ 27MHz R8 50 C12 15pF SDA SCL 27MHz VAA R7 10K JP1 JUMPER GAIN_CNTL WPE 27 FIGURE 22. HMP8115 REFERENCE SCHEMATICS 39 HMP8115 Absolute Maximum Ratings Digital Supply Voltage (VCC to GND) . . . . . . . . . . . . . . . . . . . . 7.0V Analog Supply Voltage (VAA to GND) . . . . . . . . . . . . . . . . . . . . 7.0V Digital Input Voltages . . . . . . . . . . . . . . . GND - 0.5V to VCC + 0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Information Thermal Resistance (Typical, See Note 42) θJA (oC/W) PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Maximum Power Dissipation HMP8115CN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9W Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Junction Temperatures . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Temperature Range HMP8115CN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 42. θJA is measured with the component mounted on an evaluation PC board in free air. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. Electrical Specifications PARAMETER VCC = VAA = 5.0V, TA = 25oC SYMBOL TEST CONDITION MIN TYP MAX UNITS POWER SUPPLY CHARACTERISTICS Power Supply Voltage Range Total Power Supply Current Digital Power Supply Current Analog Power Supply Current Total Power Dissipation VCC, VAA ITOT ICC IAA PTOT CLK2 = 29.5MHz, VCC = VAA = 5.25V, Outputs Not Loaded (Note 43) CLK2 = 29.5MHz, VCC = VAA = 5.25V Outputs Not Loaded 4.75 5 280 105 175 1.47 5.25 315 115 200 1.66 V mA mA mA W DC CHARACTERISTICS: DIGITAL I/O (EXCEPT CLK2 and I2C INTERFACE) Input Logic High Voltage Input Logic Low Voltage Output Logic High Voltage Output Logic Low Voltage Input Leakage Current VIH VIL VOH VOL IIH, IIL CIN, COUT VCC = Max VCC = Min IOH = -4mA, VCC = Max IOL = 4mA, VCC = Min VCC = Max Input = 0V or 5V f = 1MHz, (Note 43) All Measurements Referenced to Ground, TA = 25oC 2.0 2.4 0.8 0.4 10 V V V V µA Input/Output Capacitance - 8 - pF Three-State Output Current Leakage IOZ - - 10 µA DC CHARACTERISTICS: CLK2 DIGITAL INPUT Input Logic High Voltage Input Logic Low Voltage Input Leakage Current VIH VIL IIH IIL Input Capacitance CIN VCC = Max VCC = Min VCC = Max Input = 0V or VCC CLK2 = 1MHz, (Note 43) All Measurements Referenced to Ground, TA = 25oC 0.7xVCC - 450 8 0.3xVCC 10 V V µA µA pF 40 HMP8115 Electrical Specifications PARAMETER VCC = VAA = 5.0V, TA = 25oC (Continued) SYMBOL TEST CONDITION MIN TYP MAX UNITS DC CHARACTERISTICS: I2C INTERFACE Input Logic High Voltage Input Logic Low Voltage Output Logic High Voltage Output Logic Low Voltage Input Leakage Current VIH VIL VOH VOL IIH, IIL CIN, COUT VCC = Max VCC = Min IOH = -1mA, VCC = Max IOL = 3mA, VCC = Min VCC = Max Input = 0V or 5V SCL = 400kHz, (Note 43) All Measurements Referenced to GND, TA = 25oC 0.7xVCC 3.0 0 0.3xVCC 0.4 10 V V V V µA Input/Output Capacitance - 8 - pF AC CHARACTERISTICS: DIGITAL I/O (EXCEPT I2C INTERFACE) CLK2 Frequency CLK2 Waveform Symmetry CLK2 Pulse Width High CLK2 Pulse Width Low Data and Control Setup Time Data and Control Hold Time CLK2 to Output Delay Data and Control Rise/Fall Time AC CHARACTERISTICS: I2C INTERFACE SCL Clock Frequency SCL Pulse Width Low SCL Pulse Width High Data Hold Time Data Setup Time SDA, SCL Rise Time SDA, SCL Fall Time ANALOG INPUT PERFORMANCE Composite Video Input Amplitude (Sync Tip to White Level) Luminance (Y) Video Input Amplitude (Sync Tip to White Level) Chrominance (C) Video Input Amplitude (Burst Amplitude) Video Input Impedance RAIN Input Termination of 75Ω and 1.0µF AC-Coupled Input Termination of 75Ω and 1.0µF AC-Coupled Input Termination of 75Ω and 1.0µF AC-Coupled, (Note 43) Note 43 0.5 1.0 2.0 VP-P VP-P fSCL tLOW tHIGH tHD:DATA tSU:DATA tR tF (Note43) 0 1.3 0.6 0 100 400 300 300 kHz µs µs ns ns ns ns tPWH tPWL tSU tHD tDVLD tr, tf (Note 43) (Note 44) (Note 43) 20 40 13 13 10 0 0 5 2 29.5 60 8 6 MHz % ns ns ns ns ns ns 0.5 1.0 2.0 0.143 0.286 0.6 VP-P kΩ 200 - - 41 HMP8115 Electrical Specifications PARAMETER Video Input Bandwidth VCC = VAA = 5.0V, TA = 25oC (Continued) SYMBOL BW TEST CONDITION 1VP-P Sine Wave Input to -3dBc Reduction, (Note 43) MIN 5 TYP MAX UNITS MHz ADC Input Range AIN FULL SCALE AIN OFFSET Best Fit Linearity - 1 1.5 2 0.35 - VP-P V LSB LSB ADC Integral Nonlinearity ADC Differential Nonlinearity VIDEO PERFORMANCE Differential Gain Differential Phase Hue Accuracy Color Saturation Accuracy Luminance Nonlinearity SNR GENLOCK PERFORMANCE Horizontal Locking Time INL DNL DG DP Modulated Ramp (Note 43) - 2 1 2 2 2 50 - % Deg. Deg. % % 75% Color Bars (Note 43) - NTC-7 Composite (Note 43) SNRL WEIGHTED Pedestal Input (Note 43) - dB tLOCK Time from Initial Lock Acquisition to an Error of 1 Pixel. (Note 43) Range over specified pixel jitter is maintained. Assumes line time changes by amount indicated slowly between over one field. (Note 43) 2 3 - Fields Long-Term horizontal Sync Lock Range - - 5 % Number of Missing Horizontal Syncs Before Lost Lock Declared Number of Missing Vertical Syncs Before Lost Lock Declared Long-Term Color Subcarrier Lock Range HSYNC LOST VSYNC LOST Programmable via register 04H (Note 43) 1 or 12 1 or 12 1 or 12 Hsyncs 1 or 3 1 or 3 ±200 1 or 3 ±400 Vsyncs Range over color subcarrier locking time and accuracy specifications are maintained. Subcarrier frequency changes by amount indicated slowly over 24 hours. (Note 43) (Notes 43, 45) - Hz Vertical Sample Alignment - 1/8 10 - Pixel ns NOTES: 43. Guaranteed by design or characterization. 44. Test performed with CL = 40pF, IOL = 4mA, IOH = -4mA. Input reference level is 1.5V for all inputs. VIH = 3.0V, VIL = 0V. 45. This should not be confused with Clock Jitter, since the HMP8115 does not generate the sample clock. Thus, clock jitter is solely dependent on the source of the CLK2 signal. The Vertical Sample Alignment parameter specifies how accurately samples align vertically from one scan line to the next. 42 HMP8115 Metric Plastic Quad Flatpack Packages (MQFP/PQFP) D D1 -D- Q80.14x20 (JEDEC MO-108CB-1 ISSUE A) 80 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE SYMBOL A A1 A2 INCHES MIN 0.010 0.100 0.012 0.012 0.904 0.783 0.667 0.547 0.026 80 0.032 BSC 24 16 MAX 0.134 0.120 0.018 0.016 0.923 0.791 0.687 0.555 0.037 MILLIMETERS MIN 0.25 2.55 0.30 0.30 22.95 19.90 16.95 13.90 0.65 80 0.80 BSC 24 16 MAX 3.40 3.05 0.45 0.40 23.45 20.10 17.45 14.10 0.95 NOTES 6 3 4, 5 3 4, 5 7 Rev. 0 1/94 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- . 4. Dimensions D1 and E1 to be determined at datum plane -H- . 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 0.13/0.23 0.005/0.009 -AE E1 -B- B B1 D D1 E e PIN 1 SEATING A PLANE 0.10 0.004 0.40 0.016 MIN 0o MIN A2 A1 0o-7o 0.13/0.17 0.005/0.007 BASE METAL WITH PLATING 5o-16o 0.20 A-B S 0.008 M C -CDS B B1 E1 L N e -H- ND NE L 5o-16o 6. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. “N” is the number of terminal positions. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. 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