HMU17

HMU16, HMU17 TM Data Sheet November 1999 File Number 2803.4 16 x 16-Bit CMOS Parallel Multipliers itle MU , U1 bt x -Bit OS ralltiers) utho ) eyrds terrpoion, inctor, ralltier, C, gi, P, el ncn, send, The HMU16 and HMU17 are high speed, low power CMOS 16-bit x 16-bit multipliers ideal for fast, real time digital signal processing applications. The X and Y operands along with their mode controls (TCX and TCY) have 17-bit input registers. The mode controls independently specify the operands as either two’s complement or unsigned magnitude format, thereby allowing mixed mode multiplication operations. Two 16-bit output registers are provided to hold the most and least significant halves of the result (MSP and LSP). For asynchronous output, these registers may be made transparent through the use of the Feedthrough Control (FT). Additional inputs are provided for format adjustment and rounding. The Format Adjust control (FA) allows the user to select either a left shifted 31-bit product or a full 32-bit product, whereas the round control (RND) provides the capability of rounding the most significant portion of the result. The HMU16 has independent clocks (CLKX, CLKY, CLKL, CLKM) associated with each of these registers to maximize throughput and simplify bus interfacing. The HMU17 has only a single clock input (CLK), but makes use of three register enables (ENX, ENY and ENP). The ENX and ENY inputs control the X and Y Input Registers, while ENP controls both the MSP and LSP Output Registers. This configuration facilitates the use of the HMU17 for microprogrammed systems. The two halves of the product may be routed to a single 16-bit three-state output port via a multiplexer, and in addition, the LSP is connected to the Y-input port through a separate three-state buffer. Features • 16 x 16-Bit Parallel Multiplier with Full 32-Bit Product • High-Speed (35ns) Clocked Multiply Time • Low Power Operation - ICCSB = 500µA Maximum - ICCOP = 7.0mA Maximum at 1MHz • Supports Two’s Complement, Unsigned Magnitude and Mixed Mode Multiplication • HMU16 is Compatible with the AM29516, LMU16, IDT7216 and the CY7C516 • HMU17 is Compatible with the AM29517, LMU17, IDT7217 and the CY7C517 • TTL Compatible Inputs/Outputs • Three-State Outputs Applications • Fast Fourier Transform Analysis • Digital Filtering • Graphic Display Systems • Image Processing • Radar and Sonar • Speech Synthesis and Recognition Ordering Information PART NUMBER HMU16JC-35 HMU16JC-45 HMU16GC-35 HMU16GC-45 HMU17JC-35 HMU17JC-45 HMU17GC-35 HMU17GC-45 TEMP. RANGE ( oC) 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 PACKAGE 68 Ld PLCC 68 Ld PLCC 68 Ld CPGA 68 Ld CPGA 68 Ld PLCC 68 Ld PLCC 68 Ld CPGA 68 Ld CPGA PKG. NO. N68.95 N68.95 G68.B G68.B N68.95 N68.95 G68.B G68.B 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2001, All Rights Reserved HMU16, HMU17 Pinouts 68 LEAD PLCC TOP VIEW NC CLKM (ENP) OEP FA FT MSPSEL GND GND VCC VCC TCY TCX RND CLKX (ENX) X15 X14 X13 9 8 7 6 5 4 3 2 1 6867666564636261 P15, P31 P14, P30 P13, P29 P12, P28 P11, P27 P10, P26 P9, P25 P8, P24 P7, P23 P6, P22 P5, P21 P4, P20 P3, P19 P2, P18 P1, P17 P0, P16 NC 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27282930313233 34 35 36 37 38 39 40 41 42 43 Y15, P15 Y14, P14 Y13, P13 Y12, P12 Y11, P11 Y10, P10 Y9, P9 Y8, P8 Y7, P7 Y6, P6 Y5, P5 Y4, P4 Y3, P3 Y2, P2 Y1, P1 Y0, P0 NC 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 NC X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 OEL CLKL (CLK) CLKY (ENY) 68 LEAD CPGA TOP VIEW 11 N/C X13 X15 CLKX (ENX) RND TCY VCC GND MSP SEL FT OEP CLKM (ENP) P30/ P14 P28/ P12 P26/ P10 P24/ P8 P22/ P6 P20/ P4 P18/ P2 Y2/P2 Y4/P4 Y6/P6 Y8/P8 Y10/ P10 Y11/ P11 G Y12/ P12 Y13/ P13 H Y14/ P14 Y15/ P15 J P16/ P0 N/C K L 10 X11 X12 X14 TCX VCC GND FA N/C P31/ P15 P29/ P13 P27/ P11 P25/ P9 P23/ P7 P21/ P5 P19/ P3 P17/ P1 9 X9 X10 8 X7 X8 7 X5 X6 6 X3 X4 5 X1 X2 4 OEL CLKY (ENY) N/C X0 CLKL (CLK) Y0/P0 3 2 1 A Y1/P1 B Y3/P3 Y5/P5 C D Y7/P7 Y9/P9 E F 2 HMU16, HMU17 Functional Block Diagrams HMU16 X0 - 15 TCX RND TCY Y0 - 15/PO - 15 REGISTER REGISTER REGISTER OEL CLKX CLKY MULTIPLIER ARRAY FA FT CLKM CLKL MSPSEL OEP FORMAT ADJUST MSP RESISTER LSP RESISTER MULTIPLEXER P16 - 31/PO - 15 HMU17 X0 - 15 TCX TCX RND TCY Y0 - 15/PO - 15 REGISTER REGISTER REGISTER CLK ENX ENY MULTIPLIER ARRAY OEL FA FT FORMAT ADJUST MSP RESISTER LSP RESISTER ENP MSPSEL MULTIPLEXER OEP P16 - 31/PO - 15 3 HMU16, HMU17 Pin Description SYMBOL VCC GND X0-X15 Y0-Y15/ P0-P15 P16-P31/ P0-P15 TCY, TCX FT FA PLCC PIN NUMBER 1, 68 2, 3 47-59, 61-63 27-42 I I/O TYPE DESCRIPTION VCC. The +5V power supply pins. A 0.1µ F capacitor between the VCC and GND pins is recommended. GND. The device ground. X-Input Data. These 16 data inputs provide the multiplicand which may be in two's complement or unsigned magnitude format. Y-Input/LSP Output Data. This 16-bit port is used to provide the multiplier which may be in two's complement or unsigned magnitude format. It may also be used for output of the Least Significant Product (LSP). Output Data. This 16-bit port may provide either the MSP (P16-31) or the LSP (P0-15). Two's Complement Control. Input data is interpreted as two's complement when this control is HIGH. A LOW indicates the data is to be interpreted as unsigned magnitude format. Feed through Control. When this control is HIGH, both the MSP and LSP Registers are transparent. When LOW, the registers are latched by their associated clock signals. Format Adjust Control. A full 32-bit product is selected when this control line is HIGH. A LOW on this control line selects a left shifted 31-bit product with the sign bit replicated in the LSP. This control is normally HIGH, except for certain two's complement integer and fractional applications. Round Control. When this control is HIGH, a one is added to the Most Significant Bit (MSB) of the LSP. This position is dependent on the FA control; FA = HIGH indicates RND adds to the 2-15 bit (P15), and FA = LOW indicates RND adds to the 2-16 bit (P14). Output Multiplexer Control. When this control is LOW, the MSP is available for output at the dedicated output port, and the LSP is available at the Y-input/LSP output port. When MSPSEL is HIGH, the LSP is available at both ports and the MSP is not available for output. Y-In/P0-15 Output Port Three-State Control. When OEL is HIGH, the output drivers are in the high impedance state. This state is required for Ydata input. When OEL is LOW, the port is enabled for LSP output. P16-31/P0-15 Output Port Three-State Control. A LOW on this control line enables the output port. When OEP is HIGH, the output drivers are in the high impedance state. 10-25 66, 67 5 6 O I I I RND 65 I MSPSEL 4 I OEL 46 I OEP 7 I THE FOLLOWING PIN DESCRIPTIONS APPLY TO THE HMU16 ONLY CLKX CLKY CLKM CLKL 64 44 8 45 I I I I X-Register Clock. The rising edge of this clock loads the X-data Input Register along with the TCX and RND Registers. Y-Register Clock. The rising edge of this clock loads the Y-data Input Register along with the TCY and RND Registers. MSP Register Clock. The rising edge of CLKM loads the Most Significant Product (MSP) Register. LSP Register Clock. The rising edge of CLKL loads the Least Significant Product (LSP) Register. THE FOLLOWING PIN DESCRIPTIONS APPLY TO THE HMU17 ONLY CLK ENX ENY ENP 45 64 44 8 I I I I Clock. The rising edge of this clock will load all enabled registers. X-Register Enable. When ENX is LOW, the X-register is enabled; X-input data and TCX will be latched at the rising edge of CLK. When ENX is high, the X-register is in a hold mode. Y-Register Enable. ENY enables the Y-register. (See ENX). Product Register Enable. ENP enables the Product Register. Both the MSP and LSP Sections are enabled by ENP. (See ENX). 4 HMU16, HMU17 Functional Description The HMU16/HMU17 are high speed 16 x 16-bit multipliers designed to perform very fast multiplication of two 16-bit binary numbers. The two 16-bit operands (X and Y) may be independently specified as either two's complement or unsigned magnitude format by the two's complement controls (TCX and TCY). When either of these control lines is LOW, the respective operand is treated as an unsigned 16-bit value; and when it is HIGH, the operand is treated as a signed value represented in two's complement format. The operands along with their respective controls are latched at the rising edge of the associated clock signal. The HMU16 accomplishes this through the use of independent clock inputs for each of the Input Registers (CLKX and CLKY), while the HMU17 utilizes a single clock signal (CLK) along with the X and Y register enable inputs (ENX and ENY). Input controls are also provided for rounding and format adjustment of the 32-bit product. The Round input (RND) is provided to accommodate rounding of the most significant portion of the product by adding one to the Most Significant Bit (MSB) of the LSP Register. The position of the MSB is dependent on the state of the Format Adjust Control (see Pin Descriptions and Multiplier Input/Output Format Tables). The Round input is latched into the RND Register whenever either of the input registers is clocked. The Format Adjust control (FA) allows the product output to be formatted. When the FA control is HIGH, a full 32-bit product is output; and when FA is LOW, a left-shifted 31-bit product is output with the sign bit replicated in bit position 15 of the LSP. The FA control must be HIGH for unsigned magnitude, and mixed mode multiplication operations. It may be LOW for certain two's complement integer and fractional operations only (see Multiplier Input/ Output Formats Table). The HMU16/HMU17 multipliers are equipped with two 16-bit Output Registers (MSP and LSP) which are provided to hold the most and least significant portions of the resultant product respectively. The HMU16 uses independent clocks (CLKM and CLKL) for latching the two output registers, while the HMU17 uses a single clock input (CLK) along with the Product Latch Enable (ENP). The MSP and LSP Registers may also be made transparent for asynchronous output through the use of the Feed through Control (FT). There are two output configurations which may be selected when using the HMU16/HMU17 multipliers. The first configuration allows the simultaneous access of the most and least significant halves of the product. When the MSPSEL input is LOW, the Most Significant Product will be available at the dedicated output port (P16-31/P0-15). The Least Significant Product is simultaneously available at the bidirectional port shared with the Y-inputs (Y0-15/P0-15) through the use of the LSP output enable (OEL). The other output configuration involves multiplexing the MSP and LSP Registers onto the dedicated output port through the use of the MSPSEL control. When the MSPSEL control is LOW, the Most Significant Product will be available at the dedicated output port; and when MSPSEL is HIGH, the Least Significant Product will be available at this port. This configuration allows access of the entire 32-bit product by a 16-bit wide system bus. 5 Multiplier Input/Output Formats BINARY POINT X15 X14 X13 X12 X11 X10 X9 X8 X7 X4 X1 DIGIT VALUE X3 X2 X0 SIGNAL 2-8 2-9 2-10 2-11 2-12 2 -13 2-14 2-15 2-7 X6 X5 2-5 2-6 -20 2-1 2-2 2-3 2-4 X 2-5 DIGIT VALUE 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2 -13 2-14 2-15 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y4 Y3 Y1 Y0 Y2 Y6 Y5 SIGNAL 6 P8 P7 P6 P5 P4 P3 P2 P1 P0 2-5 MSP P8 P7 P6 P5 P4 P3 LSP P2 P1 P0 2-6 2-7 2-8 2-6 MSP LSP 2-7 2-8 2 -9 2-10 2-11 2 -12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2 -20 2 -21 2-22 2-23 2-24 2-25 2-26 2-27 2 -28 2-29 2-30 X8 X7 X4 X1 DIGIT VALUE X3 X0 2-9 2-10 2-11 2 -12 2-13 2 -14 2-15 2-16 X2 2-8 X6 X5 SIGNAL 2-6 2-7 Y8 Y7 Y4 Y1 Y3 Y0 2-9 2-10 2-11 2 -12 2-13 2 -14 2-15 2-16 Y2 2-8 Y6 Y5 SIGNAL DIGIT VALUE 2-6 2-7 P8 P7 P6 P5 P4 P3 P2 P1 2-6 MSP 2-7 2-8 LSP -2 -0 2-1 2-2 2-3 2-4 *= P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 SIGNAL FA = 0 DIGIT VALUE -20 2-1 2-2 2-3 2-4 2-9 2-10 2-11 2-12 2 -13 2-14 2-15 -20 2-16 2-17 2-18 2-19 2-20 2 -21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-30 = P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 SIGNAL FA = 1 DIGIT VALUE -21 20 2-1 2-2 2-3 2-4 2-5 HMU16, HMU17 FIGURE 1. FRACTIONAL TWO’S COMPLEMENT NOTATION NOTE: In this format an overflow occurs in the attempted multiplication of the two's complement number 1,000 . . . 0 with 1,000 . . . 0 yielding an erroneous product of -1 in the fraction case and -230 in the integer case. BINARY POINT X15 X14 X13 X12 X11 X10 X9 2-1 2-2 2-3 2-4 2-5 X Y15 Y14 Y13 Y12 Y11 Y10 Y9 2-1 2-2 2-3 2-4 2-5 = P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P0 SIGNAL DIGIT VALUE FA = 1 MANDATORY 2-1 2-2 2-3 2-4 2-5 2-9 2-10 2-11 2-12 2-13 2 -14 2-15 2-16 2 -17 2-18 2-19 2-20 2-21 2 -22 2 -23 2-24 2-25 2-26 2-27 2-28 2-29 2-30 2-31 2-32 FIGURE 2. FRACTIONAL UNSIGNED MAGNITUDE NOTATION Multiplier Input/Output Formats (Continued) BINARY POINT X15 X14 X13 X12 X11 X10 X9 X8 X7 X4 X1 DIGIT VALUE X3 X2 X0 2-8 2-9 2 -10 2-11 2-12 2 -13 2-14 2-15 2-7 X6 X5 SIGNAL (TWO’S COMPLEMENT) -20 2-1 2-2 2-3 2-4 2-5 2-6 X 2-6 DIGIT VALUE 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y4 Y1 Y3 Y2 Y0 Y7 Y6 Y5 SIGNAL (UNSIGNED MAGNITUDE) 2-1 2-2 2-3 2-4 2 -5 7 P8 P7 P6 P5 P4 P3 P2 P1 P0 2-6 MSP LSP 2-7 2-8 2-9 2-10 2-11 2-12 2 -13 2-14 2-15 2 -16 2-17 2 -18 2-19 2-20 2-21 2 -22 2-23 2-24 2-25 2 -26 2-27 2-28 2 -29 2-30 2-31 = P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 SIGNAL DIGIT VALUE FA = 1 MANDATORY -20 2 -1 2-2 2-3 2-4 2-5 FIGURE 3. FRACTIONAL MIXED MODE NOTATION BINARY POINT X15 X14 X13 X12 X11 X10 X9 -2 15 214 213 212 211 2 10 29 X8 28 X7 27 X6 26 X5 25 X4 24 X3 23 X2 22 X1 21 X0 20 SIGNAL DIGIT VALUE HMU16, HMU17 X Y15 Y14 Y13 Y12 Y11 Y10 Y9 -2 15 214 213 212 211 2 10 29 Y8 28 Y7 27 Y6 26 Y5 25 Y4 2-4 Y3 23 Y2 22 Y1 21 Y0 20 SIGNAL DIGIT VALUE = MSP P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 29 P8 28 P7 27 LSP P6 26 P5 25 P4 24 P3 23 P2 22 P1 21 P0 20 SIGNAL DIGIT VALUE FA = 0 -2 30 2 29 228 227 2 26 225 224 223 222 221 2 20 2 19 218 2 17 2 16 215 -230 214 213 2 12 211 210 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 29 P8 28 P7 27 LSP P6 26 P5 25 P4 24 P3 23 P2 22 P1 21 P0 20 SIGNAL DIGIT VALUE FA = 1 -2 31 2 30 229 228 2 27 226 225 224 223 222 2 21 2 20 219 2 18 2 17 216 215 214 2 13 2 12 211 210 MSP FIGURE 4. INTEGER TWO’S COMPLEMENT NOTATION NOTE: In this format an overflow occurs in the attempted multiplication of the two's complement number 1,000 . . . 0 with 1,000 . . . 0 yielding an erroneous product of -1 in the fraction case and -230 in the integer case. Multiplier Input/Output Formats (Continued) BINARY POINT X15 X14 X13 X12 X11 X10 X9 X8 X7 X4 X1 21 20 DIGIT VALUE 24 23 22 X3 X0 SIGNAL 27 26 25 X2 28 X6 X5 215 214 213 212 2 11 2 10 29 X 215 214 213 212 2 11 2 10 29 28 27 26 25 24 23 22 21 20 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y4 Y1 Y3 Y0 Y2 Y6 Y5 SIGNAL DIGIT VALUE 8 P8 28 LSP 27 26 25 24 23 P7 P6 P5 P4 P3 P2 22 P1 21 220 2 19 218 217 216 215 214 213 2 12 211 2 10 29 MSP = P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P0 20 SIGNAL DIGIT VALUE FA = 1 MANDATORY 231 230 229 228 2 27 2 26 225 224 223 222 2 21 FIGURE 5. INTEGER UNSIGNED MAGNITUDE NOTATION BINARY POINT X15 X14 X13 X12 X11 X10 X9 X8 28 27 X7 -215 214 213 212 211 210 29 X6 26 X5 25 X4 24 X3 23 X2 22 X1 21 X0 20 SIGNAL (TWO’S COMPLEMENT) DIGIT VALUE HMU16, HMU17 SIGNAL (UNSIGNED MAGNITUDE) Y8 29 28 Y7 27 Y6 26 Y5 25 Y4 24 Y3 23 Y2 22 Y1 21 Y0 20 DIGIT VALUE X Y15 Y14 Y13 Y12 Y11 Y10 Y9 2 15 214 213 212 211 210 = MSP P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 29 P8 28 P7 27 LSP P6 26 P5 25 P4 24 P3 23 P2 22 P1 21 P0 20 SIGNAL DIGIT VALUE FA = 1 MANDATORY -231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 2 11 210 FIGURE 6. INTEGER MIXED MODE NOTATION HMU16, HMU17 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage Applied . . . . . GND 0.5V to VCC +0.5V Storage Temperature Range . . . . . . . . . . . . . . . . . . . 65oC to 150oC Thermal Information Thermal Resistance (Typical, Note 1) θJA(oC/W) θJC (oC/W) PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . 43.2 15.1 CPGA . . . . . . . . . . . . . . . . . . . . . . . . . . 42.69 10.0 Maximum Package Power Dissipation at 70oC PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.7W CPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.46 Maximum Junction Temperature PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC CPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . . 300oC Operating Conditions Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4500 Gates CAUTION: Stresses above those listed in the ``Absolute Maximum Ratings'' may cause permanent damage to the device. This is a stress only rating, and operation at these or any other conditions above those indicated in the operations sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications PARAMETER Logical One Input Voltage Logical Zero Input Voltage Output High Voltage Output Low Voltage Input Leakage Current Output or I/O Leakage Current Standby Power Supply Current Operating Power Supply Current NOTE: VCC = 5.0V ±5%, TA = 0oC to 70oC SYMBOL VIH VIL VOH VOL II IO ICCSB ICCOP TEST CONDITIONS VCC = 5.25V VCC = 4.75V IOH = 400mA, VCC = 4.75V IOL = +4.0mA, VCC = 4.75V VI = VCC or GND, V CC = 5.25V VO = VCC or GND, V CC = 5.25V VI = VCC or GND, V CC = 5.25V Outputs Open VI = VCC or GND, V CC = 5.25V f = 1MHz (Note 2) MIN 2.0 2.6 10 10 MAX 0.8 0.4 10 10 500 7.0 UNITS V V V V µA µA µA mA 2. Operating Supply Current is proportional to frequency, Typical rating is 5mA/MHz. Capacitance TA = 25oC, Note 3 PARAMETER Input Capacitance Output Capacitance I/O Capacitance NOTE: 3. Not tested, but characterized at initial design and at major process/design changes. SYMBOL CIN COUT CI/O TEST CONDITIONS Frequency = 1MHz. All measurements referenced to device ground. TYPICAL 15 10 10 UNITS pF pF pF 9 HMU16, HMU17 AC Electrical Specifications VCC = 5.0V ±5%, TA = 0oC to 70oC, Note 6 TEST CONDITIONS HMU16/HMU17-35 MIN 15 2 10 10 Note 4 15 2 Note 5 0 MAX 55 35 22 22 22 22 22 HMU16/HMU17-45 MIN 18 2 15 15 15 2 0 MAX 70 45 25 25 25 25 25 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns PARAMETER Unclocked Multiply Time Clocked Multiply Time X, Y, RND Setup Time X, Y, RND Hold Time Clock Pulse Width High Clock Pulse Width Low MSPSEL to Product Out Output Clock to P Output Clock to Y Three-State Enable Time Three-State Disable Time Clock Enable Setup Time (HMU17 Only) Clock Enable Hold Time (HMU17 Only) Clock Low Hold Time CLKXY Relative to CLKML (HMU16 Only) Output Rise Time Output Fall Time NOTES: SYMBOL tMUC tMC tS tH tPWH tPWL tPDSEL tPDP tPDY tENA tDIS tSE tHE tHCL tr tf From 0.8V to 2.0V From 2.0V to 0.8V - 8 8 - 8 8 ns ns 4. Transition is measured at ±200mV from steady state voltage with loading specified in AC Test Circuit, V1 = 1.5V, R1 = 500Ω and C1 = 40pF. 5. To ensure the correct product is entered in the output registers, new data may not be entered into the input registers before the output registers have been clocked. 6. Refer to AC Test Circuit, with V1 = 2.4V, R1 = 500Ω and C1 = 40pF. AC Test Circuit V1 R1 AC Testing Input, Output Waveforms 0.3V DUT C1 (SEE NOTE) 0V 1.5V 1.5V VOH VOL NOTE: Includes Stray and Jig Capacitance. NOTE: AC Testing: All parameters tested as per test circuit. Input rise and fall times are driven at 1ns/V. 10 HMU16, HMU17 Timing Diagrams 3.0V 1.5V 0V 3.0V 1.5V 0V THREE STATE CONTROL tDIS OUTPUT THREE STATE tENA 1.5V DATA INPUT tS tH CLOCK INPUT HIGH IMPEDANCE 1.7V 1.3V FIGURE 7. SETUP AND HOLD TIME FIGURE 8. THREE-STATE CONTROL tPWH CLK tPWH CLKX CLKY INPUT XI YI RND CLKM CLKL OUTPUT Y tS tH tHCL tPWL ENX ENY INPUT XI YI RND tSE tS tHE tH tPWL tMC tPDY tSE ENP tMC tHE tPDY tPDSEL MSPSEL tPDP OUTPUT P tMUC OUTPUT Y tPDSEL MSPSEL tPDP OUTPUT P tMUC FIGURE 9. HMU16 TIMING DIAGRAM FIGURE 10. HMU17 TIMING DIAGRAM 11 HMU16, HMU17 Ceramic Pin Grid Array Packages (CPGA) D S1 D1 –A– G68.B MIL-STD-1835 CMGA3-P68D (P-AC) 68 LEAD CERAMIC PIN GRID ARRAY PACKAGE INCHES SYMBOL A A1 b MIN 0.215 0.070 0.016 0.016 0.042 1.140 MAX 0.345 0.145 0.0215 0.020 0.058 0.080 1.180 MILLIMETERS MIN 5.46 1.78 0.41 0.41 1.07 28.96 MAX 8.76 3.68 0.55 0.51 1.47 2.03 29.97 NOTES 3 8 4 6 5 10 11 121 121 1 2 –B– S b1 b2 C E1 E D D1 E E1 e k L 1.000 BSC 1.140 1.180 25.4 BSC 28.96 29.97 1.000 BSC 0.100 BSC 0.008 REF 0.120 0.025 0.140 0.060 25.4 BSC 2.54 BSC 0.20 REF 3.05 0.64 3.56 1.52 C INDEX CORNER SEE NOTE 9 SEE NOTE 7 A –C– B B Q1 S b1 S S1 M N SECTION B-B b 0.000 BSC 0.003 11 - 0.00 BSC 0.08 Rev. 0 6/20/95 NOTES: 1. “M” represents the maximum pin matrix size. 2. “N” represents the maximum allowable number of pins. Number of pins and location of pins within the matrix is shown on the pinout listing in this data sheet. 3. Dimension “A1” includes the package body and Lid for both cavity-up and cavity-down configurations. This package is cavity down. Dimension “A1” does not include heatsinks or other attached features. 4. Standoffs are required and shall be located on the pin matrix diagonals. The seating plane is defined by the standoffs at dimension “Q1”. 5. Dimension “Q1” applies to cavity-down configurations only. 6. All pins shall be on the 0.100 inch grid. 7. Datum C is the plane of pin to package interface for both cavity up and down configurations. 8. Pin diameter includes solder dip or custom finishes. Pin tips shall have a radius or chamfer. 9. Corner shape (chamfer, notch, radius, etc.) may vary from that shown on the drawing. The index corner shall be clearly unique. 10. Dimension “S” is measured with respect to datums A and B. 11. Dimensioning and tolerancing per ANSI Y14.5M-1982. 12. Controlling dimension: INCH. 0.008 C SEATING PLANE AT STANDOFF k A1 L e b2 Q SECTION A-A b A A Ø0.030 M Ø0.010 M C AM BM C L A1 Q 12 HMU16, HMU17 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER C L 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP 0.004 (0.10) C N68.95 (JEDEC MS-018AE ISSUE A) 68 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL A A1 MIN 0.165 0.090 0.985 0.950 0.441 0.985 0.950 0.441 68 MAX 0.180 0.120 0.995 0.958 0.469 0.995 0.958 0.469 MILLIMETERS MIN 4.20 2.29 25.02 24.13 11.21 25.02 24.13 11.21 68 MAX 4.57 3.04 25.27 24.33 11.91 25.27 24.33 11.91 NOTES 3 4, 5 3 4, 5 6 Rev. 2 11/97 0.025 (0.64) R 0.045 (1.14) D2/E2 C L E1 E D2/E2 VIEW “A” D D1 D2 E E1 E2 N D1 D 0.020 (0.51) MAX 3 PLCS A1 A 0.020 (0.51) MIN SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53) 0.045 (1.14) MIN VIEW “A” TYP. 0.025 (0.64) MIN NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 13