HS-1825ARH

® HS-1825ARH Data Sheet September 25, 2008 FN4561.8 Radiation Hardened High-Speed, Dual Output PWM The Radiation Hardened HS-1825ARH Pulse Width Modulator is designed to be used in high frequency switched-mode power supplies and can be used in either current-mode or voltage-mode. It is well suited for single-ended boost converter applications. Device features include a precision voltage reference, low power start-up circuit, high frequency oscillator, wide-band error amplifier, and fast current-limit comparator. The use of proprietary process capabilities and unique design techniques results in fast propagation delay times and high output current over a wide range of output voltages. Constructed with the Intersil Rad Hard Silicon Gate (RSG) Dielectric Isolation BiCMOS process, the HS-1825ARH has been specifically designed to provide highly reliable performance when exposed to harsh radiation environments. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. Detailed Electrical Specifications for the HS-1825ARH are contained in SMD 5962-99558. That document may be easily downloaded from our website. www.intersil.com/ Features • Electrically Screened to DESC SMD # 5962-99558 • QML Qualified per MIL-PRF-38535 Requirements • Radiation Environment - Maximum Total Dose . . . . . . . . . . . . . . . . 300 krad(SI) - Vertical Architecture Provides Low Dose Rate Immunity - DI RSG Process Provides Latch-Up Immunity • Low Start-Up Current . . . . . . . . . . . . . . . . . . . 100µA (Typ) • Fast Propagation Delay . . . . . . . . . . . . . . . . . . 80ns (Typ) • 12V to 30V Operation • 1A (Peak) Dual Output Drive Capability • 5.1V Reference • Undervoltage Lockout • Programmable Soft-Start • Switching Frequencies to 500kHz • Latched Overcurrent Comparator with Full Cycle Restart • Programmable Leading Edge Blanking Circuit Applications • Current or Voltage Mode Switching Power Supplies • Motor Speed and Direction Control Pinout HS-1825ARH SBDIP (CDIP2-T16) AND FLATPACK (CDFP4-F16) TOP VIEW INV 1 NON-INV 2 E/A OUT 3 CLOCK 4 RT 5 CT 6 RAMP 7 SOFT START 8 16 VREF 5.1V 15 VCC 14 OUTPUT B 13 VC 12 POWER GND 11 OUTPUT A 10 GND 9 ILIM/SD NOTE: Grounding the Soft-Start pin does not inhibit the outputs. The outputs may be inhibited by applying >1.26V to the ILIM/SD pin. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002, 2005, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HS-1825ARH Ordering Information ORDERING NUMBER 5962F9955801V9A HS0-1825ARH/Sample 5962F9955801VEC 5962F9955801QEC 5962F9955801VXC 5962F9955801QXC HS1-1825ARH/Proto HS9-1825ARH/Proto INTERNAL MKT. NUMBER HS0-1825ARH-Q HS0-1825ARH/Sample HS1-1825ARH-Q HS1-1825ARH-8 HS9-1825ARH-Q HS9-1825ARH-8 HS1-1825ARH/Proto HS9-1825ARH/Proto TEMP. RANGE (°C) -50 to +125 -50 to +125 -50 to +125 -50 to +125 -50 to +125 -50 to +125 -50 to +125 -50 to +125 16 Ld SBDIP 16 Ld SBDIP 16 Ld Flatpack 16 Ld Flatpack 16 Ld SBDIP 16 Ld Flatpack D16.3 D16.3 K16.A K16.A D16.3 K16.A PACKAGE PKG. DWG. # Typical Performance Curves 10k FREQUENCY (kHz) 100 C220pF C470pF C1000pF C2200pF C4700pF 100 C22nF 10 C10nF 1 10 Rt TIMING RESISTANCE (kΩ) 100 50 1 10 Rt TIMING RESISTANCE (kΩ) 100 DMAX (%) 1k 80 70 60 90 DMAX FIGURE 1. OSCILLATOR FREQUENCY vs Rt AND Ct FIGURE 2. MAXIMUM DUTY CYCLE vs Rt 2 FN4561.8 September 25, 2008 HS-1825ARH Die Characteristics DIE DIMENSIONS 4710µm x 3570µm (185 mils x 140 mils) Thickness: 483µm ±25.4µm (19 mils ±1 mil) INTERFACE MATERIALS Glassivation Type: PSG (Phosphorous Silicon Glass) Thickness: 8.0kÅ ±1.0kÅ Top Metallization Type: ALSiCu Thickness: 16.0kÅ ±2kÅ Substrate Radiation Hardened Silicon Gate, Dielectric Isolation Backside Finish Silicon ASSEMBLY RELATED INFORMATION Substrate Potential Unbiased (DI) ADDITIONAL INFORMATION Worst Case Current Density