HS1-3182-8

® HS-3182 Data Sheet May 30, 2008 FN2963.3 ARINC 429 Bus Interface Line Driver Circuit The HS-3182 is a monolithic dielectric ally isolated bipolar differential line driver designed to meet the specifications of ARINC 429. This device is intended to be used with a companion chip, HS-3282 CMOS ARINC Bus Interface Circuit, which provides the data formatting and processor interface function. All logic inputs are TTL and CMOS compatible. In addition to the DATA (A) and DATA (B) inputs, there are also inputs for CLOCK and SYNC signals which are AND’d with the DATA inputs. This feature enhances system performance and allows the HS-3182 to be used with devices other than the HS-3182. Three power supplies are necessary to operate the HS-3182: +V = +15V ±10%, -V = -15V ±10%, and V1 = 5V ±5%. VREF is used to program the differential output voltage swing such that VOUT (DIFF) = ±2VREF. Typically, VREF = V1 = 5V ±5%, but a separate power supply may be used for VREF which should not exceed 6V. The driver output impedance is 75Ω ±20% at +25°C. Driver output rise and fall times are independently programmed through the use of two external capacitors connected to the CA and CB inputs. Typical capacitor values are CA = CB = 75pF for high-speed operation (100kBPS), and CA = CB = 300pF for low-speed operation (12kBPS to 14.5kBPS). The outputs are protected against overvoltage and short circuit as shown in the Block Diagram. The HS-3182 is designed to operate over an ambient temperature range of -55°C to +125°C, or -40°C to +85°C. TABLE 1. TRUTH TABLE SYNC CLK DATA (A) DATA (B) AOUT X L H H H H L X H H H H X X L L H H X X L H L H 0V 0V 0V BOUT 0V 0V 0V COMMENTS Null Null Features • RoHS/Pb-free Available for SBDIP Package (100% Gold Termination Finish) • TTL and CMOS Compatible Inputs • Adjustable Rise and Fall Times via Two External Capacitors • Programmable Output Differential Voltage via VREF Input • Operates at Data Rates Up to 100k Bits/s • Output Short Circuit Proof and Contains Overvoltage Protection • Outputs are Inhibited (0V) If DATA (A) and DATA (B) Inputs are Both in the “Logic One” State • DATA (A) and DATA (B) Signals are “AND’d” with Clock and Sync Signals • Full Military Temperature Range Pinouts HS-3182 (16 LD SBDIP) TOP VIEW VREF 1 GND 2 SYNC 3 DATA (A) 4 CA 5 AOUT 6 -V 7 GND 8 16 V1 15 NC 14 CLK 13 DATA (B) 12 CB 11 BOUT 10 NC 9 +V HS-3182 (28 LD CLCC) TOP VIEW SYNC GND NC VREF NC NC 25 CLK 24 NC 23 DATA (B) 22 CB 21 NC 20 NC 19 NC 12 13 14 15 16 17 18 AOUT BOUT GND NC NC -V +V Null Low High Null NC DATA (A) NC NC CA 5 6 7 8 9 -VREF +VREF +VREF -VREF 0V 0V 4 3 2 1 NC 10 NC 11 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1997, 2007, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. V1 28 27 26 HS-3182 Ordering Information PART NUMBER HS1-3182-8 HS1-3182-9+ HS4-3182-8 ORDERING NUMBER 5962-8687901EA HS1-3182-9+ 5962-86879013A PART MARKING HS1-3182-8 RD HS1-3182-9+ RD HS4- 3182-8 RD TEMP. RANGE (°C) -55 to +125 -40 to +85 -55 to +125 PACKAGE 16 Ld SBDIP, Solder Seal (Pb-free) 16 Ld SBDIP, Solder Seal (Pb-free) 28 Ld TER CLCC, Solder Seal PKG. DWG. # D16.3 D16.3 J28.A NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Block Diagram (9) (5) +V CA OUTPUT DRIVER (A) ROUT/2 (4) DATA (A) LEVEL SHIFTER AND SLOPE CONTROL (A) FA (6) AOUT (14) CLOCK (1) VREF (3) SYNC (13) DATA (B) LEVEL SHIFTER AND SLOPE CONTROL (B) OUTPUT DRIVER ROUT/2 (B) FB BOUT (11) (8) GND CL RL (16) V1 (2) CURRENT REGULATOR -V (7) CB (12) OVER-VOLTAGE PROTECTION Typical Application (9) PIN NUMBERS INDICATED BY ( ) (16) (14) (3) +5V CA (1) (5) CA (12) CB +V AOUT HS-3182 ARINC DRIVER CIRCUIT 31 429D0 HS-3282 CMOS ARINC CIRCUIT 429D0 (4) DATA (A) 32 (13) DATA (B) 16 LEAD DIP BOUT TO BUS (SEE NOTE) V1 VREF CLOCK SYNC CB +15V GND (2) GND (8) -V (7) PIN NUMBER 10, 15 = NC -15V NOTE: The rise and fall time of the outputs are set to ARINC specified values by CA and CB. Typical CA = CB = 75pF for high speed and 300pF for low speed operation. The output HI and low levels are set to ARINC specifications by VREF. 2 FN2963.3 May 30, 2008 HS-3182 Absolute Maximum Ratings Voltage Between +V and -V Terminals . . . . . . . . . . . . . . . . . . . .40V V1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V Logic Input Voltage . . . . . . . . . . . . . . . . . . . GND -0.3V to V1 +0.3V Output Short Circuit Duration. . . . . . . . . . . . . . . . . . . . . . . . (Note 3) Output Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . (Note 4) Thermal Information Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) SBDIP Package . . . . . . . . . . . . . . . . . . 68 12 CLCC Package . . . . . . . . . . . . . . . . . . 54 10 Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Operating Voltage +V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V ±10% -V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15V ±10% V1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5% VREF (For ARINC 429) . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5% Operating Temperature Range HS-3182-9+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C HS-3182-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C Die Characteristics Number of Transistors or Gates . . . . . . . . . . . . . . . . . . . . . . . . . 133 CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. θJC, the “case temp” location is the center of the package underside. 3. Heat sink may be required for 100k bits/s at +125°C and output short circuit at +125°C. 4. The fuses used for output overvoltage protection may be blown by a fault at each output of greater than ±6.5V relative to GND. DC Electrical Specifications Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. DC PARAMETER Supply Current +V (Operating) Supply Current -V (Operating) Supply Current V1 (Operating) Supply Current VREF (Operating) Logic “1” Input Voltage Logic “0” Input Voltage Output Voltage High (Output to GND) Output Voltage Low (Output to GND) Output Voltage Null Input Current (Input Low) Input Current (Input High) Output Short Circuit Current (Output High) Output Short Circuit Current (Output Low) Output Impedance NOTES: SYMBOL ICCOP (+V) ICCOP (-V) ICCOP (V1) ICCOP (VREF) VIH VIL VOH VOL VNULL IIL IIH IOHSC IOLSC ZO CONDITIONS (Note 5) No Load (0k to 100k bits/s) No Load (0k to 100k bits/s) No Load (0k to 100k bits/s) No Load (0k to 100k bits/s) MIN -16 -1.0 2.0 - MAX 16 975 0.5 VREF (+250mV) -VREF (+250mV) +250 10 -80 90 UNITS mA mA µA mA V V No Load (0k to 100k bits/s) No Load (0k to 100k bits/s) No Load (0k to 100k bits/s) VREF (-250mV) -VREF (-250mV) -250 -20 - mV mA mA mA mA Ω Short to GND Short to GND TA = +25°C 80 60 5. +V = +15V ±10%, -V = -15V ±10%, V1 = VREF = 5V ±5%, unless otherwise specified TA = -40°C to +85°C for HS-3182-9+ and TA = -55°C to +125°C for HS-3182-8. 3 FN2963.3 May 30, 2008 HS-3182 AC Electrical Specifications AC PARAMETER Rise Time (AOUT, BOUT) SYMBOL tR CONDITIONS (Note 6) CA = CB = 75pF, (Note 7) (at TA = -55°C Only) CA = CB = 300pF, (Note 7) Fall Time (AOUT, BOUT) tF CA = CB = 75pF, (Note 8) (at TA = -55°C Only) CA = CB = 300pF, (Note 8) Propagation Delay Input to Output Propagation Delay Input to Output NOTES: 6. +V = +15V, -V = -15V, V1 = VREF = 5V, unless otherwise specified TA = -40°C to +85°C for HS-3182-9+ and TA = -55°C to +125°C for HS-3182-8. 7. tR measured 50% to 90% x 2, no load. 8. tF measured 50% to 10% x 2, no load. tPLH tPHL CA = CB = 75pF, No Load CA = CB = 75pF, No Load MIN 1 0.9 3 1 0.9 3 MAX 2 2.4 9 2 2.4 9 3.3 3.3 UNITS µs µs µs µs µs µs µs µs Electrical Specifications PARAMETER Input Capacitance Supply Current +V (Short Circuit) Supply Current -V (Short Circuit) NOTES: 9. Limits established by characterization and are not production tested. SYMBOL CIN ISC (+V) ISC (-V) TA = +25°C Short to GND, TA = +25°C Short to GND, TA = +25°C CONDITIONS (NOTE 9) MIN -150 MAX 15 150 UNITS pF mA mA Power Specifications DATA RATE (k BITS/s) 0 to 100 12.5 to 14 100 NOTES: No Load Nominal Power at +25°C, +V = +15V, -V = -15V, V1 = VREF = 5V, Notes 10, 12 LOAD +V 11mA 24mA 46mA V-10mA -24mA -46mA V1 600µA 600µA 600µA CHIP POWER 325mW 660mW 1 Watt POWER DISSIPATION IN LOAD 0 60mW 325mW Full Load, Note 11 Full Load, Note 11 10. Heat sink may be required for 100k bits/s at +125°C and output short circuit at +125°C. Thermal characteristics: T(CASE) = T(Junction) - θ(Junction - Case) P(Dissipation). Where: T(Junction Max) = +175°C θ(Junction - Case) = 10.9°C/W (6.1°C/W for LCC) θ(Junction - Ambient) = 73.5°C/W (54.0°C/W for LCC) 11. Full Load for ARINC 429: RL = 400Ω and CL = 30,000pF in parallel between AOUT and BOUT (See “Block Diagram” on page 2). 12. Output Overvoltage Protection: The fuses used for output overvoltage protection may be blown by a fault at each output of greater than ±6.5V relative to GND. 4 FN2963.3 May 30, 2008 HS-3182 Driver Waveforms 50% 5V 0V 5V 0V ADJ. BY CB DATA (A) 0V DATA (B) 0V VREF AOUT 0V 50% +4.75V TO +5.25V ADJ. BY CA tPHL BOUT 0V -VREF 50% 50% tR tPLH 2VREF -VREF VREF -4.75V TO -5.25V +4.75V TO +5.25V -4.75V TO -5.25V HIGH +9.5V TO +10.5V DIFFERENTIAL OUTPUT AOUT - BOUT 0V NULL -2VREF tF LOW NOTE: OUTPUTS UNLOADED -9.5V TO -10.5V NOTES: tR measured 50% to 90% x 2 tF measured 50% to 10% x 2 VIH = 5V VIL = 0V VOL = -4.75V to -5.25V VOH = 4.75V to 5.25V When the Data (A) input is in the Logic One state and the Data (B) input is in the Logic Zero state, AOUT is equal to VREF and BOUT is equal to -VREF. This constitutes the Output High state. Data (A) and Data (B) both in the Logic Zero state causes both AOUT and BOUT to be equal to 0V which designates the output Null state. Data (A) in the Logic Zero state and Data (B) in the Logic One state causes AOUT to be equal to -VREF and BOUT to be equal to VREF which is the Output Low state. Burn-In Schematic V1 DATA (B) +V VIH C3 16 1 15 2 14 13 12 11 HS-3182 3 4 5 6 C2 10 7 9 R 8 C1 VIH B VIL A VIL DATA (A) -V GND NOTES: R = 400Ω ± 5% C1 = 0.03mF ± 20% C2 = C3 = 500pF, NPO +V = +15.5V ± 0.5V -V = -15.5V ± 0.5V V1 = +5.5V ± 0.5V A 0.0mF decoupling capacitor is required on each of the three supply lines (+V, -V and V1) at every 3rd Burn-In socket. Ambient Temp. Max. = +125°C. Package = 16 Lead Side Brazed DIP. Pulse Conditions = A & B = 6.25kHz ±10%. B is delayed one-half cycle and in sync with A. VIH = 2.0V Min. VIL = 0.5V Max. 5 FN2963.3 May 30, 2008 HS-3182 Ceramic Leadless Chip Carrier Packages (CLCC) 0.010 S E H S D D3 J28.A MIL-STD-1835 CQCC1-N28 (C-4) 28 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE INCHES SYMBOL A A1 B B1 B2 B3 D D1 D2 MIN 0.060 0.050 0.022 0.006 0.442 MAX 0.100 0.088 0.028 0.022 0.460 MILLIMETERS MIN 1.52 1.27 0.56 0.15 11.23 1.83 REF 0.56 11.68 MAX 2.54 2.23 0.71 NOTES 6, 7 2, 4 2 2 2 5 5 3 3 3 Rev. 0 5/18/94 j x 45o B E3 E 0.072 REF 0.300 BSC 0.150 BSC 0.442 0.460 0.460 - 7.62 BSC 3.81 BSC 11.68 11.68 7.62 BSC 3.81 BSC 0.38 1.02 REF 0.51 REF 1.14 1.14 1.90 0.08 7 7 28 1.40 1.40 2.41 0.038 11.68 1.27 BSC 11.23 h x 45o 0.010 S E F S A A1 PLANE 2 PLANE 1 D3 E E1 E2 E3 e e1 h j 0.007 M E F S H S B1 L -H- 0.300 BSC 0.150 BSC 0.015 0.460 0.050 BSC 0.040 REF 0.020 REF 0.045 0.045 0.075 0.003 7 7 28 0.055 0.055 0.095 0.015 -E- L L1 L3 e L2 L3 ND NE N -FE1 B3 NOTES: 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. E2 L2 B2 L1 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol “N” is the maximum number of terminals. Symbols “ND” and “NE” are the number of terminals along the sides of length “D” and “E”, respectively. 4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer’s option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension “A” controls the overall package thickness. The maximum “A” dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Controlling dimension: INCH. e1 D1 D2 6 FN2963.3 May 30, 2008 HS-3182 Ceramic Dual-In-Line Metal Seal Packages (SBDIP) c1 -A-DBASE METAL M -Bbbb S C A - B S BASE PLANE SEATING PLANE S1 b2 b AA D S2 -CQ A L DS b1 M (b) SECTION A-A (c) LEAD FINISH D16.3 MIL-STD-1835 CDIP2-T16 (D-2, CONFIGURATION C) 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c c1 D E e eA eA/2 L Q S1 S2 MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.840 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 21.34 7.87 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 0.13 90o 16 5.08 1.52 105o 0.38 0.76 0.25 0.038 NOTES 2 3 4 2 3 5 6 7 2 8 Rev. 0 4/94 E eA e eA/2 c 0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 0.005 90o 16 0.200 0.060 105o 0.015 0.030 0.010 0.0015 ccc M C A - B S D S aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH. α aaa bbb ccc M N All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 7 FN2963.3 May 30, 2008