HS1-82C12RH-Q

HS-82C12RH TM Data Sheet August 2000 File Number 3041.3 Radiation Hardened 8-Bit Input/Output Port The Intersil HS-82C12RH is a radiation hardened 8-bit input/output port designed for use with the HS-80C85RH radiation hardened microprocessor. It is manufactured using a self-aligned, junction-isolated EPI-CMOS process and features three-state output buffers and device selection and control logic. A service request flip-flop is included for the generation and control of interrupts to the microprocessor. The device can be used in implement many of the peripheral and input/output functions of a microcomputer system. The HS-82C12RH is pinout- and function- compatible with industry-standard 8212 devices. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-95818. A “hot-link” is provided on our homepage for downloading. www.intersil.com/spacedefense/space.asp Features • Electrically Screened to SMD # 5962-95818 • QML Qualified per MIL-PRF-38535 Requirements • Radiation Performance - Hardened EPI-CMOS Process - Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max) - Transient Upset . . . . . . . . . . . . . . . . . > 1 x 108 rad(Si)/s - Latch-Up Immune • Low Power Dissipation • High Noise Immunity • Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . +5V • Low Input Load Current • 8-Bit Data Register and Buffer • Asynchronous Register Clear • Service Request Flip-Flop for Interrupt Generation • Three-State Outputs • Bus-Compatible with HS-80C85RH CPU Ordering Information ORDERING NUMBER 5962R9581801QJC 5962R9581801QXC 5962R9581801V9A 5962R9581801VJC 5962R9581801VXC INTERNAL MKT. NUMBER HS1-82C12RH-8 HS9-82C12RH-8 HS0-82C12RH-Q HS1-82C12RH-Q HS9-82C12RH-Q TEMP. RANGE (oC) -55 to 125 -55 to 125 25 -55 to 125 -55 to 125 • Electrically Equivalent to Sandia SA3026 • Military Temperature Range . . . . . . . . . . . -55oC to 125oC Functional Diagram DS1 DS2 STB CLR MD DATA LATCH AND BUFFER (8) CONTROL AND DEVICE SELECT LOGIC 2 SERVICE REQUEST F.F. INT 3 DI0-7 DO0-7 Pin Description PIN DI0-DI7 DO0-DO7 DS1, DS2 MD STB INT CLR Data In Data Out Device Select Mode Strobe Interrupt Clear DESCRIPTION 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 HS-82C12RH Pinouts 24 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T24 TOP VIEW DS1 1 MD 2 DI0 3 DO0 4 DI1 5 DO1 6 DI2 7 DO2 8 DI3 9 DO3 10 STB 11 GND 12 24 VDD 23 INT 22 DI7 21 DO7 20 DI6 19 DO6 18 DI5 17 DO5 16 DI4 15 DO4 14 CLR 13 DS2 24 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F24 TOP VIEW DS1 MD DI0 DO0 DI1 DO1 DI2 DO2 DI3 DO3 STB GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD INT DI7 DO7 DI6 DO6 DI5 DO5 DI4 DO4 CLR DS2 2 HS-82C12RH Timing Waveforms (DS, • DS2) tE tD 0.5VDD OUTPUT VOH VOL 0.5VDD FIGURE 1. READ TIMING DATA tPW MD OR (DS, • DS2) tH tWE OUTPUT FIGURE 2. WRITE TIMING DATA tSET tH STB OR (DS, • DS2) tPD OUTPUT FIGURE 3. DATA SETUP, HOLD, PROPAGATION DELAY TIMING tPW STB (DS, • DS2) tR tS INT tPW FIGURE 4. INTERRUPT TIMING CLR tC DO tPW FIGURE 5. CLEAR TIMING 3 HS-82C12RH Functional Description Data Latch The data latch is comprised of eight “D” type flip-flops. The output of each flip-flop will follow the corresponding data input (DI0 - DI7) when the clock (C) is high. The clock input is level sensitive and the data becomes latched when the clock returns low. An asynchronous reset (CLR) is used to clear the latched data. Since the clock (C) overrides the reset (CLR), the data must be in the latched state in order to clear the flip-flops. If the data is not latched (i.e. clock is high) when CLR goes low, then the Q outputs of the data latch will continue to follow the data input, overriding the reset signal. Mode the mode input (MD) is used to control the state of the output buffer and to determine the source of the data latch clock (C). When MD is high, the output buffers are enabled and the source of the data latch clock (C) is the device select logic (DS1 • DS2). When MD is low, the state of the output buffer is controlled by the device select logic (DS1 • DS2) and the source of the data latch clock is the strobe (STB) input. Strobe The strobe input (STB) is used as the data latch clock (C) when the mode input (MD) is low. The service request flipflop is synchronously set on the negative going edge of STB. Output Buffer Three-state buffers are used to provide output drive for the data latch. A high level on the “output buffer enable” control line enables the buffer outputs. When “output buffer enable” is low the buffer outputs are forced to the high-impedance state. Service Request Flip-Flop The service request flip-flop is to generate interrupts to microcomputer systems. It is negative edge triggered and asynchronously cleared (reset). The output of the service request flip-flop is AND-gated with the device select logic (DS1 • DS2). The output of the AND gate is the active low interrupt (INT) signal. Device Select Logic The inputs DS1 and DS2 are used for device selection. When DS1 is low and DS2 is high, the device is selected. The output buffers are enabled and the service request flipflop is asynchronously cleared when the device is selected. 4 HS-82C12RH Logic Diagram DEVICE DS1 13 DS2 S STB 11 CLR 14 DI2 7 LATCH CLOCK DI3 MD 9 2 DI4 16 D E R DO3 TSB 10 Q Q DO2 TSB 8 D C Q Q SERVICE REQUEST FLIP-FLOP DI1 5 SELECT DATA OUT ENABLE LATCH RESET DI0 3 D E R DO1 TSB 6 Q Q DO0 TSB 4 INT 23 D E R Q Q D E R Q Q D E R Q Q DO4 TSB 15 DI5 18 D E R Q Q DO5 TSB 17 DI6 20 D E R Q Q DO6 TSB 19 DI7 22 D E R Q Q DO7 TSB 21 TABLE 1. DATA OUT STB 0 1 0 1 0 1 0 1 MD 0 0 1 1 0 0 1 1 DS1 • DS2 0 0 0 0 1 1 1 1 DATA OUT EQUALS High Z State High Z State Data Latch Data Latch Data Latch Data In Data In Data In CLR 0 RESET 1 1 1 1 DS1 • DS2 0 0 0 1 RESET 0 TABLE 2. INT STB 0 0 (NOTE) Q 0 0 1 0 0 0 0 INT 1 1 0 0 1 NOTE: Internal Service Request Flip-Flop 5 HS-82C12RH Die Characteristics DIE DIMENSIONS: 90 mils x 76 mils x 14 mils ±1 mil INTERFACE MATERIALS: Glassivation: Type: SiO2 Thickness: 8kÅ ±1kÅ Top Metallization: Type: AlSi Thickness: 11kÅ ±2kÅ Substrate: Radiation Hardened Silicon Gate, Dielectric Isolation Backside Finish: Silicon ASSEMBLY RELATED INFORMATION: Substrate Potential: Unbiased (DI) Metallization Mask Layout HS-82C12RH (24) VDD (23) INT (1) DS1 (3) DI0 (2) MD (22) DI7 DO0 (4) DI1 (5) (21) DO7 (20) DI6 DO1 (6) (19) DO6 DI2 (7) DO2 (8) DI3 (9) (18) DI5 (17) DO5 (16) DI4 (15) DO4 DO3 (10) GND (12) All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369 6 CLR (14) STB (11) DS2 (13)