HS4-3282-8

TM HS-3282 CMOS ARINC Bus Interface Circuit Description The HS-3282 is a high performance CMOS bus interface circuit that is intended to meet the requirements of ARINC Specification 429, and similar encoded, time multiplexed serial data protocols. This device is intended to be used with the HS-3182, a monolithic Dl bipolar differential line driver designed to meet the specifications of ARINC 429. The ARINC 429 bus interface circuit consists of two (2) receivers and a transmitter operating independently as shown in Figure 1. The two receivers operate at a frequency that is ten (10) times the receiver data rate, which can be the same or different from the transmitter data rate. Although the two receivers operate at the same frequency, they are functionally independent and each receives serial data asynchronously. The transmitter section of the ARINC bus interface circuit consists mainly of a First-In First-Out (FIFO) memory and timing circuit. The FIFO memory is used to hold up to eight (8) ARINC data words for transmission serially. The timing circuit is used to correctly separate each ARINC word as required by ARINC Specification 429. Even though ARINC Specification 429 specifies a 32-bit word, including parity, the HS-3282 can be programmed to also operate with a word length of 25 bits. The incoming receiver data word parity is checked, and a parity status is stored in the receiver latch and output on Pin BD08 during the 1st word. [A logic “0” indicates that an odd number of logic “1” s were received and stored; a logic “1” indicates that an even number of logic “1”s were received and stored]. In the transmitter the parity generator will generate either odd or even parity depending upon the status of PARCK control signal. A logic “0” on BD12 will cause odd parity to be used in the output data stream. Versatility is provided in both the transmitter and receiver by the external clock input which allows the bus interface circuit to operate at data rates from 0 to 100 kilobits. The external clock must be ten (10) times the data rate to insure no data ambiguity. The ARINC bus interface circuit is fully guaranteed to support the data rates of ARINC specification 429 over both the voltage (±5%) and full military temperature range. It interfaces with UL, CMOS or NMOS support circuitry, and uses the standard 5-volt VCC supply. REFERENCE AN400 March 1997 Features • ARlNC Specification 429 Compatible • Data Rates of 100 Kilobits or 12.5 Kilobits • Separate Receiver and Transmitter Section • Dual and Independent Receivers, Connecting Directly to ARINC Bus • Serial to Parallel Receiver Data Conversion • Parallel to Serial Transmitter Data Conversion • Word Lengths of 25 or 32 Bits • Parity Status of Received Data • Generate Parity of Transmitter Data • Automatic Word Gap Timer • Single 5V Supply • Low Power Dissipation • Full Military Temperature Range Ordering Information PACKAGE CERDIP SMD# CLCC -40oC to +85oC -55oC to +125oC SMD# TEMP. RANGE -55oC to +125oC PART NUMBER HS1-3282-8 5962-8688001QA HS4-3282-9+ HS4-3282-8 5962-8688001XA PKG. NO. F40.6 F40.6 J44.A J44.A J44.A CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved FN2964.2 183 HS-3282 Pinouts HS-3282 (CERDIP) TOP VIEW VDD 429DI1(A) 429DI1(B) 429DI2(A) 429DI2(B) D/R1 D/R2 SEL EN1 EN2 BD15 BD14 BD13 BD12 BD11 BD10 BD09 BD08 BD07 BD06 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 NC 39 MR 38 TX CLK 37 CLK 36 NC 35 NC 34 CWSTR 33 ENTX 32 429D0 31 429D0 30 TX/R 29 PL2 28 PL1 27 BD00 26 BD01 25 BD02 24 BD03 23 BD04 22 BD05 21 GND HS-3282 (CLCC) TOP VIEW 429DI2(A) 429DI1(B) 429DI2(B) 429DI1(A) TXCLK NC CLK VDD NC MR 6 NC 7 D/R1 8 D/R2 9 SEL 10 EN1 11 EN2 12 BD15 13 BD14 14 BD13 15 BD12 16 BD11 17 5 4 3 2 1 44 43 42 41 40 39 NC 38 NC 37 CWSTR 36 ENTX 35 429D0 34 429D0 33 TX/R 32 PL2 31 PL1 30 BD00 29 BD01 18 19 20 21 22 23 24 25 26 27 28 BD10 BD09 BD08 BD07 BD06 BD05 BD04 BD03 BD02 GND NC 184 NC HS-3282 Pin Description PIN 1 2 3 4 5 6 7 8 9 10 11 SYMBOL VCC 429 DI1 (A) 429 DI1 (B) 429 Dl2 (A) 429 DI2 (B) D/R1 D/R2 SEL EN1 EN2 BD15 SECTION Recs/Trans Receiver Receiver Receiver Receiver Receiver Receiver Receiver Receiver Receiver Recs/Trans Supply pin 5 volts ±5%. ARlNC 429 data input to Receiver 1. ARlNC 429 data input to Receiver 1. ARINC 429 data input to Receiver 2. ARINC 429 data input to Receiver 2. Device ready flag output from Receiver 1 indicating a valid data word is ready to be fetched. Device ready flag output from Receiver 2 indicating a valid data word is ready to be fetched. Bus Data Selector - Input signal to select one of two 16-bit words from either Receiver 1 or 2. Input signal to enable data from Receiver 1 onto the data bus. Input signal to enable data from Receiver 2 onto the data bus. Bi-directional data bus for fetching data from either of the Receivers, or for loading data into the Transmitter memory or control word register. See Control Word Table for description of Control Word bits. See Pin 11. See Pin 11. See Pin 11. See Pin 11. See Pin 11. See Pin 11. See Pin 11. See Pin 11. See Pin 11. Circuit Ground. See Pin 11. See Pin 11. Control Word function not applicable. See Pin 11. Control Word function not applicable. See Pin 11. Control Word function not applicable. See Pin 11. Control Word function not applicable. See Pin 11. Control Word function not applicable. Parallel load input signal loading the first 16-bit word into the Transmitter memory. Parallel load input signal loading the first 16-bit word into the Transmitter memory and initiates data transfer into the memory stack. Transmitter flag output to indicate the memory is empty. DESCRIPTION 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 BD14 BD13 BD12 BD11 BD10 BD09 BD08 BD07 BD06 GND BD05 BD04 BD03 BD02 BD01 BD00 PL1 PL2 Recs/Trans Recs/Trans Recs/Trans Recs/Trans Recs/Trans Recs/Trans Recs/Trans Recs/Trans Recs/Trans Recs/Trans Recs/Trans Recs/Trans Recs/Trans Recs/Trans Recs/Trans Recs/Trans Transmitter Transmitter 30 TX/R Transmitter 185 HS-3282 Pin Description PIN 31 32 33 34 SYMBOL 429D0 429D0 ENTX CWSTR ( Continued) SECTION Transmitter Transmitter Transmitter Recs/Trans Data output from Transmitter Data output from Transmitter. Transmitter Enable input signal to initiate data transmission from FIFO memory. Control word input strobe signal to latch the control word from the databus into the control word register. No connection. Must be left open. No connection. Must be left open or tied low but never tied high. External clock input. May be either ten (10) or eighty (80) times the data rate. If using both ARINC data rates it must be ten (10) times the highest data rate, (typically 1MHz). Transmitter Clock output. Delivers a clock frequency equal to the transmitter data rate. Master Reset. Active low pulse used to reset FIFO, bit counters, gap timer, word count signal, TX/R and various other flags and controls. Master reset does not reset the control word register. Usually only used on Power-Up or System Reset. No Connection. DESCRIPTION 35 36 37 CLK Recs/Trans 38 39 TXCLK MR Transmitter Recs/Trans 40 - - Pinout 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NC NC NC 186 HS-3282 Operational Description The HS-3282 is designed to support ARINC Specification 429 and other serial data protocols that use a similar format by collecting the receiving, transmitting, synchronizing, timing and parity functions on a single, low power LSl circuit. It goes beyond the ARlNC requirements by providing for either odd or even parity, and giving the user a choice of either 25 or 32-bit word lengths. The receiver and transmitter sections operate independently of each other. The serial-toparallel conversion required of the receiver and the parallelto-serial conversion requirements of the transmitter have been incorporated into the bus interface circuit. Provisions have been made through the external clock input to provide data rate flexibility. This requires an external clock that is 10 times the data rate. To obtain the flexibility discussed above, a number of external control signals are required, To reduce the pin count requirements, an internal control word register is used. The control word is latched from the data bus into the register by the Control Word Strobe (CWSTR) signal going to a logic “1”. Eleven (11) control functions are used, and along with the Bus Data (BD) line are listed below: Control Word PIN NAME BD05 SYMBOL SLFTST FUNCTION Connects the self test signal from the transmitter directly to the receiver shift registers, bypassing the input receivers. Receiver 1 receives Data True and Receiver 2 receives Data Not. Note that the transmitter output remains active. (Logic “0” on SLFTST Enables Self Test). Signal to Activate the Source/Destination (S/D) Decoder for Receiver 1. (Logic “1” activates S/D Decoder). If SDENB1 = “1” then this bit is compared with ARlNC Data Bit #9. If Y1 also matches (see Y1), the word will be accepted by the Receiver 1. If SDENB1 = “0” this bit becomes a don’t care. If SDENBI = “1” then this bit is compared with ARINC Data Bit #10. If X1 also matches (see X1), the word will be accepted by the Receiver 1. If SDENB1 = “0” this bit becomes a don’t care. Signal to activate the Source/Destination (S/D) Decoder for Receiver 2. (Logic “1” activates S/D Decoder). If SDENB2 = “1” then this bit is compared with ARlNC Data Bit #9. If Y2 also matches (see Y2), the word will be accepted by the Receiver 2. If SDENB2 = “0” this bit becomes a don’t care. If SDENB2 = “1” then this bit is compared with ARINC Data Bit #10. If X2 also matches (see X2), the word will be accepted by the Receiver 2. If SDENB2 = “0” this bit becomes a don’t care. Signal used to invert the transmitter parity bit for test of parity circuits. Logic “0” selects normal odd parity. Logic “I” selects even parity. Selects high or low Transmitter data rate. If TXSEL = “0” then transmitter data rate is equal to the clock rate divided by ten (10). If TXSEL = “1” then transmitter data rate is equal to the clock rate divided by eighty (80). Selects high or low Receiver data rate. If RCVSEL = “0” then the received data rate should be equal to the clock rate divided by ten (10), if RCVSEL = “1 “then the received data rate should be equal to the clock rate divided by eighty (80). Selects word length. If WLSEL = “0” a 32-bit word format will be selected. If WLSEL = “1” a 25-Bit word format will be selected. BD06 BD07 BD08 BD09 BD10 BD11 BD12 BD13 BD14 SDENB1 X1 Y1 SDENB2 X2 Y2 PARCK TXSEL RCVSEL BD15 WLSEL ARlNC 429 DATA FORMAT as input to the Receiver and output from the Transmitter is as follows: TABLE 1. ARINC 429 32-BIT DATA FORMAT ARINC BIT # 1-8 9 - 10 11 12 - 27 28 29 30, 31 32 FUNCTION Label SDl or Data LSB Data MSB Sign SSM Parity Status This format is shuffled when seen on the sixteen bidirectional input/outputs. The format shown below is used from the receivers and input to the transmitter: TABLE 2A. WORD 1 FORMAT BI-DIRECTIONAL BIT # 15, 14 13 12, 11 10, 9 8 7 - 00 FUNCTION Data LSB SDl or Data SSM Status Parity Status Label ARINC BlT # 13, 12 11 10, 9 31, 30 32 1-8 187 HS-3282 TABLE 2B. WORD 2 FORMAT BI-DIRECTIONAL BlT# 15 14 13 - 00 FUNCTION Sign MSB Data ARINC BIT# 29 28 27 - 14 • The Line Receiver functions as a voltage level translator. It transforms the 10 volt differential line voltage, ARINC 429 format, into 5 volt internal logic level. • The output of the Line Receiver is one of two inputs to the Self-Test Data Selector (SEL). The other input to the Data Selector is the Self-Test Signal from the Transmitter section. • The incoming data, either Self-Test or ARlNC 429, is double sampled by the Word Gap Timer to generate a Data Clock. The Receiver sample frequency (RCVCLK), 1MHz, or 125kHz, is generated by the Receiver/Transmitter Timing Circuit. This sampling frequency is ten times the Data Rate to ensure no data ambiguity. • The derived data clock then shifts the data down a 32-Bit long Data Shift Register (Data S/RI). The Data Word Length is selectable for either 25 Bits or 32 Bits long by the Control Signal (WLSEL). As soon as the data word is completely received, an internal signal (WDCNT1) is generated by the Word Gap Timer Circuit. • The Source/Destination (S/D) Decoder compares the user set code (X and Y) with Bits 9 and 10 of the Data Word. If the two codes are matched, a positive signal is generated to enable the WDCNT1 signal to latch in the received data. Otherwise, the data word is ignored and no latching action takes place. The S/D Decoder can be Enabled and Disabled by the control signal S/D ENB. If the data word is latched, an indicator flag (D/R1) is set. This indicates a valid data word is ready to be fetched by the user. • After the receiver data has been shifted down the shift register, it is placed in a holding register. The device ready flag will then be set indicating that data is ready to be fetched. If the data is ignored and left in the holding register, it will be written over when the next data word is received. • The received data in the 32-bit holding register is placed on the bus in the form of two (2)16-bit words regardless of whether the format is for 32 or 25-bit data words. Either word can be accessed first or repeatedly until the next received data word falls into the holding register. • The parity of the incoming word is checked and the status (i.e., logic “0” for odd parity and logic “1” for even parity) stored in the receiver latch and output on BD08 during the Word No. 1. • Assuming the user desires to access the data, he first sets the Data Select Line (SEL) to a Logic “0” level and pulses the Enable (EN1) line. This action causes the Data Selector (SELl) to select the first-data word, which contains the label field and Enable it onto the Data Bus. To obtain the second data word, the user sets the SEL line to a Logic “1” level and pulse the Enable (EN1) line again. The Enable pulse duration is matched to the user circuit requirement needed to read the Data Word from the Data Bus. The second Enable pulse is also used to reset the Device Ready (D/R1) flip-flop. This completes a receiving cycle. Receiver Parity Status: 0 = Odd Parity 1 = Even Parity If the receiver input data word string is broken before the entire data word is received, the receiver will reset and ignore the partially received data word. If the transmitter is used to transmit consecutive data words, each word will be separated by a four (4) bit “null” state (both positive and negative outputs will maintain a zero (0) volt level.) TABLE 3. ARINC 25-BIT DATA FORMAT ARINC BIT # 1-8 9 11 - 23 24 25 FUNCTION Label LSB Data MSB Parity Status TABLE 4A. WORD 1 FORMAT BI-DIRECTIONAL BIT# 15 - 9 8 7-0 FUNCTION Don’t Care Parity Status Label ARINC BIT# XXX 25 1-8 TABLE 4B. WORD 2 FORMAT BI-DIRECTIONAL BIT# 15 14 - 1 0 FUNCTION MSB Data LSB ARINC BlT# 24 23 -10 9 Receiver Parity Status: 0 = Odd Parity 1 = Even Parity No Source/Destination (S/D) in 25-Bit format. Receiver Operation Since the two receivers are functionally identical, only one will be discussed in detail, and the block diagram will be used for reference in this discussion. The receiver consists of the following circuits: 188 HS-3282 Transmitter Operation The Transmitter section consists of an 8-word deep by 31Bit long FIFO Memory, Parity Generator, Transmitter Word Gap Timing Circuit and Driver Circuit. • The FlFO Memory is organized in such a way that data loaded in the input register is automatically transferred to the output register for Serial Data Transmission. This eliminates a large amount of data managing time since the data need not be clocked from the input register to the output register. The FIFO input register is made up of two sets of 16 D-type flip-flops, which are clocked by the two parallel load signals (PL1 and PL2). PL1 must always precede PL2. Multiple PL1’s may occur and data will be written over. As soon as PL2 is received, data is transferred to the FIFO. The data from the Data Bus is clocked into the D-type flip-flop on the positive going edge of the PL signals. If the FIFO memory is initially empty, or the stack is not full, the data will be automatically transferred down the Memory Stack and into the output register or to the last empty FIFO storage register. If the Transmitter Enable signal (ENTX) is not active, a Logic “0”, the data remains at the output register. The FIFO Memory has storage locations to hold eight 31-bit words. If the memory is full and the new data is again strobed with PL, the old data at the input register is written over by the new data. Data will remain in the Memory until ENTX goes to a Logic “1”. This activates the FIFO Clock and data is shifted out serially to the Transmitter Driver. Data may be loaded into the FIFO only while ENTX is inactive (low). It is not possible to write data into the FIFO while transmitting. WARNING: If PL1 or PL2 is applied while ENTX is high, i.e., while transmitting, the FlFO may be disrupted such that it would require a MR (Master Reset) signal to recover. • The Output Register of the FIFO is designed such that it can shift out a word of 24 Bits long or 31 Bits long. This word length is again controlled by the WLSEL bit. The TX word Gap Timer Circuit also automatically inserts a gap equivalent to 4-Bit Times between each word. This gives a minimum requirement of 29-Bit time or 36-Bit time for each word transmission. Assuming the signal, ENTX, remains at a Logic “1”, a transfer to stack signal is generated to transfer the data down the Memory Stack one position. This action is continued until the last word is shifted out of the FIFO memory. At this time a Transmitter Ready (TX/R) flag is generated to signal the user that the Transmitter is ready to receive eight more data words. During transmission, if ENTX is taken low then high again, transmission will cease leaving a portion of the word untransmitted, and the data integrity of the FIFO will be destroyed. • A Bit Counter is used to detect the last Bit shifted out of the FIFO memory and appends the Parity Bit generated by the Parity Generator. The Parity Generator has a control signal, Parity Check (PARCK), which establishes whether odd or even parity is used in the output data word. PARCK set to a logic “0” will result in odd parity and when set to a logic “1” will result in even parity. Sample Interface Technique From Figure 1, one can see that the Data Bus is time shared between the Receiver and Transmitter. Therefore, bus controlling must be synchronously shared between the Receiver and the Transmitter. Figure 2 shows the typical interface timing control of the ARlNC Chip for Receiving function and for Transmitting function. Timing sequence for loading the Transmitter FIFO Memory is shown in Timing Interval A. A transmitter Ready (TX/R) Flag signals the user that the Transmitter Memory is empty. The user then Enables the Transmitter Data, a 16-Bit word, on the Data Bus and strobes the Transmitter with a Parallel Load (PL1) Signal. The second part of the 32-Bit word is similarly loaded into the Transmitter with PL2, which also initiates data transfer to stack. This is continuous until the Memory is full, which is eight 31-Bit words. The user must keep track of the number of words loaded into the Memory to ensure no data is written over by other data. During the time the user is loading the Transmitter, he does not have to service the Receiver, even if the Receiver flags the user with the signal D/R1 that a valid received word is ready to be fetched. This is shown by the Timing interval B. If the user decides to obtain the received data before the Transmitter is completely loaded, he sets the two parallel load signals (PL1 and PL2) at a Logic “1” state, and strobes EN1 while the signal SEL is at a Logic “0” state. After the negative edge of EN1, the first 16-Bit segment of the received word becomes valid on the Data Bus. At the positive edge of EN1, the user should toggle the signal SEL to ready the Receiver for the second 16-Bit word. Strobing the Receiver with EN1, the second time, enables the second 16-Bit word and resets the Receiver Ready Flag D/R1. The user should now reset the signal SEL to a Logic “0” state to ready the Receiver for another Read Cycle. During the time period that the user is fetching the received words, he can load the transmitter. This is done by interlacing the PL signals with the EN signals as shown in the Timing Interval B. Servicing the Receiver 2 is similar and is illustrated by Timing interval C. Timing interval D shows the rest of the Transmitter loading sequence and the beginning of the transmission by switching the signal TX Enable to a Logic “1” state. Timing interval E is the time it takes to transmit all data from the FlFO Memory, either 288 Bit times or 232 Bit times. Repeater Operation This mode of operation allows a data word that has been received to be placed directly in the FIFO for transmission. A timing diagram is shown in Figure 7. A 32-bit word is used in this example. The data word is shifted into the shift register and the D/R flag goes low. A logic “0” is placed on the SEL line and EN1 is strobed. This is the same as the normal receiver operation and places half the data word (16 bits) on the data bus. By strobing PL1 at the same time as EN1, these 16 bits will be taken off the bus and placed in the FIFO. SEL is brought back high and EN1 is strobed again for the second 16 bits of the data word. Again by strobing PL2 at the same time the second 16 bits will be placed in the FIFO. The parity bit will have been stripped away leaving the 31-bit data word in the FIFO ready for transmission as shown in Figure 6. 189 HS-3282 CLK 37 RCV CLK RCVSEL WDCNT 1 WORD GAP TXSEL DATA CLOCK DATA S/R 1 32 LATCH 1 16 16 S/D DECODER WDCNT 1 WDCNT 2 16 16 SEL 2 16 D F/F LATCH 2 4 LINE RECEIV. ER 2 32 SEL SELF TEST WLSEL RCV CLK 39 6 7 8 9 10 BD15BD00 DATA BUS 28 29 30 DATA S/R 2 DATA CLOCK WORD GAP WDCNT 2 22 - 27 PARCK SELF TEST 16 16 16 32 31 429D0 SEL EN2 D F/F TX CLK WLSEL SEL 1 SEL EN1 11 16 RCV TIMING CONTROL WORD REGISTER TX TX CLK 38 VCC 1 GND 21 SLF TST (BD05) S/D ENB1 (BD06) S/D ENB2 (BD09) X1 (BD07) Y1 (BD06) X2 (BD10) Y2 (BD11) PARCK (BD12) TXSEL (BD13) RCVSEL (BD14) WLSEL (BD15) 34 CWSTR WLSEL SELF TEST 429D11 (A) 2 LINE RECEIV. ER 1 SLF TEST S/DENB SEL 429D11 (B) RCV CLK TX CLK 3 S/D CODER 429D12 (A) TX WORD GAP 33 ENTX 429D12 (B) 5 FIFO 8 x 31 PARITY TXC DRVR 429D0 11 - 20 MR D/R1 D/R2 SEL EN1 EN2 PL1 PL2 TX/R FIGURE 1. SINGLE CHIP ARINC 429 INTERFACE FUNCTIONAL BLOCK DIAGRAM 190 HS-3282 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage Applied (Except Pins 2 - 5) . . . . . . . . . . . . . . . . GND -0.3V to VDD +0.3V Input Voltage Applied (Pins 2 - 5). . . . . . . . . . . . . . . . . -29V to +29V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Information Thermal Resistance θJA (oC/W) θJC (oC/W) CDIP Package . . . . . . . . . . . . . . . . . . . 35 8 CLCC Package . . . . . . . . . . . . . . . . . . 55 12 Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V Operating Temperature Range HS-3282-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC HS-3282-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2632 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. DC Electrical Performance Specifications VDD = 5V ±5%, TA = 0oC to +70oC (HS-3282-5), TA = -55oC to +125oC (HS-3282-8) LIMITS PARAMETER ARlNC INPUTS Pins 2-3,4-5 Logic “1” Input Voltage Logic “0” Input Voltage Null Input Voltage Common Mode Voltage Input Leakage Input Leakage Differential Input Impedance Input lmpedance to VDD Input lmpedance to GND V lH VIL VNUL VCH IlH IlL RI RH RG VDD = 5.25V VDD = 5.25V VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V VDD = 5.25V, VIN = ±6.5V VDD = 5.25V, VIN = 0.0V VDD = 5.25V, VIN = +5V, -5V VDD = 5.25V, VlN = 0V VDD = Open, VlN = 5.0V 6.7 -13.0 -2.5 -5.0 -450 12 12 12 13.0 -6.7 +2.5 +5.0 200 V V V V µA µA kΩ kΩ kΩ SYMBOL CONDITIONS MIN MAX UNITS BIDIRECTIONAL INPUTS Pins 11-20, 22-27 Logic “1” Input Voltage Logic “0” Input Voltage Input Leakage Input Leakage VIH V IL lIH IlL VDD = 5.25V VDD = 4.75V VDD = 5.25V,VIN = 5.25V VDD = 5.25V, VIN = 0.0V 2.1 -1.5 0.7 1.5 V V µA µA ALL OTHER INPUTS Pins 8-10, 28, 29, 33, 34, 37, 39 Logic “1” Input Voltage Logic “0” Input Voltage Input Leakage Input Leakage VIH V IL IlH IlL VDD = 5.25V VDD = 4.75V VDD = 5.25V, VIN = 5.25V VDD = 5.25V, VIN = 0.0V 3.5 -75 0.7 10 V V µA µA OUTPUTS Pins 6, 7, 11-20, 22-27, 30-32, 38, Supply Pin 1 Logic “1” Output Voltage Logic “0” Output Voltage Standby Supply Current Operating Supply Current V OH VOL lCC1 lCC2 VDD = 4.75V, IOH = -1.5mA VDD = 4.75V lOL= 1.8mA VDD = 5.25V, VIN = 0V Except 9,10, 29 = 5.25V VDD = 5.25V, VIN = 5.25V Except 8, 33 = 0.0V, CLK = 1MHz 2.7 0.4 20 20 V V mA mA 191 HS-3282 AC Electrical Performance Specifications VDD = 5V ±5%, TA = 0oC to +70oC (HS-3282-5), TA = -55oC to +125oC (HS-3282-8) LIMITS P ARAMETER Clock Frequency Data Rate 1/ Data Rate 2/ Master Reset Pulse Width RECEIVER TIMING Receiver Ready Time From 32nd Bit 1/ Receiver Ready Time From 32nd Bit 2/ Device Ready to Enable Time Data Enable Pulse Width Data Enable to Data Enable Time Data Enable to Device Ready Reset Time Output Data Valid to Enable Time Data Enable to Data Select Time Data Select to Data Enable Time Output Data Disable Time CONTROL WORD TIMING Control Word Strobe Pulse Width Control Word Setup Time Control Word Hold Time TRANSMITTER FIFO Write Timing Parallel Load Pulse Width Parallel Load to Parallel Load 2 Delay Transmitter Ready Delay Time Data Word Setup Time Data Word Hold Time TRANSMITTER Output Timing Enable Transmit to Output Data Valid Time 1/ Enable Transmit to Output Data Valid Time 2/ Output Data Bit Time 1/ Output Data Bit Time 2/ Output Data Null Time 1/ Output Data Null Time 2/ TENDAT TENDAT TBlT TBlT TNULL TNULL VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V 4.95 39.6 4.95 39.6 25 200 5.05 40.4 5.05 40.4 µs µs µs µs µs µs TPL TPL12 TTX/R TDWSET TDWHLD VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V 200 0 110 0 840 ns ns ns ns ns TCWSTR TCWSET TCWHLD VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V 130 130 0 ns ns ns TD/R2 TD/R2 TD/REN TEN TENEN TEND/R TENDATA TENSEL TSELEN TDATAEN VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V 0 200 50 20 20 16 128 200 200 80 µs µs ns ns ns ns ns ns ns ns SYMBOL FC FD FD TMR CONDITIONS VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V MIN 200 MAX 1 100 12.5 UNITS MHz kHz kHz ns 192 HS-3282 AC Electrical Performance Specifications VDD = 5V ±5%, TA = 0oC to +70oC (HS-3282-5), TA = -55oC to +125oC (HS-3282-8) (Continued) LIMITS PARAMETER Data Word Gap Time 1/ Data Word Gap Time 2/ Data Transmission Word to TX/R Set Time Enable Transmit Turnoff Time REPEATER OPERATION TIMING Data Enable to Parallel Load Delay Time Data Enable Hold for Parallel Load Time Enable Transmit Delay Time NOTES: 1. 100kHz Data Rate. 2. 12.5kHz Data Rate. TENPL TPLEN TTX/REN VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V 0 0 0 ns ns ns SYMBOL TGAP TGAP TDTX/R TENTX/R CONDITIONS VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V VDD = 4.75V, 5.25V MIN 39.6 316.8 0 MAX 40.4 323.2 400 UNITS µs µs ns ns Electrical Performance Specifications VDD = 5V ±5%, TA = 0oC to +70oC (HS-3282-5), TA = -55oC to +125oC (HS-3282-8) LIMITS PARAMETER Differential Input Capacitance Input Capacitance to VDD lnput Capacitance to GND Input Capacitance Output Capacitance Clock Rise Time Clock Fall Time Input Rise Time Input Fall Time NOTES: 1. The parameters listed in this table are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes affecting these parameters. 2. All measurements are referenced to device GND. 3. Pins 2-3, 4-5. 4. Pins 8-10, 28, 29, 33, 34, 37, 39. 5. Pins 6, 7, 11-20, 22-27, 30-32, 38. 6. Pins 8-20, 22-29, 33, 34. SYMBOL CD CH CG Cl CO TLHC THLC TLHI THLI (NOTE 1) CONDITIONS VDD = Open, f = 1MHz, Note 2, 3 VDD = GND, f = 1MHz, Note 2, 3 VDD = Open, f = 1MHz, Note 2, 3 VDD = Open, f = 1MHz, Note 2, 4 VDD = Open, f = 1MHz, Note 2, 5 CLK = 1MHz, From 0.7V to 3.5V CLK = 1MHz, From 3.5V to 0.7V From 0.7V to 3.5V, Note 6 From 3.5V to 0.7V, Note 6 MIN MAX 20 20 20 15 15 10 10 15 15 UNITS pF pF pF pF pF ns ns ns ns 193 HS-3282 Timing Waveforms TX/R TX ENABLE DATA BUS PL1 PL2 D/R1 D/R2 EN1 EN2 SEL TIME INTERVAL A TIME INTERVAL B TIME INTERVAL C TIME INTERVAL D TIME INTERVAL E BUS IS BEING USED AS AN OUTPUT BUS IS BEING USED AS AN INPUT FIGURE 2. TYPICAL INTERFACE TIMING SEQUENCE 429DI BIT 32 tD/R tEND/R D/R tD/REN EN tSELEN SEL tENDATA BD00-15 WORD 1 tSELEN tENSEL tEN tDATAEN tENDATA WORD 2 tDATAEN tENSEL tENEN tEN OR SEL BD00-15 WORD 2 WORD 1 FIGURE 3. RECEIVER TIMING 194 HS-3282 Timing Waveforms (Continued) tCWSTR CWSTR tCWHLD tCWSET BD00-15 CONTROL WORD FIGURE 4. CONTROL WORD TIMING PL1 tPL PL2 tPL TX/R tDWSET tDWHLD BD00-15 WORD 1 WORD 2 tDWSET tDWHLD tPL12 tTX/R FIGURE 5. TRANSMITTER FIFO WRITE TIMING TX/R tENTX/R ENTX tENDAT 42900 BIT 1 tBIT tNUL BIT 2 BIT 32 tNUL tGAP BIT 1 BIT 32 tNUL tDTX/R FIGURE 6. TRANSMITTER OUTPUT TIMING 195 HS-3282 Timing Waveforms (Continued) 429DI BIT 32 tD/R D/R tD/REN EN tSELEN SEL tENPL PL1 tENPL PL2 tPLEN tEN tENEN tSELEN tENSEL tEN tEND/R tENSEL tPLEN tTX/R TX/R tTX/REN ENTX tENDAT 429D0 BIT 1 BIT 32 tDTX/R tNUL tENTX/R FIGURE 7. REPEATER OPERATION TIMING 196 HS-3282 Burn-In Circuits HS-3282 CERDIP C GND F4 GND F4 GND NC NC F9 VDD F8 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 VDD 1 VDD 2 DI1(A) 3 DI1(B) 4 DI2(A) 5 DI2(B) 6 D/R1 7 D/R2 8 SEL 9 EN1 10 EN2 11 BD15 12 BD14 13 BD13 14 BD12 15 BD11 16 BD10 17 BD09 18 BD08 19 BD07 20 BD06 NC 40 MR 39 TX CLK 38 CLK 37 NC 36 NC 35 CWSTR 34 ENTX 33 429D0 32 429D0 31 TX/R 30 PL2 29 PL1 28 BD00 27 BD01 26 BD02 25 BD03 24 BD04 23 BD05 22 21 NC F15 NC F0 NC NC VDD GND NC NC NC F8 F8 F0 F1 F2 F3 F4 F5 GND All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 197 Burn-In Circuits HS-3282 CLCC GND F4 VDD GND GND F15 NC NC NC NC NC 39 NC 38 CWSTR 37 ENTX 36 D0 35 D0 34 TX/R 33 PL2 32 PL1 31 BD00 30 BD01 29 BD09 BD08 BD07 BD06 BD05 BD04 BD03 BD02 GND NC C F4 F0 CLK 6 NC 5 DI2(B) 4 DI2(A) 3 DI1(B) 2 DI1(A) 1 44 43 42 41 40 TXCLK VCC MR NC NC NC NC F9 VDD F8 F15 F14 F13 F12 F11 7 8 9 NC NC NC VDD GND NC NC NC F8 F8 F0 F1 D/R1 D/R2 10 SEL 11 EN1 12 EN2 13 BD15 14 BD14 15 BD13 16 BD12 17 BD11 BD10 NC 18 19 20 21 22 23 24 25 26 27 28 GND NC F10 F09 F08 F07 F06 F05 F04 F03 NOTES: 1. Resistors = 47kΩ, 5%, 1/4W (Min) 2. GND = Ground 3. VDD = +5.5V, ±0.5V 4. C = 0.01mF/Socket (Min) 5. F0 = 100kHz, F1 = F0/2, . . . F15 = F14/2 198 F02 Die Characteristics DIE DIMENSIONS: 246 x 224 x 19 mils) (6250 x 5700 x 483µm) METALLIZATION: Type: Si-Al Thickness: 11kÅ ±2kÅ GLASSIVATION: Type: SiO2 Thickness: 8kA ±1kÅ WORST CASE CURRENT DENSITY: 2 x 105 A/cm2 Metallization Mask Layout HS-3282 (5) 429DI2(B) (4) 429DI2(A) (3) 429DI1(B) (2) 429DI1(A) (1) VDD (38) TX CLK D/R2 (7) (36) N/C SEL (8) EN1 (9) (37) CLK (35) N/C (34) CWSTR (33) ENTX (32) 429D0 (31) 429D0 (30) TX/R (29) PL2 (28) PL1 (27) BD00 (6) D/R1 (40) N/C BD04 (23) BD03 (24) EN1 (10) BD15 (11) BD14 (12) BD13 (13) BD12 (14) BD11 (15) BD10 (16) BD09 (17) BD08 (18) BD07 (19) BD06 (20) BD05 (22) (39) MR BD02 (25) All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 199 BD01 (26) GND (21)