ICL3241E

±15kV ESD Protected, +3V to +5.5V, 1µA, 250kbps, RS-232 Transmitters/Receivers ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E The Intersil ICL32xxE devices are 3.0V to 5.5V powered RS-232 transmitters/receivers which meet ElA/TIA-232 and V.28/V.24 specifications, even at VCC = 3.0V. Additionally, they provide ±15kV ESD protection (IEC61000-4-2 Air Gap and Human Body Model) on transmitter outputs and receiver inputs (RS-232 pins). Targeted applications are PDAs, Palmtops, and notebook and laptop computers where the low operational, and even lower standby, power consumption is critical. Efficient on-chip charge pumps, coupled with manual and automatic power-down functions (except for the ICL3232E), reduce the standby supply current to a 1µA trickle. Small footprint packaging, and the use of small, low value capacitors ensure board space savings as well. Data rates greater than 250kbps are guaranteed at worst case load conditions. This family is fully compatible with 3.3V-only systems, mixed 3.3V and 5.0V systems, and 5.0V-only systems. The ICL324XE are 3-driver, 5-receiver devices that provide a complete serial port suitable for laptop or notebook computers. Both devices also include noninverting always-active receivers for “wake-up” capability. The ICL3221E, ICL3223E and ICL3243E, feature an automatic power-down function which powers down the on-chip power-supply and driver circuits. This occurs when an attached peripheral device is shut off or the RS-232 cable is removed, conserving system power automatically without changes to the hardware or operating system. These devices power up again when a valid RS-232 voltage is applied to any receiver input. Table 1 summarizes the features of the devices represented by this data sheet, while Application Note AN9863 summarizes the features of each device comprising the ICL32xxE 3V family. ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Features • ESD Protection for RS-232 I/O Pins to ±15kV (IEC61000) • Drop in Replacements for MAX3221E, MAX3222E, MAX3223E, MAX3232E, MAX3241E, MAX3243E, SP3243E • ICL3221E is a Low Power, Pin Compatible Upgrade for 5V MAX221E • ICL3222E is a Low Power, Pin Compatible Upgrade for 5V MAX242E, and SP312E • ICL3232E is a Low Power Upgrade for HIN232E, ICL232 and Pin Compatible Competitor Devices • RS-232 Compatible with VCC = 2.7V • Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V • Latch-Up Free • On-Chip Voltage Converters Require Only Four External 0.1µF Capacitors • Manual and Automatic Power-Down Features • Guaranteed Mouse Driveability (ICL324xE Only) • Receiver Hysteresis For Improved Noise Immunity • Guaranteed Minimum Data Rate. . . . . . . . 250kbps • Wide Power Supply Range . . . . Single +3V to +5.5V • Low Supply Current in Power-Down State . . . . . 1µA • Pb-Free Available (RoHS Compliant) Applications • Any System Requiring RS-232 Communication Ports - Battery Powered, Hand-Held, and Portable Equipment - Laptop Computers, Notebooks, Palmtops - Modems, Printers and other Peripherals - Digital Cameras - Cellular/Mobile Phones Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” February 22, 2010 FN4910.21 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2000-2005, 2007-2008, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E TABLE 1. SUMMARY OF FEATURES NUMBER OF MONITOR RECEIVERS (ROUTB) 0 0 0 0 2 1 DATA RATE (kbps) 250 250 250 250 250 250 RECEIVER ENABLE FUNCTION? Yes Yes Yes No Yes No AUTOMATIC POWERDOWN FUNCTION? Yes No Yes No No Yes PART NUMBER NUMBER NUMBER OF Tx OF Rx ICL3221E ICL3222E ICL3223E ICL3232E ICL3241E ICL3243E 1 2 2 2 3 3 1 2 2 2 5 5 READY OUTPUT? No No No No No No MANUAL POWER-DOWN? Yes Yes Yes No Yes Yes Typical Operating Circuits ICL3221E C3 (OPTIONAL CONNECTION, NOTE) +3.3V 15 VCC V+ 3 + C3 0.1µF C4 + V- 7 T1 13 + 0.1µF T1OUT R1IN RS-232 LEVELS 8 R1 1 EN FORCEOFF 12 FORCEON GND 14 INVALID 16 10 VCC TO POWER CONTROL LOGIC 5kΩ + 0.1µF C1 0.1µF C2 0.1µF 2 + C1+ 4 C15 + C2+ 6 C211 T1IN TTL/CMOS LOGIC LEVELS R1OUT 9 NOTE: THE NEGATIVE TERMINAL OF C3 CAN BE CONNECTED TO EITHER VCC OR GND 2 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Typical Operating Circuits +3.3V (Continued) ICL3222E C3 (OPTIONAL CONNECTION, NOTE) + 0.1µF + 2 4 5 + 6 12 11 C1+ C1C2+ C2T1 T2 V17 VCC 3 V+ 7 + 15 8 + C3 0.1µF C4 0.1µF + T1OUT T2OUT RS-232 LEVELS 14 R1 5kΩ 9 R2 5kΩ 18 R2IN R1IN GND 16 SHDN VCC C1 0.1µF C2 0.1µF T1IN T2IN TTL/CMOS LOGIC LEVELS R1OUT 13 R2OUT 10 1 EN NOTE: THE NEGATIVE TERMINAL OF C3 CAN BE CONNECTED TO EITHER VCC OR GND ICL3223E +3.3V + 0.1µF 2 + 4 5 + 6 13 12 C1+ C1C2+ C2T1 T2 19 VCC V+ 3 + C3 0.1µF C4 0.1µF + T1OUT T2OUT RS-232 LEVELS C1 0.1µF C2 0.1µF V- 7 17 8 T1IN T2IN TTL/CMOS LOGIC LEVELS R1OUT 15 R1 5kΩ 16 R1IN R2OUT 10 1 EN R2 5kΩΩ 9 R2IN FORCEOFF 14 FORCEON GND 18 INVALID 20 11 VCC TO POWER CONTROL LOGIC 3 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Typical Operating Circuits +3.3V + (Continued) ICL3232E 0.1µF 1 + + 3 4 5 11 10 12 R1 5kΩ 8 R2 GND 15 5kΩ R2IN C1+ C1C2+ C2T1 T2 V16 VCC V+ 2 + C3 (OPTIONAL CONNECTION, NOTE) NOTE: THE NEGATIVE TERMINAL OF C3 CAN BE CONNECTED TO EITHER VCC OR GND C1 0.1µF C2 0.1µF + C3 0.1µF 6 14 7 C4 0.1µF + T1OUT T2OUT T1IN T2IN R1OUT TTL/CMOS LOGIC LEVELS 13 R1IN RS-232 LEVELS R2OUT 9 4 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Typical Operating Circuits ICL3241E +3.3V + 0.1µF C1+ C1C2+ C2T1 T2 T3 26 VCC V+ 27 (Continued) ICL3243E +3.3V + C1 0.1µF C2 0.1µF 0.1µF 28 + 24 1 + 2 C1+ C1C2+ C2T1 V3 26 VCC 27 V+ + C3 0.1µF C1 0.1µF C2 0.1µF T1IN T2IN T3IN R1OUTB R2OUTB TTL/CMOS LOGIC LEVELS R1OUT 28 + 24 + 1 2 + C3 0.1µF C4 0.1µF + T1OUT V- 3 9 10 11 C4 0.1µF + 14 13 12 21 20 19 R1 T1IN RS-232 LEVELS 14 9 T1OUT 10 T2OUT 11 T3OUT RS-232 LEVELS T2OUT T3OUT T2IN T3IN 13 12 T2 T3 20 R2OUTB 4 5kΩ 5 R2 5kΩ 6 R3 5kΩ 7 R4 5kΩ 8 EN R5 5kΩ R5IN R5OUT 15 23 SHDN GND 25 VCC TO POWER CONTROL LOGIC 22 21 FORCEOFF INVALID GND 25 R5 FORCEON 5kΩ R4IN R4OUT 16 R4 5kΩ 8 R5IN R3IN RS-232 LEVELS 17 R3OUT R3 5kΩ 7 R4IN R2IN R1IN R1OUT TTL/CMOS LOGIC LEVELS R2OUT R1 18 R2 5kΩ 6 R3IN RS-232 LEVELS 5kΩ 5 R2IN 19 4 R1IN R2OUT 18 17 R3OUT 16 R4OUT 15 R5OUT 23 22 VCC 5 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Pin Configurations ICL3221E (16 LD SSOP, TSSOP) TOP VIEW EN 1 C1+ 2 V+ 3 C1- 4 C2+ 5 C2- 6 V- 7 R1IN 8 16 FORCEOFF 15 VCC 14 GND 13 T1OUT 12 FORCEON 11 T1IN 10 INVALID 9 R1OUT ICL3222E (18 LD PDIP, SOIC) TOP VIEW EN 1 C1+ 2 V+ 3 C1- 4 C2+ 5 C2- 6 V- 7 T2OUT 8 R2IN 9 18 SHDN 17 VCC 16 GND 15 T1OUT 14 R1IN 13 R1OUT 12 T1IN 11 T2IN 10 R2OUT ICL3222E (20 LD SSOP, TSSOP) TOP VIEW EN 1 C1+ 2 V+ 3 C1- 4 C2+ 5 C2- 6 V- 7 T2OUT 8 R2IN 9 R2OUT 10 20 SHDN 19 VCC 18 GND 17 T1OUT 16 R1IN 15 R1OUT 14 NC 13 T1IN 12 T2IN 11 NC ICL3223E (20 LD SSOP, TSSOP) TOP VIEW EN 1 C1+ 2 V+ 3 C1- 4 C2+ 5 C2- 6 V- 7 T2OUT 8 R2IN 9 R2OUT 10 20 FORCEOFF 19 VCC 18 GND 17 T1OUT 16 R1IN 15 R1OUT 14 FORCEON 13 T1IN 12 T2IN 11 INVALID ICL3232E (16 LD SOIC, SSOP, TSSOP-16) TOP VIEW C1+ 1 V+ 2 C1- 3 C2+ 4 C2- 5 V- 6 T2OUT 7 R2IN 8 16 VCC 15 GND 14 T1OUT 13 R1IN 12 R1OUT 11 T1IN 10 T2IN 9 R2OUT ICL3232E (20 LD TSSOP-20) TOP VIEW NC 1 C1+ 2 V+ 3 C1- 4 C2+ 5 C2- 6 V- 7 T2OUT 8 R2IN 9 NC 10 20 NC 19 VCC 18 GND 17 T1OUT 16 R1IN 15 R1OUT 14 T1IN 13 T2IN 12 R2OUT 11 NC 6 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Pin Configurations (Continued) ICL3243E (28 LD SOIC, SSOP, TSSOP) TOP VIEW C2+ 1 C2- 2 V- 3 R1IN 4 R2IN 5 R3IN 6 R4IN 7 R5IN 8 T1OUT 9 T2OUT 10 T3OUT 11 T3IN 12 T2IN 13 T1IN 14 28 C1+ 27 V+ 26 VCC 25 GND 24 C123 FORCEON 22 FORCEOFF 21 INVALID 20 R2OUTB 19 R1OUT 18 R2OUT 17 R3OUT 16 R4OUT 15 R5OUT ICL3241E (28 LD SOIC, SSOP, TSSOP) TOP VIEW C2+ 1 C2- 2 V- 3 R1IN 4 R2IN 5 R3IN 6 R4IN 7 R5IN 8 T1OUT 9 T2OUT 10 T3OUT 11 T3IN 12 T2IN 13 T1IN 14 28 C1+ 27 V+ 26 VCC 25 GND 24 C123 EN 22 SHDN 21 R1OUTB 20 R2OUTB 19 R1OUT 18 R2OUT 17 R3OUT 16 R4OUT 15 R5OUT Pin Descriptions PIN VCC V+ VGND C1+ C1C2+ C2TIN TOUT RIN ROUT ROUTB INVALID EN SHDN System power supply input (3.0V to 5.5V). Internally generated positive transmitter supply (+5.5V). Internally generated negative transmitter supply (-5.5V). Ground connection. External capacitor (voltage doubler) is connected to this lead. External capacitor (voltage doubler) is connected to this lead. External capacitor (voltage inverter) is connected to this lead. External capacitor (voltage inverter) is connected to this lead. TTL/CMOS compatible transmitter Inputs. ±15kV ESD Protected, RS-232 level (nominally ±5.5V) transmitter outputs. ±15kV ESD Protected, RS-232 compatible receiver inputs. TTL/CMOS level receiver outputs. TTL/CMOS level, noninverting, always enabled receiver outputs. Active low output that indicates if no valid RS-232 levels are present on any receiver input. Active low receiver enable control; doesn’t disable ROUTB outputs. Active low input to shut down transmitters and on-board power supply, to place device in low power mode. FUNCTION FORCEOFF Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and FORCEON (see Table 2). FORCEON Active high input to override automatic power-down circuitry thereby keeping transmitters active (FORCEOFF must be high). 7 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Ordering Information PART NUMBER (Note 3) ICL3221ECA ICL3221ECA-T (Note 1) ICL3221ECAZ (Note 2) ICL3221ECAZ-T (Notes 1, 2) ICL3221ECAZA (Note 2) ICL3221ECAZA-T (Notes 1, 2) ICL3221ECV ICL3221ECVZ (Note 2) ICL3221ECVZ-T (Notes 1, 2) ICL3221EIA ICL3221EIA-T (Note 1) ICL3221EIAZ (Note 2) ICL3221EIAZ-T (Notes 1, 2) ICL3221EIVZ (Note 2) ICL3221EIVZ-T (Notes 1, 2) ICL3222ECA-T (Note 1) ICL3222ECAZ (Note 2) ICL3222ECAZ-T (Notes 1, 2) ICL3222ECP ICL3222ECV-T (Note 1) ICL3222ECVZ (Note 2) ICL3222ECVZ-T (Notes 1, 2) ICL3222EIAZ (Note 2) ICL3222EIAZ-T (Notes 1, 2) ICL3222EIB ICL3222EIB-T (Note 1) ICL3222EIBZ (Note 2) ICL3222EIBZ-T (Notes 1, 2) ICL3222EIV ICL3222EIV-T (Note 1) ICL3222EIVZ (Note 2) ICL3222EIVZ-T (Notes 1, 2) ICL3223ECA ICL3223ECA-T (Note 1) ICL3223ECAZ (Note 2) ICL3223ECAZ-T (Notes 1, 2) ICL3223ECV ICL3223ECVZ (Note 2) ICL3223ECVZ-T (Notes 1, 2) PART MARKING ICL 3221ECA ICL 3221ECA ICL32 21ECAZ ICL32 21ECAZ ICL32 21ECAZ ICL32 21ECAZ 3221 ECV 3221 ECVZ 3221 ECVZ ICL 3221EIA ICL 3221EIA ICL32 21EIAZ ICL32 21EIAZ 3221 EIVZ 3221 EIVZ ICL 3222ECA ICL32 22ECAZ ICL32 22ECAZ ICL3222ECP ICL 3222ECV ICL32 22ECVZ ICL32 22ECVZ ICL32 22EIAZ ICL32 22EIAZ ICL3222EIB ICL3222EIB 3222EIBZ 3222EIBZ ICL 3222EIV ICL 3222EIV ICL32 22EIVZ ICL32 22EIVZ ICL 3223ECA ICL 3223ECA ICL32 23ECAZ ICL32 23ECAZ ICL 3223ECV ICL32 23ECVZ ICL32 23ECVZ TEMP RANGE (°C) 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 PACKAGE 16 Ld SSOP 16 Ld SSOP 16 Ld SSOP (Pb-free) 16 Ld SSOP (Pb-free) 16 Ld SSOP (Pb-free) 16 Ld SSOP (Pb-free) 16 Ld TSSOP 16 Ld TSSOP (Pb-free) 16 Ld TSSOP (Pb-free) 16 Ld SSOP 16 Ld SSOP 16 Ld SSOP (Pb-free) 16 Ld SSOP (Pb-free) 16 Ld TSSOP (Pb-free) 16 Ld TSSOP (Pb-free) 20 Ld SSOP 20 Ld SSOP (Pb-free) 20 Ld SSOP (Pb-free) 18 Ld PDIP 20 Ld TSSOP 20 Ld TSSOP (Pb-free) 20 Ld TSSOP (Pb-free) 20 Ld SSOP (Pb-free) 20 Ld SSOP (Pb-free) 18 Ld SOIC 18 Ld SOIC 18 Ld SOIC (Pb-free) 18 Ld SOIC (Pb-free) 20 Ld TSSOP 20 Ld TSSOP 20 Ld TSSOP (Pb-free) 20 Ld TSSOP (Pb-free) 20 Ld SSOP 20 Ld SSOP 20 Ld SSOP (Pb-free) 20 Ld SSOP (Pb-free) 20 Ld TSSOP 20 Ld TSSOP (Pb-free) 20 Ld TSSOP (Pb-free) PKG. DWG. # M16.209 M16.209 M16.209 M16.209 M16.209 M16.209 M16.173 M16.173 M16.173 M16.209 M16.209 M16.209 M16.209 M16.173 M16.173 M20.209 M20.209 M20.209 E18.3 M20.173 M20.173 M20.173 M20.209 M20.209 M18.3 M18.3 M18.3 M18.3 M20.173 M20.173 M20.173 M20.173 M20.209 M20.209 M20.209 M20.209 M20.173 M20.173 M20.173 8 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Ordering Information PART NUMBER (Note 3) ICL3223EIA ICL3223EIA-T (Note 1) ICL3223EIAZ (Note 2) ICL3223EIAZ-T (Notes 1, 2) ICL3223EIV ICL3223EIVZ (Note 2) ICL3223EIVZ-T (Notes 1, 2) ICL3232ECA ICL3232ECA-T (Note 1) ICL3232ECAZ (Note 2) ICL3232ECAZ-T (Notes 1, 2) ICL3232ECBZ (Note 2) ICL3232ECBZ-T (Notes 1, 2) ICL3232ECBN ICL3232ECBN-T (Note 1) ICL3232ECBNZ (Note 2) ICL 3223EIA ICL 3223EIA (Continued) TEMP RANGE (°C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 -40 to +125 -40 to +125 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 0 to +70 PACKAGE 20 Ld SSOP 20 Ld SSOP 20 Ld SSOP (Pb-free) 20 Ld SSOP (Pb-free) 20 Ld TSSOP 20 Ld TSSOP (Pb-free) 20 Ld TSSOP (Pb-free) 16 Ld SSOP 16 Ld SSOP 16 Ld SSOP (Pb-free) 16 Ld SSOP (Pb-free) 16 Ld SOIC (Pb-free) 16 Ld SOIC (Pb-free) 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC (Pb-free) 16 Ld SOIC (Pb-free) 16 Ld TSSOP 16 Ld TSSOP (Pb-free) 16 Ld TSSOP (Pb-free) 20 Ld TSSOP (Pb-free) 20 Ld TSSOP (Pb-free) 16 Ld TSSOP (Pb-free) 16 Ld TSSOP (Pb-free) 16 Ld SSOP 16 Ld SSOP (Pb-free) 16 Ld SSOP (Pb-free) 16 Ld SOIC 16 Ld SOIC (Pb-free) 16 Ld SOIC (Pb-free) 16 Ld SOIC (Pb-free) 16 Ld SOIC (Pb-free) 16 Ld TSSOP 16 Ld TSSOP 16 Ld TSSOP (Pb-free) 16 Ld TSSOP (Pb-free) 20 Ld TSSOP (Pb-free) 20 Ld TSSOP (Pb-free) 28 Ld SSOP PKG. DWG. # M20.209 M20.209 M20.209 M20.209 M20.173 M20.173 M20.173 M16.209 M16.209 M16.209 M16.209 M16.3 M16.3 M16.15 M16.15 M16.15 M16.15 M16.173 M16.173 M16.173 M20.173 M20.173 M16.173 M16.173 M16.209 M16.209 M16.209 M16.3 M16.3 M16.3 M16.15 M16.15 M16.173 M16.173 M16.173 M16.173 M20.173 M20.173 M28.209 PART MARKING ICL32 23EIAZ ICL32 23EIAZ ICL 3223EIV ICL32 23EIVZ ICL32 23EIVZ ICL 3232ECA ICL 3232ECA 3232 ECAZ 3232 ECAZ 3232ECBZ 3232ECBZ 3232ECBN 3232ECBN 3232ECBNZ ICL3232ECBNZ-T (Notes 1, 2) 3232ECBNZ ICL3232ECV-16T (Note 1) ICL3232ECV-16Z (Note 2) 3232E CV-16 3232E CV-16Z ICL3232ECV-16Z-T (Notes 1, 2) 3232E CV-16Z ICL3232ECV-20Z (Note 2) ICL3232 ECV-20Z ICL3232ECV-20Z-T (Notes 1, 2) ICL3232 ECV-20Z ICL3232EFV-16Z (Note 2) 3232E FV-16Z ICL3232EFV-16Z-T (Notes 1, 2) 3232E FV-16Z ICL3232EIA-T (Note 1) ICL3232EIAZ (Note 2) ICL3232EIAZ-T (Notes 1, 2) ICL3232EIB-T (Note 1) ICL3232EIBZ (Note 2) ICL3232EIBZ-T (Notes 1, 2) ICL3232EIBNZ (Note 2) ICL3232EIBNZ-T (Notes 1, 2) ICL3232EIV-16 ICL3232EIV-16-T (Note 1) ICL3232EIV-16Z (Note 2) ICL3232 EIA 3232 EIAZ 3232 EIAZ ICL3232EIB 3232EIBZ 3232EIBZ 3232EIBNZ 3232EIBNZ 3232E IV-16 3232E IV-16 3232E IV-16Z ICL3232EIV-16Z-T (Notes 1, 2) 3232E IV-16Z ICL3232EIV-20Z (Note 2) ICL3232 EIV-20Z ICL3232EIV-20Z-T (Notes 1, 2) ICL3232 EIV-20Z ICL3241ECA ICL 3241ECA 9 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Ordering Information PART NUMBER (Note 3) ICL3241ECA-T (Note 1) ICL3241ECAZ (Note 2) ICL3241ECAZ-T (Notes 1, 2) ICL3241ECBZ (Note 2) ICL3241ECBZ-T (Notes 1, 2) ICL3241ECVZ (Note 2) ICL3241EIA-T (Note 1) ICL3241EIAZ (Note 2) ICL3241EIAZ-T (Notes 1, 2) ICL3241EIBZ (Note 2) ICL3241EIBZ-T (Notes 1, 2) ICL3241EIV-T (Note 1) ICL3241EIVZ (Note 2) ICL3241EIVZ-T (Notes 1, 2) ICL3243ECA ICL3243ECA-T (Note 1) ICL3243ECAZ (Note 2) ICL3243ECAZ-T (Notes 1, 2) ICL3243ECBZ (Note 2) ICL3243ECBZ-T (Notes 1, 2) ICL3243ECV-T (Note 1) ICL3243ECVZ (Note 2) ICL3243ECVZ-T (Notes 1, 2) ICL3243EIA-T (Note 1) ICL3243EIAZ (Note 2) ICL3243EIAZ-T (Notes 1, 2) ICL3243EIV ICL3243EIVZ (Note 2) ICL3243EIVZ-T (Notes 1, 2) NOTES: ICL 3241ECA (Continued) TEMP RANGE (°C) 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 0 to +70 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE 28 Ld SSOP 28 Ld SSOP (Pb-free) 28 Ld SSOP (Pb-free) 28 Ld SOIC (Pb-free) 28 Ld SOIC (Pb-free) 28 Ld TSSOP (Pb-free) 28 Ld SSOP 28 Ld SSOP (Pb-free) 28 Ld SSOP (Pb-free) 28 Ld SOIC (Pb-free) 28 Ld SOIC (Pb-free) 28 Ld TSSOP 28 Ld TSSOP (Pb-free) 28 Ld TSSOP (Pb-free) 28 Ld SSOP 28 Ld SSOP 28 Ld SSOP (Pb-free) 28 Ld SSOP (Pb-free) 28 Ld SOIC (Pb-free) 28 Ld SOIC (Pb-free) 28 Ld TSSOP 28 Ld TSSOP (Pb-free) 28 Ld TSSOP (Pb-free) 28 Ld SSOP 28 Ld SSOP (Pb-free) 28 Ld SSOP (Pb-free) 28 Ld TSSOP 28 Ld TSSOP (Pb-free) 28 Ld TSSOP (Pb-free) PKG. DWG. # M28.209 M28.209 M28.209 M28.3 M28.3 M28.173 M28.209 M28.209 M28.209 M28.3 M28.3 M28.173 M28.173 M28.173 M28.209 M28.209 M28.209 M28.209 M28.3 M28.3 M28.173 M28.173 M28.173 M28.209 M28.209 M28.209 M28.173 M28.173 M28.173 PART MARKING ICL3241 ECAZ ICL3241 ECAZ ICL3241ECBZ ICL3241ECBZ ICL3241 ECVZ ICL 3241EIA ICL3241 EIAZ ICL3241 EIAZ ICL3241EIBZ ICL3241EIBZ ICL3241 EIV ICL3241 EIVZ ICL3241 EIVZ ICL 3243ECA ICL 3243ECA ICL32 43ECAZ ICL32 43ECAZ ICL3243ECBZ ICL3243ECBZ ICL3243 ECV ICL3243 ECVZ ICL3243 ECVZ ICL 3243EIA ICL32 43EIAZ ICL32 43EIAZ ICL3243 EIV ICL3243 EIVZ ICL3243 EIVZ 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E. For more information on MSL please see techbrief TB363. 10 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Table of Contents Related Literature ............................................................................................................................... 1 Typical Operating Circuits.................................................................................................................... 2 Pin Configurations ............................................................................................................................... 6 Pin Descriptions .................................................................................................................................. 7 Ordering Information .......................................................................................................................... 8 Absolute Maximum Ratings .............................................................................................................. 12 Thermal Information ........................................................................................................................ 12 Recommended Operating Conditions ................................................................................................ 12 Electrical Specifications .................................................................................................................... 12 Detailed Description .......................................................................................................................... 14 Charge-Pump ................................................................................................................................. 14 Transmitters................................................................................................................................... 14 Receivers ....................................................................................................................................... 14 Low Power Operation ........................................................................................................................ 15 Pin Compatible Replacements for 5V Devices ...................................................................................... 15 Power-Down Functionality (Except ICL3232E) .................................................................................. 15 Software Controlled (Manual) Power-Down ......................................................................................... 15 Automatic Power-Down (ICL3221E, ICL3223E, ICL3243E Only) ............................................................. 17 Receiver ENABLE Control (ICL3221E, ICL3222E, ICL3223E, ICL3241E Only)............................................ 18 Capacitor Selection............................................................................................................................ 18 Power Supply Decoupling .................................................................................................................. 18 Operation Down to 2.7V .................................................................................................................... 18 Transmitter Outputs when Exiting Power-Down ................................................................................ 18 Mouse Driveability ............................................................................................................................. 18 High Data Rates................................................................................................................................. 19 Interconnection with 3V and 5V Logic ............................................................................................... 19 ±15kV ESD Protection ....................................................................................................................... 20 Human Body Model (HBM) Testing..................................................................................................... 20 IEC61000-4-2 Testing...................................................................................................................... 20 Typical Performance Curves VCC = 3.3V, TA = +25°C. ............................................................................. 20 Die Characteristics ............................................................................................................................ 21 Revision History ................................................................................................................................ 22 Products ............................................................................................................................................ 22 Package Outline Drawings ................................................................................................................. 23 11 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Absolute Maximum Ratings VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V Input Voltages TIN, FORCEOFF, FORCEON, EN, SHDN . . . . . . -0.3V to 6V RIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V Output Voltages TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V ROUT, INVALID . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V Short Circuit Duration TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous ESD Rating . . . . . . . . . . . . . . . . . . See Specification Table Thermal Information Thermal Resistance (Typical, Note 4) ΘJA (°C/W) 18 Ld PDIP Package* . . . . . . . . . . . . . . . . . 80 16 Ld Wide SOIC Package . . . . . . . . . . . . . . 100 16 Ld Narrow SOIC Package . . . . . . . . . . . . 115 18 Ld SOIC Package . . . . . . . . . . . . . . . . . . 75 28 Ld SOIC Package . . . . . . . . . . . . . . . . . . 75 16 Ld SSOP Package. . . . . . . . . . . . . . . . . . 135 20 Ld SSOP Package. . . . . . . . . . . . . . . . . . 122 16 Ld TSSOP Package . . . . . . . . . . . . . . . . . 145 20 Ld TSSOP Package . . . . . . . . . . . . . . . . . 140 28 Ld SSOP and TSSOP Packages. . . . . . . . . 100 Maximum Junction Temperature (Plastic Package) . +150°C Maximum Storage Temperature Range . . . -65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature Range ICL32xxECX . . . . . ICL32xxEFX . . . . . ICL32xxEIX. . . . . . Supply Voltage (VCC) Rx Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C . -40°C to +125°C . . -40°C to +85°C . . . . . 3.3V or 5V . . . -15V to +15V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 4. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified. Typicals are at TA = +25°C. Boldface limits apply over the operating temperature range. TEST CONDITIONS TEMP MIN (°C) (Note 6) TYP MAX (Note 6) UNITS PARAMETER DC CHARACTERISTICS Supply Current, Automatic Power-Down Supply Current, Power-Down Supply Current, Automatic Power-Down Disabled All RIN Open, FORCEON = GND, FORCEOFF = VCC (ICL3221E, ICL3223E, ICL3243E Only) FORCEOFF = SHDN = GND (Except ICL3232E) All Outputs Unloaded, VCC = 3.0V, ICL3241, FORCEON = FORCEOFF ICL3243 = SHDN = VCC VCC = 3.0V, ICL3223 VCC = 3.15V, ICL3221, ICL3222, ICL3223, ICL3232 25 25 25 25 25 - 1.0 1.0 0.3 0.7 0.3 10 10 1.0 3.0 1.0 µA µA mA mA mA LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS Input Logic Threshold Low TIN, FORCEON, FORCEOFF, EN, SHDN VCC = 3.3V VCC = 5.0V All but ICL3232EF ICL3232EF Full Full Full Full Full Full Full All but ICL3232EF ICL3232EF Full Full 2.0 2.4 ±0.01 ±0.01 ±0.05 0.8 ±1.0 ±10 ±10 0.4 V V V µA µA µA V V V Input Logic Threshold High TIN, FORCEON, FORCEOFF, EN, SHDN Input Leakage Current TIN, FORCEON, FORCEOFF, EN, SHDN Output Leakage Current (Except ICL3232E) Output Voltage Low Output Voltage High FORCEOFF = GND or EN = VCC IOUT = 1.6mA IOUT = -1.0mA VCC - 0.6 VCC - 0.1 VCC - 0.9 VCC - 0.1 12 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Electrical Specifications Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified. Typicals are at TA = +25°C. Boldface limits apply over the operating temperature range. (Continued) TEST CONDITIONS TEMP MIN (°C) (Note 6) TYP MAX (Note 6) UNITS PARAMETER AUTOMATIC POWER-DOWN (ICL3221E, ICL3223E, ICL3243E Only, FORCEON = GND, FORCEOFF = VCC) Receiver Input Thresholds to Enable Transmitters Receiver Input Thresholds to Disable Transmitters INVALID Output Voltage Low INVALID Output Voltage High Receiver Threshold to Transmitters Enabled Delay (tWU) Receiver Positive or Negative Threshold to INVALID High Delay (tINVH) Receiver Positive or Negative Threshold to INVALID Low Delay (tINVL) RECEIVER INPUTS Input Voltage Range Input Threshold Low VCC = 3.3V VCC = 5.0V Input Threshold High VCC = 3.3V VCC = 5.0V Input Hysteresis Input Resistance TRANSMITTER OUTPUTS Output Voltage Swing Output Resistance Output Short-Circuit Current Output Leakage Current VOUT = ±12V, VCC = 0V or 3V to 5.5V, Automatic Power-Down or FORCEOFF = SHDN = GND All Transmitter Outputs Loaded with 3kΩ to Ground VCC = V+ = V- = 0V, Transmitter Output = ±2V Full Full Full Full ±5.0 300 ±5.4 10M ±35 ±60 ±25 V Ω mA µA 25 25 25 25 25 25 25 -25 0.6 0.8 3 1.2 1.5 1.5 1.8 0.5 5 25 2.4 2.4 7 V V V V V V kΩ ICL32xxE Powers Up (see Figure 6) ICL32xxE Powers Down (see Figure 6) IOUT = 1.6mA IOUT = -1.0mA Full Full Full Full 25 -2.7 -0.3 VCC - 0.6 100 2.7 0.3 0.4 V V V V µs 25 - 1 - µs 25 - 30 - µs MOUSE DRIVEABILITY (ICL324XE Only) Transmitter Output Voltage T1IN = T2IN = GND, T3IN = VCC, T3OUT Loaded with 3kΩ to GND, T1OUT and T2OUT Loaded with (see Figure 9) 2.5mA Each TIMING CHARACTERISTICS Maximum Data Rate Receiver Propagation Delay RL = 3kΩ, CL = 1000pF, One Transmitter Switching Receiver Input to Receiver Output, CL = 150pF tPHL tPLH Full 25 25 25 250 500 0.15 0.15 200 kbps µs µs ns Full ±5 V Receiver Output Enable Time Normal Operation (Except ICL3232E) 13 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Electrical Specifications Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified. Typicals are at TA = +25°C. Boldface limits apply over the operating temperature range. (Continued) TEST CONDITIONS Normal Operation (Except ICL3232E) tPHL to tPLH (Note 5) tPHL to tPLH VCC = 3.3V, RL = 3kΩ to 7kΩ, Measured from 3V to -3V or -3V to 3V CL = 150pF to 2500pF CL = 150pF to 1000pF TEMP MIN (°C) (Note 6) 25 25 25 25 25 4 6 TYP 200 100 50 MAX (Note 6) UNITS 30 30 ns ns ns V/µs V/µs PARAMETER Receiver Output Disable Time Transmitter Skew Receiver Skew Transition Region Slew Rate ESD PERFORMANCE RS-232 Pins (TOUT, RIN) Human Body Model IEC61000-4-2 Contact Discharge IEC61000-4-2 Air Gap Discharge All Other Pins NOTES: 5. Transmitter skew is measured at the transmitter zero crossing points. 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Human Body Model 25 25 25 25 ±15 ±8 ±15 ±2 kV kV kV kV Detailed Description ICL32xxE interface ICs operate from a single +3V to +5.5V supply, guarantee a 250kbps minimum data rate, require only four small external 0.1µF capacitors, feature low power consumption, and meet all ElA RS-232C and V.28 specifications. The circuit is divided into three sections: charge pump, transmitters and receivers. Except for the ICL3232E, all transmitter outputs disable and assume a high impedance state when the device enters the power-down mode (see Table 2). These outputs may be driven to ±12V when disabled. All devices guarantee a 250kbps data rate for full load conditions (3kΩ and 1000pF), VCC ≥ 3.0V, with one transmitter operating at full speed. Under more typical conditions of VCC ≥ 3.3V, RL = 3kΩ, and CL = 250pF, one transmitter easily operates at 900kbps. Transmitter inputs float if left unconnected, and may cause ICC increases. Connect unused inputs to GND for the best performance. Charge-Pump Intersil’s new ICL32xxE family utilizes regulated onchip dual charge pumps as voltage doublers, and voltage inverters to generate ±5.5V transmitter supplies from a VCC supply as low as 3.0V. This allows these devices to maintain RS-232 compliant output levels over the ±10% tolerance range of 3.3V powered systems. The efficient on-chip power supplies require only four small, external 0.1µF capacitors for the voltage doubler and inverter functions at VCC = 3.3V. See “Capacitor Selection” on page 18 and Table 3 on page 18 for capacitor recommendations for other operating conditions. The charge pumps operate discontinuously (i.e., they turn off as soon as the V+ and V- supplies are pumped up to the nominal values), resulting in significant power savings. Receivers All the ICL32xxE devices contain standard inverting receivers that three-state (except for the ICL3232E) via the EN or FORCEOFF control lines. Additionally, the two ICL324XE products include noninverting (monitor) receivers (denoted by the ROUTB label) that are always active, regardless of the state of any control lines. All the receivers convert RS-232 signals to CMOS output levels and accept inputs up to ±25V while presenting the required 3kΩ to 7kΩ input impedance (see Figure 1) even if the power is off (VCC = 0V). The receivers’ Schmitt trigger input stage uses hysteresis to increase noise immunity and decrease errors due to slow input signal transitions. The ICL3221E, ICL3222E, ICL3223E, ICL3241E inverting receivers disable only when EN is driven high. ICL3243E receivers disable during forced (manual) power-down, but not during automatic power-down (see Table 2). FN4910.21 February 22, 2010 Transmitters The transmitters are proprietary, low dropout, inverting drivers that translate TTL/CMOS inputs to EIA/TIA-232 output levels. Coupled with the on-chip ±5.5V supplies, these transmitters deliver true RS-232 levels over a wide range of single supply system voltages. 14 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E ICL3241E and ICL3243E monitor receivers remain active even during manual power-down and forced receiver disable, making them extremely useful for Ring Indicator monitoring. Standard receivers driving powered down peripherals must be disabled to prevent current flow through the peripheral’s protection diodes (see Figures 2 and 3). This renders them useless for wake up functions, but the corresponding monitor receiver can be dedicated to this task as shown in Figure 3. VCC RXIN -25V ≤ VRIN ≤ +25V GND 5kΩ RXOUT GND ≤ VROUT ≤ VCC Power-Down Functionality (Except ICL3232E) The already low current requirement drops significantly when the device enters power-down mode. In power-down, supply current drops to 1µA, because the on-chip charge pump turns off (V+ collapses to VCC, V- collapses to GND), and the transmitter outputs three-state. Inverting receiver outputs may or may not disable in power-down; refer to Table 2 for details. This micro-power mode makes these devices ideal for battery powered and portable applications. Software Controlled (Manual) Power-Down Most devices in the ICL32xxE family provide pins that allow the user to force the IC into the low power, standby state. On the ICL3222E and ICL3241E, the power-down control is via a simple shutdown (SHDN) pin. Driving this pin high enables normal operation, while driving it low forces the IC into its power-down state. Connect SHDN to VCC if the power-down function isn’t needed. Note that all the receiver outputs remain enabled during shutdown (see Table 2). For the lowest power consumption during power-down, the receivers should also be disabled by driving the EN input high (see next section, and Figures 2 and 3). The ICL3221E, ICL3223E, and ICL3243E utilize a two pin approach where the FORCEON and FORCEOFF inputs determine the IC’s mode. For always enabled operation, FORCEON and FORCEOFF are both strapped high. To switch between active and power-down modes, under logic or software control, only the FORCEOFF input need be driven. The FORCEON state isn’t critical, as FORCEOFF dominates over FORCEON. Nevertheless, if strictly manual control over powerdown is desired, the user must strap FORCEON high to disable the automatic power-down circuitry. ICL3243E inverting (standard) receiver outputs also disable when the device is in manual power-down, thereby eliminating the possible current path through a shutdown peripheral’s input protection diode (see Figures 2 and 3). FIGURE 1. INVERTING RECEIVER CONNECTIONS Low Power Operation These 3V devices require a nominal supply current of 0.3mA, even at VCC = 5.5V, during normal operation (not in power-down mode). This is considerably less than the 5mA to 11mA current required by comparable 5V RS-232 devices, allowing users to reduce system power simply by switching to this new family. Pin Compatible Replacements for 5V Devices The ICL3221E, ICL3222E, ICL3232E are pin compatible with existing 5V RS-232 transceivers - See the “Features” section on page 1 for details. This pin compatibility coupled with the low ICC and wide operating supply range, make the ICL32xxE potential lower power, higher performance drop-in replacements for existing 5V applications. As long as the ±5V RS-232 output swings are acceptable, and transmitter input pull-up resistors aren’t required, the IICL32xxE should work in most 5V applications. When replacing a device in an existing 5V application, it is acceptable to terminate C3 to VCC as shown on the “Typical Operating Circuits” on page 2. Nevertheless, terminate C3 to GND if possible, as slightly better performance results from this configuration. TABLE 2. POWER-DOWN AND ENABLE LOGIC TRUTH TABLE RS-232 SIGNAL PRESENT FORCEOFF AT RECEIVER OR SHDN FORCEON EN TRANSMITTER INPUT? INPUT INPUT INPUT OUTPUTS ICL3222E, ICL3241E N/A N/A N/A N/A L L H H N/A N/A N/A N/A L H L H High-Z High-Z Active Active ROUTB RECEIVER OUTPUTS OUTPUTS (NOTE 7) Active High-Z Active High-Z Active Active Active Active INVALID OUTPUT N/A N/A N/A N/A MODE OF OPERATION Manual Power-Down Manual Power-Down with Receiver Disabled Normal Operation Normal Operation with Receiver Disabled 15 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E TABLE 2. POWER-DOWN AND ENABLE LOGIC TRUTH TABLE (Continued) RS-232 SIGNAL PRESENT FORCEOFF AT RECEIVER OR SHDN FORCEON EN TRANSMITTER INPUT? INPUT INPUT INPUT OUTPUTS ICL3221E, ICL3223E No No Yes Yes No No Yes Yes No No ICL3243E No Yes No Yes No NOTE: 7. Applies only to the ICL3241E and ICL3243E. H H H L L H L L X X N/A N/A N/A N/A N/A Active Active High-Z High-Z High-Z Active Active Active High-Z High-Z Active Active Active Active Active L H L H L Normal Operation (Auto Power-Down Disabled) Normal Operation (Auto Power-Down Enabled) Power-Down Due to Auto Power-Down Logic Manual Power-Down Manual Power-Down H H H H H H L L L L H H L L L L X X X X L H L H L H L H L H Active Active Active Active High-Z High-Z High-Z High-Z High-Z High-Z Active High-Z Active High-Z Active High-Z Active High-Z Active High-Z N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A L L H H L L H H L L Normal Operation (Auto Power-Down Disabled) Normal Operation (Auto Power-Down Enabled) Power-Down Due to Auto Power-Down Logic Manual Power-Down Manual Power-Down with Receiver Disabled Manual Power-Down Manual Power-Down with Receiver Disabled ROUTB RECEIVER OUTPUTS OUTPUTS (NOTE 7) INVALID OUTPUT MODE OF OPERATION The INVALID output always indicates whether or not a valid RS-232 signal is present at any of the receiver inputs (see Table 2), giving the user an easy way to determine when the interface block should power down. In the case of a disconnected interface cable where all the receiver inputs are floating (but pulled to GND by the internal receiver pull down resistors), the INVALID logic detects the invalid levels and drives the output low. The power management logic then uses this indicator to power down the interface block. Reconnecting the cable restores valid levels at the receiver inputs, INVALID switches high, and the power management logic wakes up the interface block. INVALID can also be used to indicate the DTR or RING INDICATOR signal, as long as the other receiver inputs are floating, or driven to GND (as in the case of a powered down driver). Connecting FORCEOFF and FORCEON together disables the automatic power-down feature, enabling them to function as a manual SHUTDOWN input (see Figure 4). VCC VCC CURRENT FLOW VOUT = VCC VCC Rx POWERED DOWN UART Tx GND SHDN = GND OLD RS-232 CHIP FIGURE 2. POWER DRAIN THROUGH POWERED DOWN PERIPHERAL 16 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E VCC TRANSITION DETECTOR TO WAKE-UP LOGIC VCC R2OUTB RX POWERED DOWN UART VOUT = HI-Z R2OUT TX T1IN T1OUT FORCEOFF = GND OR SHDN = GND, EN = VCC R2IN ICL324XE FORCEOFF FORCEON POWER MANAGEMENT UNIT MASTER POWER-DOWN LINE 0.1µF 1MΩ ICL3221E, ICL3223E, ICL3243E FIGURE 5. CIRCUIT TO PREVENT AUTO POWER-DOWN FOR 100ms AFTER FORCED POWER-UP Automatic Power-Down (ICL3221E, ICL3223E, ICL3243E Only) Even greater power savings is available by using the devices which feature an automatic power-down function. When no valid RS-232 voltages (see Figure 6) are sensed on any receiver input for 30µs, the charge pump and transmitters power-down, thereby reducing supply current to 1µA. Invalid receiver levels occur whenever the driving peripheral’s outputs are shut off (powered down) or when the RS-232 interface cable is disconnected. The ICL32xxE powers back up whenever it detects a valid RS-232 voltage level on any receiver input. This automatic power-down feature provides additional system power savings without changes to the existing operating system. 2.7V VALID RS-232 LEVEL - ICL32xxE IS ACTIVE INDETERMINATE - POWER-DOWN MAY OR MAY NOT OCCUR 0.3V INVALID LEVEL - POWER-DOWN OCCURS AFTER 30µs -0.3V INDETERMINATE - POWER-DOWN MAY OR MAY NOT OCCUR FIGURE 3. DISABLED RECEIVERS PREVENT POWER DRAIN FORCEOFF PWR MGT LOGIC FORCEON INVALID ICL3221E, ICL3223E, ICL3243E I/O UART CPU FIGURE 4. CONNECTIONS FOR MANUAL POWER-DOWN WHEN NO VALID RECEIVER SIGNALS ARE PRESENT -2.7V VALID RS-232 LEVEL - ICL32xxE IS ACTIVE With any of the control schemes, the time required to exit power-down, and resume transmission is only 100µs. A mouse, or other application, may need more time to wake up from shutdown. If automatic power-down is being utilized, the RS-232 device will reenter power-down if valid receiver levels aren’t reestablished within 30µs of the ICL32xxE powering up. Figure 5 illustrates a circuit that keeps the ICL32xxE from initiating automatic power-down for 100ms after powering up. This gives the slow-to-wake peripheral circuit time to reestablish valid RS-232 output levels. FIGURE 6. DEFINITION OF VALID RS-232 RECEIVER LEVELS Automatic power-down operates when the FORCEON input is low, and the FORCEOFF input is high. Tying FORCEON high disables automatic power-down, but manual power-down is always available via the overriding FORCEOFF input. Table 2 summarizes the automatic power-down functionality. 17 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Devices with the automatic power-down feature include an INVALID output signal, which switches low to indicate that invalid levels have persisted on all of the receiver inputs for more than 30µs (see Figure 7). INVALID switches high 1µs after detecting a valid RS-232 level on a receiver input. INVALID operates in all modes (forced or automatic power-down, or forced on), so it is also useful for systems employing manual power-down circuitry. When automatic power-down is utilized, INVALID = 0 indicates that the ICL32xxE is in power-down mode. The time to recover from automatic power-down mode is typically 100µs. RECEIVER INPUTS TRANSMITTER OUTPUTS VCC 0 V+ VCC 0 VINVALID } REGION larger nominal value. The capacitor’s equivalent series resistance (ESR) usually rises at low temperatures and it influences the amount of ripple on V+ and V-. TABLE 3. REQUIRED CAPACITOR VALUES VCC (V) 3.0 to 3.6 4.5 to 5.5 3.0 to 5.5 C1 (µF) 0.1 0.047 0.1 C2, C3, C4 (µF) 0.1 0.33 0.47 Power Supply Decoupling In most circumstances a 0.1µF bypass capacitor is adequate. In applications that are particularly sensitive to power supply noise, decouple VCC to ground with a capacitor of the same value as the charge-pump capacitor C1. Connect the bypass capacitor as close as possible to the IC. INVALID OUTPUT tINVL AUTOPWDN tINVH PWR UP Operation Down to 2.7V ICL32xxE transmitter outputs meet RS-562 levels (±3.7V), at full data rate, with VCC as low as 2.7V. RS-562 levels typically ensure interoperability with RS-232 devices. Transmitter Outputs when Exiting Power-Down Figure 8 shows the response of two transmitter outputs when exiting power-down mode. As they activate, the two transmitter outputs properly go to opposite RS-232 levels, with no glitching, ringing, nor undesirable transients. Each transmitter is loaded with 3kΩ in parallel with 2500pF. Note that the transmitters enable only when the magnitude of the supplies exceed approximately 3V.. 5V/DIV FORCEOFF T1 FIGURE 7. AUTOMATIC POWER-DOWN AND INVALID TIMING DIAGRAMS Receiver ENABLE Control (ICL3221E, ICL3222E, ICL3223E, ICL3241E Only) Several devices also feature an EN input to control the receiver outputs. Driving EN high disables all the inverting (standard) receiver outputs placing them in a high impedance state. This is useful to eliminate supply current, due to a receiver output forward biasing the protection diode, when driving the input of a powered down (VCC = GND) peripheral (see Figure 2). The enable input has no effect on transmitter nor monitor (ROUTB) outputs. 2V/DIV Capacitor Selection The charge pumps require 0.1µF capacitors for 3.3V operation. For other supply voltages refer to Table 3 for capacitor values. Do not use values smaller than those listed in Table 3. Increasing the capacitor values (by a factor of 2) reduces ripple on the transmitter outputs and slightly reduces power consumption. C2, C3, and C4 can be increased without increasing C1’s value, however, do not increase C1 without also increasing C2, C3, and C4 to maintain the proper ratios (C1 to the other capacitors). When using minimum required capacitor values, make sure that capacitor values do not degrade excessively with temperature. If in doubt, use capacitors with a 18 T2 VCC = +3.3V C1 - C4 = 0.1µF TIME (20µs/DIV) FIGURE 8. TRANSMITTER OUTPUTS WHEN EXITING POWER-DOWN Mouse Driveability The ICL3241E and ICL3243E have been specifically designed to power a serial mouse while operating from low voltage supplies. Figure 9 shows the transmitter FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E output voltages under increasing load current. The on-chip switching regulator ensures the transmitters will supply at least ±5V during worst case conditions (15mA for paralleled V+ transmitters, 7.3mA for single Vtransmitter). The Automatic Power-Down feature does not work with a mouse, so FORCEOFF and FORCEON should be connected to VCC. 6 TRANSMITTER OUTPUT VOLTAGE (V) 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 0 1 2 3 4 5 6 7 8 9 10 VCC VCC = 3.0V T1 VOUT+ T2 ICL3241E, ICL3243E T3 VOUT VOUT 5V/DIV T1IN VOUT+ R1OUT VCC = +3.3V C1 - C4 = 0.1µF 5µs/DIV 5V/DIV T1IN T1OUT FIGURE 11. LOOPBACK TEST AT 120kbps LOAD CURRENT PER TRANSMITTER (mA) FIGURE 9. TRANSMITTER OUTPUT VOLTAGE vs LOAD CURRENT (PER TRANSMITTER, i.e., DOUBLE CURRENT AXIS FOR TOTAL VOUT+ CURRENT) T1OUT High Data Rates The ICL32xxE maintain the RS-232 ±5V minimum transmitter output voltages even at high data rates. Figure 10 details a transmitter loopback test circuit, and Figure 11 illustrates the loopback test result at 120kbps. For this test, all transmitters were simultaneously driving RS-232 loads in parallel with 1000pF, at 120kbps. Figure 12 shows the loopback results for a single transmitter driving 1000pF and an RS-232 load at 250kbps. The static transmitters were also loaded with an RS-232 receiver. VCC 0.1µF + R1OUT VCC = +3.3V C1 - C4 = 0.1µF 2µs/DIV FIGURE 12. LOOPBACK TEST AT 250kbps Interconnection with 3V and 5V Logic The ICL32XX directly interface with 5V CMOS and TTL logic families. Nevertheless, with the ICL32XX at 3.3V, and the logic supply at 5V, AC, HC, and CD4000 outputs can drive ICL32XX inputs, but ICL32XX outputs do not reach the minimum VIH for these logic families. See Table 4 for more information. TABLE 4. LOGIC FAMILY COMPATIBILITY WITH VARIOUS SUPPLY VOLTAGES SYSTEM POWER-SUPPLY VOLTAGE (V) 3.3 5 VCC SUPPLY VOLTAGE (V) 3.3 5 + C1 C1+ C1- VCC ICL32xxE V+ + C3 + C2 C2+ C2TIN ROUT EN TOUT V- C4 + RIN 5K 1000pF COMPATIBILITY Compatible with all CMOS families. Compatible with all TTL and CMOS logic families. VCC SHDN OR FORCEOFF FIGURE 10. TRANSMITTER LOOPBACK TEST CIRCUIT 19 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E TABLE 4. LOGIC FAMILY COMPATIBILITY WITH VARIOUS SUPPLY VOLTAGES (Continued) SYSTEM POWER-SUPPLY VOLTAGE (V) 5 VCC SUPPLY VOLTAGE (V) 3.3 IEC61000-4-2 Testing The IEC61000 test method applies to finished equipment, rather than to an individual IC. Therefore, the pins most likely to suffer an ESD event are those that are exposed to the outside world (the RS-232 pins in this case), and the IC is tested in its typical application configuration (power applied) rather than testing each pin-to-pin combination. The lower current limiting resistor coupled with the larger charge storage capacitor yields a test that is much more severe than the HBM test. The extra ESD protection built into this device’s RS-232 pins allows the design of equipment meeting level 4 criteria without the need for additional board level protection on the RS-232 port. AIR-GAP DISCHARGE TEST METHOD For this test method, a charged probe tip moves toward the IC pin until the voltage arcs to it. The current waveform delivered to the IC pin depends on approach speed, humidity, temperature, etc., so it is difficult to obtain repeatable results. The “E” device RS-232 pins withstand ±15kV air-gap discharges. CONTACT DISCHARGE TEST METHOD During the contact discharge test, the probe contacts the tested pin before the probe tip is energized, thereby eliminating the variables associated with the air-gap discharge. The result is a more repeatable and predictable test, but equipment limits prevent testing devices at voltages higher than ±8kV. All “E” family devices survive ±8kV contact discharges on the RS-232 pins. COMPATIBILITY Compatible with ACT and HCT CMOS, and with TTL. ICL32XX outputs are incompatible with AC, HC, and CD4000 CMOS inputs. ±15kV ESD Protection All pins on ICL32XX devices include ESD protection structures, but the ICL32xxE family incorporates advanced structures which allow the RS-232 pins (transmitter outputs and receiver inputs) to survive ESD events up to ±15kV. The RS-232 pins are particularly vulnerable to ESD damage because they typically connect to an exposed port on the exterior of the finished product. Simply touching the port pins, or connecting a cable, can cause an ESD event that might destroy unprotected ICs. These new ESD structures protect the device whether or not it is powered up, protect without allowing any latch-up mechanism to activate, and don’t interfere with RS-232 signals as large as ±25V. Human Body Model (HBM) Testing As the name implies, this test method emulates the ESD event delivered to an IC during human handling. The tester delivers the charge through a 1.5kΩ current limiting resistor, making the test less severe than the IEC61000 test which utilizes a 330Ω limiting resistor. The HBM method determines an IC’s ability to withstand the ESD transients typically present during handling and manufacturing. Due to the random nature of these events, each pin is tested with respect to all other pins. The RS-232 pins on “E” family devices can withstand HBM ESD events to ±15kV. Typical Performance Curves 6 TRANSMITTER OUTPUT VOLTAGE (V) 4 2 0 -2 -4 -6 VOUT VOUT+ VCC = 3.3V, TA = +25°C. 25 20 1 TRANSMITTER AT 250kbps 1 OR 2 TRANSMITTERS AT 30kbps SLEW RATE (V/µs) 15 -SLEW +SLEW 10 0 1000 2000 3000 4000 5000 5 0 1000 LOAD CAPACITANCE (pF) 2000 3000 LOAD CAPACITANCE (pF) 4000 5000 FIGURE 13. TRANSMITTER OUTPUT VOLTAGE vs LOAD CAPACITANCE FIGURE 14. SLEW RATE vs LOAD CAPACITANCE 20 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Typical Performance Curves 45 40 SUPPLY CURRENT (mA) 35 30 25 20 15 10 5 0 0 1000 2000 3000 4000 20kbps 120kbps ICL3221E VCC = 3.3V, TA = +25°C. (Continued) 45 40 ICL3222E, ICL3223E, ICL3232E 250kbps 250kbps SUPPLY CURRENT (mA) 35 30 25 20 15 10 5 120kbps 20kbps 5000 0 0 1000 2000 3000 4000 5000 LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF) FIGURE 15. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA FIGURE 16. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA 45 ICL324XE 40 250kbps SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 35 30 120kbps 25 20 20kbps 15 10 0 1000 2000 3000 4000 5000 LOAD CAPACITANCE (pF) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 ICL324XE 0 2.5 3.0 3.5 4.0 4.5 NO LOAD ALL OUTPUTS STATIC ICL3221E, ICL3222E, ICL3223E, ICL3232E ICL324XE 5.0 5.5 6.0 SUPPLY VOLTAGE (V) FIGURE 17. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA FIGURE 18. SUPPLY CURRENT vs SUPPLY VOLTAGE Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: ICL3221E: 286 ICL3222E: 338 ICL3223E: 357 ICL3232E: 296 ICL324XE: 464 PROCESS: Si Gate CMOS 21 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 2/22/10 REVISION FN4910.21 Revision history begins with this revision. Converted to new Intersil template. Added new temp grade (F = extended industrial) to ICL3232. Updated ordering info table, Operating Conditions, and added 125°C specs for input lkg currents, and rcvr output high voltage. Pages 8-10: Removed all withdrawn devices from Ordering Information table. Pages 12-14: Added "Boldface limits apply over the operating temperature range." to common conditions of Electrical Specs table. Replaced Note 6 "Parts are 100% tested at +25°C. Full temp limits are guaranteed by bench and tester characterization." with "Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested." CHANGE Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php 22 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Dual-In-Line Plastic Packages (PDIP) N INDEX AREA E1 12 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 -CA2 L A1 A C L E E18.3 (JEDEC MS-001-BC ISSUE D) 18 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B B1 C D D1 E E1 e eA eB L N eA eC C A BS C MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 21.47 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 22.35 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 2 11/03 MIN 0.015 0.115 0.014 0.045 0.008 0.845 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.880 0.325 0.280 e eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3 may have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 0.100 BSC 0.300 BSC 0.115 18 0.430 0.150 - 2.54 BSC 7.62 BSC 10.92 3.81 18 2.93 23 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Small Outline Plastic Packages (SOIC) N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45° 0.25(0.010) M BM M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 1.35 0.10 0.33 0.19 9.80 3.80 5.80 0.25 0.40 16 8° 0° 8° MAX 1.75 0.25 0.51 0.25 10.00 4.00 6.20 0.50 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05 MIN 0.0532 0.0040 0.013 0.0075 0.3859 0.1497 0.2284 0.0099 0.016 16 0° MAX 0.0688 0.0098 0.020 0.0098 0.3937 0.1574 0.2440 0.0196 0.050 A1 B C D E e H C α A1 0.10(0.004) 0.050 BSC 1.27 BSC e B 0.25(0.010) M C AM BS h L N NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 24 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM M16.173 16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D E1 A2 c 0.10(0.004) C AM BS MILLIMETERS MIN 0.05 0.85 0.19 0.09 4.90 4.30 6.25 0.50 16 8o 0o 8o MAX 1.10 0.15 0.95 0.30 0.20 5.10 4.50 6.50 0.70 NOTES 9 3 4 6 7 Rev. 1 2/02 MIN 0.002 0.033 0.0075 0.0035 0.193 0.169 0.246 0.020 16 0o MAX 0.043 0.006 0.037 0.012 0.008 0.201 0.177 0.256 0.028 e b 0.10(0.004) M α A1 e E L N 0.026 BSC 0.65 BSC NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) α 25 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Small Outline Plastic Packages (SSOP) N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA 0.25 0.010 L GAUGE PLANE 0.25(0.010) M BM M16.209 (JEDEC MO-150-AC ISSUE B) 16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B C D E A2 C 0.10(0.004) C AM BS MILLIMETERS MIN 0.05 1.65 0.22 0.09 5.90 5.00 7.40 0.55 16 8° 0° 8° Rev. 3 MAX 2.00 1.85 0.38 0.25 6.50 5.60 8.20 0.95 NOTES 9 3 4 6 7 6/05 MIN 0.002 0.065 0.009 0.004 0.233 0.197 0.292 0.022 16 0° MAX 0.078 0.072 0.014 0.009 0.255 0.220 0.322 0.037 α A1 e B 0.25(0.010) M e H L N 0.026 BSC 0.65 BSC NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimension at maximum material condition. 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 26 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Small Outline Plastic Packages (SOIC) N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45° 0.25(0.010) M BM M16.3 (JEDEC MS-013-AA ISSUE C) 16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 2.35 0.10 0.33 0.23 10.10 7.40 10.00 0.25 0.40 16 8° 0° 8° MAX 2.65 0.30 0.51 0.32 10.50 7.60 10.65 0.75 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05 MIN 0.0926 0.0040 0.013 0.0091 0.3977 0.2914 0.394 0.010 0.016 16 0° MAX 0.1043 0.0118 0.0200 0.0125 0.4133 0.2992 0.419 0.029 0.050 A1 B C D E e H C α A1 0.10(0.004) 0.050 BSC 1.27 BSC e B 0.25(0.010) M C AM BS h L N NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 27 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Small Outline Plastic Packages (SOIC) N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45° 0.25(0.010) M BM M18.3 (JEDEC MS-013-AB ISSUE C) 18 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 2.35 0.10 0.33 0.23 11.35 7.40 10.00 0.25 0.40 18 8° 0° 8° MAX 2.65 0.30 0.51 0.32 11.75 7.60 10.65 0.75 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05 MIN 0.0926 0.0040 0.013 0.0091 0.4469 0.2914 0.394 0.010 0.016 18 0° MAX 0.1043 0.0118 0.0200 0.0125 0.4625 0.2992 0.419 0.029 0.050 A1 B C D E e H C α A1 0.10(0.004) 0.050 BSC 1.27 BSC e B 0.25(0.010) M C AM BS h L N NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 28 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM M20.173 20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.252 0.169 0.246 0.0177 20 0o 8o 0o MAX 0.047 0.006 0.051 0.0118 0.0079 0.260 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 6.40 4.30 6.25 0.45 20 8o MAX 1.20 0.15 1.05 0.30 0.20 6.60 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 1 6/98 e b 0.10(0.004) M C AM BS α A1 0.10(0.004) A2 c E1 e E L N 0.026 BSC 0.65 BSC NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) α 29 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Shrink Small Outline Plastic Packages (SSOP) N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM M20.209 (JEDEC MO-150-AE ISSUE B) 20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B C D E A2 C 0.10(0.004) C AM BS MILLIMETERS MIN 1.73 0.05 1.68 0.25 0.09 7.07 5.20’ 7.65 0.63 20 0 deg. MAX 1.99 0.21 1.78 0.38 0.20’ 7.33 5.38 7.90’ 0.95 8 deg. Rev. 3 11/02 6 7 3 4 9 NOTES MIN 0.068 0.002 0.066 0.010’ 0.004 0.278 0.205 0.301 0.025 20 0 deg. MAX 0.078 0.008’ 0.070’ 0.015 0.008 0.289 0.212 0.311 0.037 8 deg. e B 0.25(0.010) M α A1 e H L N 0.026 BSC 0.65 BSC α NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimension at maximum material condition. 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 30 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM M28.173 28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.378 0.169 0.246 0.0177 28 0o 8o 0o MAX 0.047 0.006 0.051 0.0118 0.0079 0.386 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 9.60 4.30 6.25 0.45 28 8o MAX 1.20 0.15 1.05 0.30 0.20 9.80 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 0 6/98 e b 0.10(0.004) M C AM BS α A1 0.10(0.004) A2 c E1 e E L N 0.026 BSC 0.65 BSC NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AE, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) α 31 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Shrink Small Outline Plastic Packages (SSOP) N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA 0.25 0.010 L GAUGE PLANE 0.25(0.010) M BM M28.209 (JEDEC MO-150-AH ISSUE B) 28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B C D E A2 C 0.10(0.004) C AM BS MILLIMETERS MIN 0.05 1.65 0.22 0.09 9.90 5.00 7.40 0.55 28 8° 0° 8° MAX 2.00 1.85 0.38 0.25 10.50 5.60 8.20 0.95 NOTES 9 3 4 6 7 Rev. 2 6/05 MIN 0.002 0.065 0.009 0.004 0.390 0.197 0.292 0.022 28 0° MAX 0.078 0.072 0.014 0.009 0.413 0.220 0.322 0.037 α A1 e B 0.25(0.010) M e H L N 0.026 BSC 0.65 BSC NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimension at maximum material condition. 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 32 FN4910.21 February 22, 2010 ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E Small Outline Plastic Packages (SOIC) N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45o 0.25(0.010) M BM M28.3 (JEDEC MS-013-AE ISSUE C) 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 L MILLIMETERS MIN 2.35 0.10 0.33 0.23 17.70 7.40 10.00 0.25 0.40 28 0o MAX 2.65 0.30 0.51 0.32 18.10 7.60 10.65 0.75 1.27 8o NOTES 9 3 4 5 6 7 Rev. 0 12/93 MIN 0.0926 0.0040 0.013 0.0091 0.6969 0.2914 0.394 0.01 0.016 28 0o MAX 0.1043 0.0118 0.0200 0.0125 0.7125 0.2992 0.419 0.029 0.050 8o B C D E e H C α A1 0.10(0.004) 0.05 BSC 1.27 BSC e B 0.25(0.010) M C AM BS h L N NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 33 FN4910.21 February 22, 2010