ICL7126

® ICL7126 Data Sheet October 25, 2004 FN3084.5 3 1/2 Digit, Low Power, Single Chip A/D Converter The ICL7126 is a high performance, very low power 31/2-digit, A/D converter. All the necessary active devices are contained on a single CMOS IC, including seven segment decoders, display drivers, reference, and clock. The ICL7126 is designed to interface with a liquid crystal display (LCD) and includes a backplane drive. The supply current of 100µA is ideally suited for 9V battery operation. The ICL7126 brings together an unprecedented combination of high accuracy, versatility, and true economy. It features auto-zero to less than 10µV, zero drift of less than 1µV/oC, input bias current of 10pA maximum, and rollover error of less than one count. The versatility of true differential input and reference is useful in all systems, but gives the designer an uncommon advantage when measuring load cells, strain gauges and other bridge-type transducers. And finally the true economy of single power operation allows a high performance panel meter or multi-meter to be built with the addition of only 10 passive components and a display. The ICL7126 can be used as a plug-in replacement for the ICL7106 in a wide variety of applications, changing only the passive components. Features • 8,000 Hours Typical 9V Battery Life • Guaranteed Zero Reading for 0V Input on All Scales • True Polarity at Zero for Precise Null Detection • 1pA Typical Input Current • True Differential Input and Reference • Direct LCD Display Drive - No External Components Required • Pin Compatible With the ICL7106 • Low Noise - Less Than 15µVP-P • On-Chip Clock and Reference • Low Power Dissipation Guaranteed Less Than 1mW • No Additional Active Circuits Required • Pb-Free Available (RoHS Compliant) Pinout ICL7126 (PDIP) TOP VIEW V+ D1 C1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 OSC 1 39 OSC 2 38 OSC 3 37 TEST 36 REF HI 35 REF LO 34 CREF+ 33 CREF32 COMMON 31 IN HI 30 IN LO 29 A-Z 28 BUFF 27 INT 26 V25 G2 (10s) 24 C3 23 A3 22 G3 21 BP/GND (100s) Ordering Information TEMP. RANGE PART NUMBER (°C) ICL7126CPL ICL7126CPLZ (Note 1) NOTES: 1. Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. 2. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. (10s) PACKAGE 40 Ld PDIP PKG. DWG. # E40.6 B1 (1s) A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3 (100s) B3 F3 E3 (1000) AB4 POL (MINUS) 0 to 70 0 to 70 40 Ld PDIP E40.6 (Pb-free) (Note 2) 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003, 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ICL7126 Absolute Maximum Ratings Supply Voltage V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V Analog Input Voltage (Either Input) (Note 1) . . . . . . . . . . . . .V+ to VReference Input Voltage (Either Input) . . . . . . . . . . . . . . . . .V+ to VClock Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEST to V+ Thermal Information Thermal Resistance (Typical, Note 2) θJA (oC/W) PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC NOTE: Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER SYSTEM PERFORMANCE Zero Input Reading Ratiometric Reading Rollover Error TA = 25oC, VREF = 100mV, fCLOCK = 48kHz (Notes 1, 3) TEST CONDITIONS MIN TYP MAX UNITS VIN = 0.0V, Full Scale = 200mV VlN = VREF , VREF = 100mV -VIN = +VlN ≅ 200mV Difference in Reading for Equal Positive and Negative Inputs Near Full Scale Full Scale = 200mV or Full Scale = 2V Maximum Deviation from Best Straight Line Fit (Note 5) VCM = ±1V, VIN = 0V, Full Scale = 200mV (Note 5) VIN = 0V, Full Scale = 200mV (Peak-To-Peak Value Not Exceeded 95% of Time) (Note 5) VlN = 0V (Note 5) VlN = 0V, 0oC To 70oC (Note 5) VIN = 199mV, 0oC To 70oC, (Ext. Ref. 0ppm/×oC) (Note 5) VIN = 0V (Does Not Include COMMON Current) 25kΩ Between Common and Positive Supply (With Respect to + Supply) 25kΩ Between Common and Positive Supply (With Respect to + Supply) (Note 5) V+ = to V- = 9V (Note 4) vs Clock Frequency -000.0 999 - ±000.0 999/100 0 ±0.2 +000.0 1000 ±1 Digital Reading Digital Reading Counts Linearity Common Mode Rejection Ratio Noise Leakage Current Input Zero Reading Drift Scale Factor Temperature Coefficient V+ Supply Current COMMON Pin Analog Common Voltage Temperature Coefficient of Analog Common Peak-To-Peak Segment Drive Voltage Peak-To-Peak Backplane Drive Voltage Power Dissipation Capacitance 2.4 4 - ±0.2 50 15 1 0.2 1 70 3.0 80 5.5 40 ±1 10 1 5 100 3.2 6 - Counts µV/V µV pA µV/oC ppm/oC µA V ppm/oC V pF NOTES: 3. Unless otherwise noted, specifications are tested using the circuit of Figure 1. 4. Back plane drive is in phase with segment drive for ‘off’ segment, 180 degrees out of phase for ‘on’ segment. Frequency is 20 times conversion rate. Average DC component is less than 50mV. 5. Not tested, guaranteed by design. 2 FN3084.5 ICL7126 Typical Application Schematics C3 R1 R5 240kΩ 1MΩ C5 R3 180kΩ R4 10kΩ C1 0.1µF 0.01 C2 R2 0.22µF 0.047µF 180kΩ C4 50pF 750Ω OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 REF LO 35 CREF+ 34 CREF- 33 COM 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V- 26 G2 25 C3 24 A3 23 G3 22 ICL7126 20 POL 19 AB4 G1 D1 C1 B1 A1 D2 10 C2 11 B2 12 A2 15 D3 16 B3 V+ E1 14 E2 18 E3 F1 13 F2 17 F3 1 2 3 4 5 6 7 8 9 DISPLAY FIGURE 1. ICL7126 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE SET REF = 100.0mV R1 R5 240kΩ 1MΩ C5 R3 180kΩ 0.33µF 180kΩ C1 0.1µF 0.15µF C4 50pF 0.01 R4 10kΩ C2 R2 OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 REF LO 35 CREF+ 34 CREF- 33 COM 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V- 26 G2 25 C3 24 A3 23 G3 22 ICL7126 20 POL 19 AB4 G1 D1 C1 B1 A1 D2 10 C2 11 B2 12 A2 15 D3 16 B3 V+ E1 14 E2 18 E3 F1 13 F2 17 F3 1 2 3 4 5 6 7 8 9 DISPLAY FIGURE 2. ICL7126 CLOCK FREQUENCY 16kHz, 1 READING/S 3 BP 21 - + + IN - 9V C3 BP 21 + + IN - 9V DISPLAY C1 = 0.1µF C2 = 0.22µF C3 = 0.047µF C4 = 50pF C5 = 0.01µF R1 = 240kΩ R2 = 180kΩ R3 = 180kΩ R4 = 10kΩ R5 = 1MΩ DISPLAY C1 = 0.1µF C2 = 0.33µF C3 = 0.5µF C4 = 50pF C5 = 0.01µF R1 = 240kΩ R2 = 180kΩ R3 = 180kΩ R4 = 10kΩ R5 = 1M Ω FN3084.5 ICL7126 Typical Application Schematics (Continued) + IN R1 240kΩ R5 1MΩ C5 R3 180kΩ 0.22µF C1 0.1µF 0.047µF 180kΩ C4 50pF 0.01 R4 10kΩ C2 R2 C3 750Ω OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 REF LO 35 CREF+ 34 CREF- 33 COM 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V- 26 G2 25 C3 24 A3 23 G3 22 ICL7126 20 POL 19 AB4 G1 D1 C1 B1 A1 D2 10 C2 11 B2 12 A2 15 D3 16 B3 V+ E1 14 E2 18 E3 F1 13 F2 17 F3 1 2 3 4 5 6 7 8 9 DISPLAY FIGURE 3. CLOCK FREQUENCY 48kHz, 3 READINGS/S 4 BP 21 DISPLAY + - 9V C1 = 0.1µF C2 = 0.22µF C3 = 0.047µF C4 = 50pF C5 = 0.01µF R1 = 240kΩ R2 = 180kΩ R3 = 180kΩ R4 = 10kΩ R5 = 1M Ω FN3084.5 ICL7126 Design Information Summary Sheet • OSCILLATOR FREQUENCY fOSC = 0.45/RC COSC > 50pF; ROSC > 50kΩ fOSC (Typ) = 48kHz • OSCILLATOR PERIOD tOSC = RC/0.45 • INTEGRATION CLOCK FREQUENCY fCLOCK = fOSC /4 • INTEGRATION PERIOD tINT = 1000 x (4/fOSC) • 60/50Hz REJECTION CRITERION tINT /t60Hz or tlNT /t50Hz = Integer • OPTIMUM INTEGRATION CURRENT IINT = 4µA • FULL-SCALE ANALOG INPUT VOLTAGE VlNFS (Typ) = 200mV or 2V • INTEGRATE RESISTOR V INFS R INT = ---------------I INT • DISPLAY COUNT V IN COUNT = 1000 × -------------V REF • CONVERSION CYCLE tCYC = tCL0CK x 4000 tCYC = tOSC x 16,000 when fOSC = 48KHz; tCYC = 333ms • COMMON MODE INPUT VOLTAGE (V- + 1V) < VlN < (V+ - 0.5V) • AUTO-ZERO CAPACITOR 0.01µF < CAZ < 1µF • REFERENCE CAPACITOR 0.1µF < CREF < 1µF • VCOM Biased between V+ and V• VCOM ≅ V+ - 2.8V Regulation lost when V+ to V- < ≅6.8V; If VCOM is externally pulled down to (V + to V -)/2, the VCOM circuit will turn off • ICL7126 POWER SUPPLY: SINGLE 9V V+ - V- = 9V Digital supply is generated internally VTEST ≅ V+ - 4.5V • ICL7126 DISPLAY: LCD Type: Direct drive with digital logic supply amplitude • INTEGRATE CAPACITOR ( t INT ) ( I INT ) C INT = ------------------------------V INT • INTEGRATOR OUTPUT VOLTAGE SWING ( t INT ) ( I INT ) V INT = ------------------------------C INT • VINT MAXIMUM SWING: (V- + 0.5V) < VINT < (V+ - 0.5V), VINT (Typ) = 2V Typical Integrator Amplifier Output Waveform (INT Pin) AUTO ZERO PHASE (COUNTS) 2999 - 1000 SIGNAL INTEGRATE PHASE FIXED 1000 COUNTS DE-INTEGRATE PHASE 0 - 1999 COUNTS TOTAL CONVERSION TIME = 4000 x tCLOCK = 16,000 x tOSC 5 FN3084.5 ICL7126 Detailed Description Analog Section Figure 4 shows the Functional Diagram of the Analog Section for the ICL7126. Each measurement cycle is divided into three phases. They are (1) auto-zero (A-Z), (2) signal integrate (INT) and (3) de-integrate (DE). De-integrate Phase The final phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator to output to return to zero. The time required for the output to return to zero is proportional to the input signal. Specifically, the digital reading displayed is:  VIN  Display Count = 1000  --------------  .  VREF  Auto-Zero Phase During auto-zero three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor CAZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited only by the noise of the system. In any case, the offset referred to the input is less than 10µV. Differential Input The input can accept differential voltages anywhere within the common mode range of the input amplifier, or specifically from 0.5V below the positive supply to 1V above the negative supply. In this range, the system has a CMRR of 86dB typical. However, care must be exercised to assure the integrator output does not saturate. A worst case condition would be a large positive common mode voltage with a near full-scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. For these critical applications the integrator output swing can be reduced to less than the recommended 2V full scale swing with little loss of accuracy. The integrator output can swing to within 0.5V of either supply without loss of linearity. Signal Integrate Phase During signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide common mode range: up to 1V from either supply. If, on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to analog COMMON to establish the correct common mode voltage. At the end of this phase, the polarity of the integrated signal is determined. CREF RINT CREF+ V+ 34 REF HI 36 A-Z 1 µA 31 IN HI INT DEDE+ INPUT HIGH 6.2V A-Z REF LO 35 A-Z CREF33 BUFFER V+ 28 1 29 INTEGRATOR + CAZ A-Z CINT INT 27 + - - + 2.8V TO DIGITAL SECTION A-Z N 32 COMMON A-Z AND DE(±) 30 IN LO INT 26 VINPUT LOW DE+ DE+ COMPARATOR - FIGURE 4. ANALOG SECTION OF ICL7126 6 FN3084.5 ICL7126 V+ V+ V+ REF HI REF LO 6.8V ZENER IZ V+ 27kΩ 200kΩ ICL7126 ICL7126 REF HI REF LO COMMON VICL8069 1.2V REFERENCE FIGURE 5A. FIGURE 5. FIGURE 5B. Differential Reference The reference voltage can be generated anywhere within the power supply voltage of the converter. The main source of common mode error is a roll-over voltage caused by the reference capacitor losing or gaining charge to stray capacity on its nodes. If there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called up to de-integrate a positive signal but lose charge (decrease voltage) when called up to de-integrate a negative input signal. This difference in reference for positive or negative input voltage will give a roll-over error. However, by selecting the reference capacitor large enough in comparison to the stray capacitance, this error can be held to less than 0.5 count worst case. (See Component Value Selection.) COMMON, a common mode voltage exists in the system and is taken care of by the excellent CMRR of the converter. However, in some applications IN LO will be set at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied to the same point, thus removing the common mode voltage from the converter. The same holds true for the reference voltage. If reference can be conveniently tied to analog COMMON, it should be since this removes the common mode voltage from the reference system. Within the lC, analog COMMON is tied to an N channel FET that can sink approximately 3mA of current to hold the voltage 2.8V below the positive supply (when a load is trying to pull the common line positive). However, there is only 1µA of source current, so COMMON may easily be tied to a more negative voltage thus overriding the internal reference. Analog COMMON This pin is included primarily to set the common mode voltage for battery operation or for any system where the input signals are floating with respect to the power supply. The COMMON pin sets a voltage that is approximately 2.8V more negative than the positive supply. This is selected to give a minimum end-of-life battery voltage of about 6.8V. However, analog COMMON has some of the attributes of a reference voltage. When the total supply voltage is large enough to cause the zener to regulate (