IRF520

IRF520 Data Sheet November 1999 File Number 1574.4 9.2A, 100V, 0.270 Ohm, N-Channel Power MOSFET This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA09594. Features • 9.2A, 100V • rDS(ON) = 0.270Ω • SOA is Power Dissipation Limited • Single Pulse Avalanche Energy Rated • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Ordering Information PART NUMBER IRF520 PACKAGE TO-220AB BRAND IRF520 Symbol D NOTE: When ordering, use the entire part number. G S Packaging JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) 4-172 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 IRF520 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified IRF520 Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Dissipation Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 100 100 9.2 6.5 37 ±20 60 0.4 36 -55 to 175 300 260 UNITS V V A A A V W W/oC mJ oC oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS ID(ON) IGSS rDS(ON) gfs td(ON) tr td(OFF) tf Qg(TOT) Qgs Qgd CISS COSS CRSS LD Measured From the Contact Screw On Tab To Center of Die Measured From the Drain Lead, 6mm (0.25in) From Package to Center of Die Modified MOSFET Symbol Showing the Internal Devices Inductances D LD G LS S TEST CONDITIONS ID = 250µA, VGS = 0V (Figure 10) VGS = VDS, ID = 250µA VDS = 95V, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 150oC VDS > ID(ON) x rDS(ON)MAX, VGS = 10V (Figure 7) VGS = ±20V ID = 5.6A, VGS = 10V (Figure 8, 9) VDS ≥ 50V, ID = 5.6A (Figure 12) VDD = 50V, ID ≈ 9.2A, RG = 18Ω, RL = 5.5Ω MOSFET Switching Times are Essentially Independent of Operating Temperature VGS = 10V, ID = 9.2A, VDS = 0.8 x Rated BVDSS, Ig(REF) = 1.5mA (Figure 14) Gate Charge is Essentially Independent of Operating Temperature VDS = 25V, VGS = 0V, f = 1MHz (Figure 11) MIN 100 2.0 9.2 2.7 - TYP 0.25 4.1 9 30 18 20 10 2.5 2.5 350 130 25 3.5 MAX 4.0 250 1000 ±100 0.27 13 63 70 59 30 - UNITS V V µA µA A nA Ω S ns ns ns ns nC nC nC pF pF pF nH Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero Gate Voltage Drain Current On-State Drain Current (Note 2) Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge Gate to Drain “Miller” Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Internal Drain Inductance - 4.5 - nH Internal Source Inductance LS Measured From the Source Lead, 6mm (0.25in) From Header to Source Bonding Pad - 7.5 - nH Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient RθJC RθJA Free Air Operation - - 2.5 80 oC/W oC/W 4-173 IRF520 Source to Drain Diode Specifications PARAMETER Continuous Source to Drain Current Pulse Source to Drain Current (Note 3) SYMBOL ISD ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode G D MIN - TYP - MAX 9.2 37 UNITS A A S Source to Drain Diode Voltage (Note 2) Reverse Recovery Time Reverse Recovered Charge NOTES: VSD trr QRR TJ = 25oC, ISD = 9.2A, VGS = 0V (Figure 13) TJ = 25oC, ISD = 9.2A, dISD/dt = 100A/µs TJ = 25oC, ISD = 9.2A, dISD/dt = 100A/µs 5.5 0.17 100 0.5 2.5 240 1.1 V ns µC 2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 25V, starting TJ = 25oC, L = 640mH, RG = 25Ω, peak IAS = 9.2A. Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 Unless Otherwise Specified 10 ID, DRAIN CURRENT (A) 8 6 4 2 125 50 75 100 TC , CASE TEMPERATURE (oC) 150 175 0 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 10 ZθJC, TRANSIENT THERMAL IMPEDANCE (oC/W) 1 0.5 0.2 0.1 PDM t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC + TC 10-4 10-2 10-3 0.1 t1, RECTANGULAR PULSE DURATION (s) 1 10 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 10-5 FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE 4-174 IRF520 Typical Performance Curves 100 10µs ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 100µs Unless Otherwise Specified (Continued) 15 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 7V 9 VGS = 6V 6 10V VGS = 8V 12 10 1ms OPERATION IN THIS AREA IS LIMITED BY rDS(ON) TC = 25oC TJ = MAX RATED SINGLE PULSE 1 10 100 VDS , DRAIN TO SOURCE VOLTAGE (V) 1000 10ms 1 3 VGS = 5V VGS = 4V 0 30 10 40 20 VDS, DRAIN TO SOURCE VOLTAGE (V) 50 0.1 0 FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS 15 VGS = 10V VGS = 8V VGS = 7V ID, DRAIN CURRENT (A) 12 ID(ON), ON-STATE DRAIN CURRENT (A) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 102 VDS ≥ 50V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 10 9 6 VGS = 6V 1 175oC 25oC 3 VGS = 5V 0 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) VGS = 4V 5 0.1 0 2 4 6 8 10 VGS , GATE TO SOURCE VOLTAGE (V) FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS rDS(ON), DRAIN TO SOURCE ON RESISTANCE 2.5 2.0 NORMALIZED ON RESISTANCE PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 3.0 2.4 ID = 9.2A, VGS = 10V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 1.5 VGS = 10V 1.8 1.0 1.2 0.5 VGS = 20V 0 0 8 16 24 ID, DRAIN CURRENT (A) 32 40 0.6 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 TJ, JUNCTION TEMPERATURE (oC) FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 4-175 IRF520 Typical Performance Curves 1.25 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250µA Unless Otherwise Specified (Continued) 1000 1.05 C, CAPACITANCE (pF) 1.15 800 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 600 0.95 400 CISS COSS CRSS 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 102 0.85 200 0.75 -60 0 60 120 180 0 TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 5 ISD, SOURCE TO DRAIN CURRENT (A) gfs, TRANSCONDUCTANCE (S) 100 TJ = 25oC PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 4 10 3 TJ = 175oC 2 1 TJ = 175oC TJ = 25oC 1 0 0 3 VDS ≥ 50 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 6 9 ID, DRAIN CURRENT (A) 12 15 0.1 0 0.4 0.8 1.2 1.6 2.0 VSD, SOURCE TO DRAIN VOLTAGE (V) FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 20 VGS, GATE TO SOURCE VOLTAGE (V) ID = 9.2A 16 VDS = 20V VDS = 50V VDS = 80V 12 8 4 0 0 3 6 9 12 15 Qg, GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 4-176 IRF520 Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + 0V IAS 0.01Ω 0 tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON td(ON) tr RL VDS + tOFF td(OFF) tf 90% 90% RG DUT - VDD 0 10% 90% 10% VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS CURRENT REGULATOR VDS (ISOLATED SUPPLY) VDD SAME TYPE AS DUT Qg(TOT) Qgd Qgs D VDS VGS 12V BATTERY 0.2µF 50kΩ 0.3µF G DUT 0 Ig(REF) 0 IG CURRENT SAMPLING RESISTOR S VDS ID CURRENT SAMPLING RESISTOR IG(REF) 0 FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS 4-177 IRF520 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 4-178