IS-1845ASRH

IS-1845ASRH ESIGNS NEW D ART D FOR ME N D E MENT P RECOM ED REPLACE Data Sheet N OT MEND XARH RECOM ISL7884 September 25, 2008 FN9001.4 Single Event Radiation Hardened High Speed, Current Mode PWM The IS-1845ASRH is designed to be used in switching power supplies operating in current-mode. The rising edge of the on-chip oscillator turns on the output. Turn-off is controlled by the current sense comparator and occurs when the sensed current reaches a peak controlled by the error amplifier. TM Features • Electrically Screened to DSCC SMD # 5962-01509 • QML Qualified per MIL-PRF-38535 Requirements • Radiation Environment - Total Dose. . . . . . . . . . . . . . . . . . . . . 300 krad(SI) (Max) - SEL Immune. . . . . . . . . . . . . . . . . Dielectrically Isolated - SEU Immune . . . . . . . . . . . . . . . . . . . . 35MeV/mg/cm2 - SEU Cross-Section at 89MeV/mg/cm2 . . . . 5 x 10-6cm2 • Low Start-up Current . . . . . . . . . . . . . . . . . . . 100µA (Typ) • Fast Propagation Delay . . . . . . . . . . . . . . . . . . 80ns (Typ) • Supply Voltage Range . . . . . . . . . . . . . . . . . . . 12V to 20V • High Output Drive. . . . . . . . . . . . . . . . . . . . 1A (Peak, Typ) • Undervoltage Lockout . . 8.8V Start (Typ), 8.2V Stop (Typ) Constructed with Intersil’s Rad Hard Silicon Gate (RSG) dielectrically isolated BiCMOS process, these devices are immune to single event latch-up and have been specifically designed to provide a high level of immunity to single event transients. All specified parameters are guaranteed and tested for 300krad(Si) total dose performance. Detailed Electrical Specifications for these devices are contained in SMD 5962-01509. A “hot-link” is provided on our website for downloading the SMD. Applications • Current-Mode Switching Power Supplies • Control of High Current FET Drivers • Motor Speed and Direction Control Pinouts IS7-1845ASRH (8 LD CDIP2-T8 SBDIP) TOP VIEW COMP VFB ISENSE RTCT 1 2 3 4 8 7 6 5 VREF VCC OUT GND NC COMP VFB NC NC NC ISENSE RTCT NC IS9-1845ASRH (18 LD FLATPACK) TOP VIEW 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 NC VREF VCC VC OUT NC GND OSCGND NC NOTES: 1. Grounding the Comp pin does not inhibit the output. The output may be inhibited by applying >1.2V to the ISENSE pin. 2. This part should be operated with Ct = 3.3nF and Rt = 10k timing components only. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003, 2008. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. IS-1845ASRH Ordering Information ORDERING NUMBER 5962F0150901V9A IS0-1845ASRH/Sample 5962F0150901VPC 5962F0150901VPC 5962F0150901QPC 5962F0150901QPC 5962F0150901VXC 5962F0150901VXC 5962F0150901QXC IS7-1845ASRH/Proto IS9-1845ASRH/Proto INTERNAL MKT. NUMBER IS0-1845ASRH-Q IS0-1845ASRH/Sample IS7-1845ASRH-Q IS7-1845ASRH-QS9000 IS7-1845ASRH-8 IS7-1845ASRH-8S9000 IS9-1845ASRH-Q IS9-1845ASRH-QS9000 IS9-1845ASRH-8 IS7-1845ASRH/Proto IS9-1845ASRH/Proto TEMP. RANGE (°C) -50 to +125 -50 to +125 -50 to +125 -50 to +125 -50 to +125 -50 to +125 -50 to +125 -50 to +125 -50 to +125 -50 to +125 -50 to +125 8 Ld SBDIP 8 Ld SBDIP 8 Ld SBDIP 8 Ld SBDIP 18 Ld Flatpack 18 Ld Flatpack 18 Ld Flatpack 8 Ld SBDIP 18 Ld Flatpack D8.3 D8.3 D8.3 D8.3 K18.B K18.B K18.B D8.3 K18.3 PACKAGE PKG. DWG. # Typical Performance Curves 10k C470pF C1000pF C2200pF C4700pF 100 DMAX (%) 60 40 20 0 100 DMAX 80 FREQUENCY (Hz) 1k 10 1 1 10 Rt TIMING RESISTANCE (kΩ) 100 0.1 1 10 Rt TIMING RESISTANCE (kΩ) 100 FIGURE 1. OSCILLATOR FREQUENCY vs Rt and Ct FIGURE 2. MAXIMUM DUTY CYCLE vs Rt 2 FN9001.4 September 25, 2008 IS-1845ASRH Die Characteristics DIE DIMENSIONS 3090µm x 4080µm (121.6 mils x 159.0 mils) Thickness: 483µm ± 25.4µm (19 mils ± 1 mil) INTERFACE MATERIALS Glassivation Type: Phosphorus Silicon Glass (PSG) Thickness: 8.0kA ± 1.0kA Top Metallization Type: AlSiCu Thickness: 16.0kA ± 2kA Substrate Radiation Hardened Silicon Gate, Dielectric Isolation Backside Finish Silicon ASSEMBLY RELATED INFORMATION Substrate Potential Unbiased (DI) ADDITIONAL INFORMATION Worst Case Current Density