IS80C286-12

80C286/883 March 1997 High Performance Microprocessor with Memory Management and Protection Description The Intersil 80C286/883 is a static CMOS version of the NMOS 80286 microprocessor. The 80C286/883 is an advanced, high-performance microprocessor with specially optimized capabilities for multiple user and multi-tasking systems. The 80C286/883 has built-in memory protection that supports operating system and task isolation as well as program and data privacy within tasks. The 80C286/883 includes memory management capabilities that map 230 (one gigabyte) of virtual address space per task into 224 bytes (16 megabytes) of physical memory. The 80C286/883 is upwardly compatible with 80C86 and 80C88 software (the 80C286/883 instruction set is a superset of the 80C86/80C88 instruction set). Using the 80C286/ 883 real address mode, the 80C286/883 is object code compatible with existing 80C86 and 80C88 software. In protected virtual address mode, the 80C286/883 is source code compatible with 80C86 and 80C88 software but may require upgrading to use virtual address as supported by the 80C286/883’s integrated memory management and protection mechanism. Both modes operate at full 80C286/883 performance and execute a superset of the 80C86 and 80C88 instructions. The 80C286/883 provides special operations to support the efficient implementation and execution of operating systems. For example, one instruction can end execution of one task, save its state, switch to a new task, load its state, and start execution of the new task. The segment-not-present exception and restartable instructions. Features • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. • Compatible with NMOS 80286/883 • Static CMOS Design for Low Power Operation - ICCSB = 5mA Maximum - ICCOP = 185mA Maximum (80C286-10/883) - ICCOP = 220mA Maximum (80C286-12/883) • Large Address Space - 16 Megabytes Physical - 1 Gigabyte Virtual per Task • Integrated Memory Management, Four-Level Memory Protection and Support for Virtual Memory and Operating Systems • Two 80C86 Upward Compatible Operating Modes - 80C286/883 Real Address Mode - Protected Virtual Address Mode • Compatible with 80287 Numeric Data Co-Processor Ordering Information PACKAGE 68 Pin PGA TEMP. RANGE 0oC to +70oC -40oC to +85oC 10MHz IG80C286-10 12.5MHz CG80C286-12 IG80C286-12 16MHz CG80C286-16 20MHz CG80C286-20 25MHz PKG. NO. G68.B G68.B G68.B G68.B -55oC to +125oC MG80C286-10/883 MG80C286-12/883 5962-9067801MXC 5962-9067802MXC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 File Number 2948.1 3-128 80C286/883 Pinout 68 LEAD PGA, COMPONENT PAD VIEW As viewed from underside of the component when mounted on the board. D10 D11 D12 D13 D14 49 50 D7 D0 D1 D2 D3 D4 D5 35 A0 A2 VCC A3 A5 A7 A9 A11 A13 D0 A1 CLK RESET A4 A6 A8 A10 A12 34 32 30 28 26 24 22 20 18 36 33 31 29 27 25 23 21 19 17 A12 37 38 39 40 41 42 43 44 45 46 47 48 D6 51 53 55 57 59 61 63 65 67 52 54 56 58 60 62 64 66 68 ERROR NC INTR NMI PEREQ READY HLDA M/ IO NC NC BUSY NC NC VSS VCC HOLD COD/ INTA LOCK 16 15 A15 14 13 A17 12 11 A19 10 9 A21 8 7 A22 6 5 PEACK 4 3 S1 NC ERROR 2 1 D15 VSS D8 D9 PIN 1 INDICATOR P.C. BOARD VIEW As viewed from the component side of the P.C. board. D15 D14 D13 D12 D11 D10 VSS 35 36 33 31 29 27 25 23 21 4 3 S1 6 5 PEACK 8 7 A22 10 9 A21 12 11 A19 14 13 A17 16 15 A15 19 17 A12 34 32 30 28 26 24 22 20 18 D0 A1 CLK RESET A4 A6 A8 A10 A12 A0 A2 VCC A3 A5 A7 A9 A11 A13 A14 D0 D9 D2 39 40 A18 D8 A16 D1 37 38 ERROR D7 D6 D5 BHE D4 43 44 VSS A14 A16 A18 A20 A23 VSS NC S0 51 NC BUSY NC NC VSS VCC HOLD COD/ INTA LOCK ERROR NC INTR NMI PEREQ READY HLDA M/ IO NC 52 54 56 58 60 62 64 66 68 53 55 57 59 61 63 65 67 2 1 NC 49 50 47 48 45 46 PIN 1 INDICATOR NC BHE S0 3-129 A23 A20 D3 41 42 80C286/883 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage Applied. . . . . . GND -1.0V to VCC +1.0V Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Information Thermal Resistance (Typical) θJA θJC PGA Package . . . . . . . . . . . . . . . . . . . . . 35oC/W 6oC/W Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22,500 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC System Clock (CLK) RISE Time (From 1.0V to 3.6V . . . . 8ns (Max) System Clock (CLK) FALL Time (from 3.6V to 1.0V) . . . . 8ns (Max) Input RISE and FALL Time (From 0.8V to 2.0V 80C286-10/883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns (Max) 80C286-12/883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8ns (Max) TABLE 1. 80C286/883 D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 LIMITS TEMPERATURE -55oC ≤ TA ≤ +125oC -55 C ≤ TA ≤ +125 C o o PARAMETER Input LOW Voltage Input HIGH Voltage CLK Input LOW Voltage CLK Input HIGH Voltage Output LOW Voltage Output HIGH Voltage SYMBOL VIL VIH VILC VIHC VOL VOH CONDITIONS VCC = 4.5V VCC = 5.5V VCC = 4.5V VCC = 5.5V IOL = 2.0mA, VCC = 4.5V IOH = -2.0mA, VCC = 4.5V IOH = -100µA, VCC = 4.5V MIN -0.5 2.0 -0.5 3.6 3.0 VCC -0.4 MAX 0.8 VCC +0.5 1.0 VCC +0.5 0.4 10 UNITS V V V V V V V µA -55oC o ≤ TA ≤ ≤ TA ≤ +125oC o -55 C ≤ TA ≤ +125 C -55oC o +125oC o -55 C ≤ TA ≤ +125 C -55 C ≤ TA ≤ +125 C o o Input Leakage Current II VIN = GND or VCC, VCC = 5.5V, Pins 29, 31, 57, 59, 61, 63-64 VCC = 4.5V and 5.5V, VIN = 1.0V, Note 1 VCC = 4.5V and 5.5V, VIN = 3.0V, Note 2 VCC = 4.5V and 5.5V VIN = GND, Note 5 VO = GND or VCC VCC = 5.5V, Pins 1, 7-8, 10-28, 32-34 80C286-10/883, Note 4 80C286-12/883, Note 4 1, 2, 3 -10 Input Sustaining Current LOW Input Sustaining Current HIGH Input Sustaining Current on BUSY and ERROR Pins Output Leakage Current IBHL IBHH ISH 1, 2, 3 1, 2, 3 1, 2, 3 -55oC ≤ TA ≤ +125oC -55oC ≤ TA ≤ +125oC -55oC ≤ TA ≤ +125oC 38 -50 -30 200 -400 -500 µA µA µA IO 1, 2, 3 -55oC ≤ TA ≤ +125oC -10 10 µA Active Power Supply Current Standby Power Supply Current NOTES: ICCOP 1, 2, 3 -55oC ≤ TA ≤ +125oC -55oC ≤ TA ≤ +125oC - 185 220 5 mA mA mA ICCSB VCC = 5.5V, Note 3 1, 2, 3 - 2. IBHL should be measured after lowering VIN to GND and then raising to 1.0V on the following pins: 36-51, 66, 67. 3. IBHH should be measured after raising VIN to VCC and then lowering to 3.0V on the following pins: 4-6, 36-51, 66-68. 4. ICCSB should be tested with the clock stopped in phase two of the processor clock cycle. VIN = VCC or GND, VCC = 5.5V, outputs unloaded. 5. ICCOP measured at 10MHz for the 80C286-10/883 and 12.5MHz for the 80C286-12/883. VIN = 2.4V or 0.4V, VCC = 5.5V, outputs unloaded. 6. ISH should be measured after raising VIN to VCC and then lowering to 0V on pins 53 and 54. 3-130 80C286/883 TABLE 2. 80C286/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS AC Timings are Referenced to 0.8V and 2.0V Points of the Signals as Illustrated in Datasheet Waveforms, Unless Otherwise Noted. Device Guaranteed and 100% Tested. 80C286/883 10MHz PARAMETER System Clock (CLK) Period System Clock (CLK) Low Time System Clock (CLK) High Time Asynchronous Inputs SETUP Time (Note 1) Asynchronous Inputs HOLD Time (Note 1) RESET SETUP Time SYMBOL 1 CONDITIONS VCC = 4.5V and 5.5V GROUP A SUBGROUPS 9, 10, 11 TEMPERATURE -55oC ≤ TA ≤ +125oC -55oC ≤TA ≤ +125oC -55oC ≤ TA ≤ +125oC -55oC ≤ TA ≤ +125oC MIN 50 MAX 12.5MHz MIN 40 MAX UNITS ns 2 VCC = 4.5V and 5.5V at 1.0V VCC = 4.5V and 5.5V at 3.6V VCC = 4.5V and 5.5V 9, 10, 11 12 - 11 - ns 3 9, 10, 11 16 - 13 - ns 4 9, 10, 11 20 - 15 - ns 5 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 20 - 15 - ns 6 VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V, CL = 100pF IL = | 2mA| VCC = 4.5V and 5.5V, CL = 100pF IL = | 2mA| VCC = 4.5V and 5.5V, CL = 100pF IL = | 2mA| VCC = 4.5V and 5.5V, CL = 100pF IL = | 2mA| 9, 10, 11 -55oC ≤ TA ≤ +125oC -55oC ≤ TA ≤ +125oC -55oC ≤ TA ≤ +125oC -55oC ≤ TA ≤ +125oC -55oC ≤ TA ≤ +125oC -55oC ≤TA ≤ +125oC -55oC ≤ TA ≤ +125oC 19 - 10 - ns RESET HOLD Time 7 9, 10, 11 0 - 0 - ns Read Data SETUP Time Read Data HOLD Time READY SETUP Time 8 9, 10, 11 8 - 5 - ns 9 9, 10, 11 4 - 4 - ns 10 9, 10, 11 26 - 20 - ns READY HOLD Time 11 9, 10, 11 25 - 20 - ns Status/PEACK Active Delay, (Note 4) 12A 9, 10, 11 1 22 1 21 ns Status/PEACK Inactive Delay (Note 3) Address Valid Delay (Note 2) 12B 9, 10, 11 -55oC ≤ TA ≤ +125oC 1 30 1 24 ns 13 9, 10, 11 -55oC ≤ TA ≤ +125oC 1 35 1 32 ns Write Data Valid Delay, (Note 2) 14 9, 10, 11 -55oC ≤ TA ≤ +125oC 0 40 0 31 ns 3-131 80C286/883 TABLE 2. 80C286/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) AC Timings are Referenced to 0.8V and 2.0V Points of the Signals as Illustrated in Datasheet Waveforms, Unless Otherwise Noted. Device Guaranteed and 100% Tested. 80C286/883 10MHz PARAMETER HLDA Valid Delay (Note 5) SYMBOL 15 CONDITIONS VCC = 4.5V and 5.5V, CL = 100pF IL = |2mA| GROUP A SUBGROUPS 9, 10, 11 TEMPERATURE -55oC ≤ TA ≤ +125oC MIN 0 MAX 47 12.5MHz MIN 0 MAX 25 UNITS ns NOTES: 1. Asynchronous inputs are INTR, NMI, HOLD, PEREQ, ERROR, and BUSY. This specification is given only for testing purposes, to assure recognition at a specific CLK edge. 2. Delay from 1.0V on the CLK to 0.8V or 2.0V. 3. Delay from 1.0V on the CLK to 0.8V for Min (HOLD time) and to 2.0V for Max (inactive delay). 4. Delay from 1.0V on the CLK to 2.0V for Min (HOLD time) and to 0.8V for Max (active delay). 5. Delay from 1.0V on the CLK to 2.0V. TABLE 3. 80C286/883 ELECTRICAL PERFORMANCE SPECIFICATIONS 80C286/883 10MHz PARAMETER CLK Input Capacitance Other Input Capacitance I/O Capacitance Address/Status/Data Float Delay Address Valid to Status SETUP Time NOTES: 1. Output Load: CL = 100pF. 2. Delay measured from address either reaching 0.8V or 2.0V (valid) to status going active reaching 0.8V or status going inactive reaching 2.0V. 3. Delay from 1.0V on the CLK to Float (no current drive) condition. 4. I L = -6mA (VOH to Float), IL = 8mA (VOL to Float). 5. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Group C & D METHOD 100%/5004 100%/5004 100% 100% Samples/5005 SUBGROUPS 1, 7, 9 1 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9 SYMBOL CCLK CIN CI/O 15 19 IL = | 2.0mA| CONDITIONS FREQ = 1MHz FREQ = 1MH FREQ = 1MH NOTES 5 5 5 1, 3, 4, 5 1, 2, 5 TEMPERATURE TA = TA = TA = -55oC +25oC +25oC +25oC +125oC MIN 0 27 MAX 10 10 10 47 12.5MHz MIN 0 20 MAX 10 10 10 32 UNITS pF pF pF ns ns ≤ TA ≤ -55oC ≤ TA ≤ +125oC 3-132 80C286/883 AC Electrical Specifications 82C284 and 82C288 Timing Specifications Are Given For Reference Only, And No Guarantee is Implied. 82C284 Timing 10MHz SYMBOL PARAMETER MIN MAX 12.5MHz MIN MAX UNIT TEST CONDITION TIMING REQUIREMENTS 11 12 13 14 SRDY/SRDYEN Setup Time SRDY/SRDYEN Hold Time ARDY/ARDYEN Setup Time ARDY/ARDYEN Hold Time 15 2 5 30 15 2 5 25 ns ns ns ns (Note 1) (Note 1) TIMING RESPONSES 19 PCLK Delay 0 20 0 16 ns CL = 75pF, IOL = 5mA, IOH = -1mA NOTE: 1. These times are given for testing purposes to ensure a predetermined action. 82C288 Timing 10MHz SYMBOL PARAMETER MIN MAX 12.5MHz MIN MAX UNIT TEST CONDITION TIMING REQUIREMENTS 12 13 CMDLY Setup Time CMDLY Hold Time 15 1 15 1 ns ns TIMING RESPONSES 16 17 19 20 21 22 23 24 29 30 ALE Active Delay ALE Inactive Delay DT/R Read Active Delay DEN Read Active Delay DEN Read Inactive Delay DT/R Read Inactive Delay DEN Write Active Delay DEN Write Inactive Delay Command Active Delay from CLK Command Inactive Delay from CLK 1 0 3 5 3 3 3 16 19 23 21 23 24 23 23 21 20 1 0 3 5 3 3 3 16 19 23 21 21 18 23 23 21 20 ns ns ns ns ns ns ns ns ns ns CL = 300pF IOL = 32mA Max CL = 150pF IOL = 16mA Max IOH = -1mA Max 3-133 80C286/883 AC Specifications 4.0V 3.6V 3.6V CLK INPUT 1.0V 0.45V 1.0V 4.0V 3.6V CLK INPUT 1.0V 0.45V 1.0V 3.6V tSETUP tHOLD 2.4V 2.0V OTHER DEVICE INPUT 0.8V 0.4V tDELAY (MAX) tDELAY (MIN) 2.0V DEVICE OUTPUT 0.8V 0.8V 2.0V NOTE: 1. For AC testing, input rise and fall times are driven at 1ns per volt. FIGURE 1. AC DRIVE AND MEASURE POINTS - CLK INPUT 3-134 80C286/883 Waveforms READ CYCLE ILLUSTRATED WITH ZERO WAIT STATES TS TC φ2 1 φ2 φ1 φ2 WRITE CYCLE ILLUSTRATED WITH ONE WAIT STATE TS TC φ1 φ2 φ1 φ2 φ1 READ (TI OR TS) TC φ2 φ1 BUS CYCLE TYPE VOH CLK 2 VOL S1 • S0 TI 3 12A 12B 19 13 80C286/883 A23 - A0 M/IO, COD INTA BHE, LOCK VALID ADDRESS 13 VALID CONTROL 9 13 19 VALID ADDRESS 13 VALID CONTROL VALID IF TS 14 8 D15 - D0 VALID READ DATA 11 10 READY 12 11 82C284 (SEE NOTE 2) SRDY + SRDYEN 19 13 ARDY + ARDYEN 19 PCLK 16 ALF 12 13 CMDLY 82C288 (SEE NOTE 2) 29 MWTC 29 MRDC 19 DT/R 22 20 DEN 21 23 30 (SEE NOTE 1) 30 13 12 12 13 17 19 20 14 10 VALID WRITE DATA 11 15 24 NOTES: 1. The modified timing is due to the CMDLY signal being active. 2. 82C254 and 82C288 Timing Waveforms are shown for reference only, and no guarantee is inplied. FIGURE 2. MAJOR CYCLE TIMING 3-135 80C286/883 Waveforms (Continued) BUS CYCLE TYPE VCH CLK VCL PCLK (SEE NOTE 1) 5 INTR, NMI HOLD, PEREQ (SEE NOTE 2) 4 ERROR, BUSY (SEE NOTE 2) 4 CLK 5 RESET 19 19 RESET φ1 TX φ2 CLK VCH φ2 φ1 TX φ1 φ2 VCL 7 6 (SEE NOTE 1) VCH φ1 TX φ2 φ2 VCL 7 6 (SEE NOTE 1) NOTES: 1. PCLK indicates which processor cycle phase will occur on the next CLK. PCLK may not indicate the correct phase until the first cycle is performed. 2. These inputs are asynchronous. The setup and hold times shown assure recognition for testing purposes. FIGURE 3. 80C286/883 ASYNCHRONOUS INPUT SIGNAL TIMING BUS CYCLE TYPE VCH CLK VCL HILDA 16 (SEE NOTE 4) 12A (NOTE 3) 12B PEACK IF NPX TRANSFER BHE, LOCK A23 - A0, M/IO, COD/INTA 13 (SEE NOTE 5) VALID 14 D15 - D0 (SEE NOTE 6) (SEE NOTE 2) 15 (SEE NOTE 1) 15 IF TS 15 16 φ1 TH φ2 TH OR TI φ1 NOTE: 1. When RESET meets the setup time shown, the next CLK will start or repeat φ1 of a processor cycle. FIGURE 4. 80C286/883 RESET INPUT TIMING AND SUBSEQUENT PROCESSOR CYCLE PHASE TI TH φ2 φ1 φ2 φ1 φ2 S1 • S0 80C286/883 15 (SEE NOTE 3) VALID IF WRITE 80C284 PCLK NOTES: 1. 2. 3. 4. 5. 6. These signals may not be driven by the 80C286/883 during the time shown. The worst case in terms of latest float time is shown. The data bus will be driven as shown if the last cycle before TI in the diagram was a write TC. The 80C286/883 puts its status pins in a high impedance logic one state during TH. For HOLD request set up to HLDA, refer to Figure 8. BHE and LOCK are driven at this time but will not become valid until TS. The data bus will remain in a high impedance state if a read cycle is performed. FIGURE 5. EXITING AND ENTERING HOLD 3-136 80C286/883 Waveforms BUS CYCLE TYPE VCH CLK VCL S1 • S0 CLK A23 -A0 M/IO, COD INTA PEACK I/0 READ IF PROC. EXT. TO MEMORY MEMORY READ IF MEMORY TO PROC. EXT MEMORY WRITE IF PROC. EXT. TO MEMORY I/O WRITE IF MEMORY TO PROC. EXT. TI φ2 φ1 TS φ2 1 TC φ2 φ1 TS φ2 φ1 TC φ2 φ1 TI (Continued) MEMORY ADDRESS IF PROC. EXT. TO MEMORY TRANSFER I/O PORT ADDRESS 00FA(H) IF MEMORY TO PROC. EXT. TRANSFER I/O PORT ADDRESS 00FA(H) IF PROC. EXT. TO MEMORY TRANSFER MEMORY ADDRESS IF MEMORY TO PROC. EXT. TRANSFER 5 12A 12B (SEE NOTE 1) (SEE NOTE 2) 4 PEREQ NOTES: 1. PEACK always goes active during the first bus operation of a processor extension data operand transfer sequence. The first bus operation will be either a memory read at operand address or I/O read at port address 00FA(H). 2. To prevent a second processor extension data operand transfer, the worst case maximum time (shown above) is 3 x 1 - 12AMAX -(4)MIN The actual, configuration dependent, maximum time is: 3 x 1 - 12AMAX - (4)MIN +N x 2 x (1). N is the number of extra TC states added to either the first or second bus operation of the processor extension data operand transfer sequence. FIGURE 6. 80C286/883 PEREQ/PEACK TIMING FOR ONE TRANSFER ONLY BUS CYCLE TYPE VCH CLK VCL RESET S1 • S0 PEACK A23 - A0 BHE φ2 φ1 TX φ2 φ1 TX φ2 φ1 TX φ2 φ1 TI φ2 6 6 (SEE NOTE 1) AT LEAST 16 CLK PERIODS UNKNOWN (SEE NOTE 2) 7 12B 13 UNKNOWN 13 M/IO COD/INTA LOCK UNKNOWN 13 UNKNOWN 15 (SEE NOTE 3) DATA 16 HILDA UNKNOWN NOTES: 1. Setup time for RESET ↑ may be violated with the consideration that φ1 of the processor clock may begin one system CLK period later. 2. Setup and hold times for RESET ↓ must be met for proper operation, but RESET ↓ may occur during φ1 or φ2. 3. The data bus is only guaranteed to be in a high impedance state at the time shown. FIGURE 7. INITIAL 80C286/883 PIN STATE DURING RESET 3-137 80C286/883 Waveforms (Continued) BUS HOLD ACKNOWLEDGE TH φ1 CLK (SEE NOTE 5) HOLD HLDA (SEE NOTE 1) 80C286 S1 • S0 A23 - A0 M/IO, COD/INTA BHE, LOCK (SEE NOTE 2) VALID (SEE NOTE 3) VALID (SEE NOTE 1) (SEE NOTE 4) (SEE NOTE 6) φ2 φ1 TH φ2 φ1 TH φ2 φ1 TS φ2 φ1 TC φ2 φ1 WRITE CYCLE TC φ2 φ1 TC φ2 φ1 TI φ2 φ1 BUS HOLD ACKNOWLEDGE TH φ2 BUS CYCLE TYPE D15 - D0 SRDY + SRDYEN VALID 80C284 NOT READY NOT READY ARDY + ARDYEN NOT READY NOT READY CMDLY DELAY ENABLE MWTC (SEE NOTE 7) READY (SEE NOTE 7) 80C288 VOH DT/R DEN ALE TS - STATUS CYCLE CT - COMMAND CYCLE NOTES: 1. Status lines are held at a high impedance logic one by the 80C286 during a HOLD state. 2. Address, M/IO and COD/lNTA may start floating during any TC depending on when internal 80C286 bus arbiter decides to release bus to external HOLD. The float starts in φ2 of TC. 3. BHE and LOCK may start floating after the end of any TC depending on when internal 80C286 bus arbiter decides to release bus to external HOLD. The float starts in φ1 of TC. 4. The minimum HOLD to HLDA time is shown. Maximum is one TH longer. 5. The earliest HOLD time is shown. It will always allow a subsequent memory cycle if pending is shown. 6. The minimum HOLD to HLDA time is shown. Maximum is a function of the instruction, type of bus cycle and other machine state (i.e., Interrupts, Waits, Lock, etc.). 7. Asynchronous ready allows termination of the cycle. Synchronous ready does not signal ready in this example. Synchronous ready state is ignored after ready is signaled via the asynchronous input. FIGURE 8. MULTIBUS WRITE TERMINATED BY ASYNCHRONOUS READY WITH BUS HOLD 3-138 80C286/883 Burn-In Circuit RO RO RO RO RO RO RO RO RO RO RO RO RO F0 RC RI F7 RO 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 35 34 18 17 RI 36 16 RI 37 15 RI RI 38 14 RI 39 13 RI 40 12 RI 41 80C286/883 PGA 11 RI 43 42 RI 9 10 44 RI 8 45 RI 7 46 RI 47 6 RI 5 48 RI 4 49 RI 50 3 RI 2 52 51 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 F5 F4 F3 VSS 68 1 RI RI RI RI RI RI RI RI GND C1 VDD RO RO RO RO RO NOTES: 8. Supply Voltage: VDD = 5.5V, VSS = 0.0V. 9. Input Voltage Limits: VIL (Maximum) = 0.8V, VIH (Minimum) = 2.0V 10. Component Values: RC = 1kΩ ±5%, RI = 10kΩ ±5%, RO = Two Series 2.7kΩ ±5% 11. Capacitor Values: C1 = 0.1 Microfarads 12. Oven Type and Frequency Requirements: Wakefield Oven Board f0 = 100kHz, f3 = 12.5kHz, f4 = 6.25kHz, f5 = 3.125kHz, f7 = 781.25Hz. 13. Special Requirements: (a) ELECTROSTATIC DISCHARGE SENSITIVE. Proper Precautions Must be Used When Handling Units. (b) All Power Supplies Must be at Zero Volts When the Boards are Inserted into the Ovens. (c) When Powering Up, the Inputs Must be Held Below the VDD Voltage. (d) If an Excessive Current is Indicated at Final Inspection, Check to See if a Part is Inserted Backwards or is Latched Up. 3-139 RO 5.5V VDD RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO VSS 80C286/883 Die Characteristics DIE DIMENSIONS: 286 x 283 x 19 ±1mils METALLIZATION: Type: Si-Al Thickness: 8kÅ GLASSIVATION: Type: Nitrox Thickness: 10kÅ WORST CASE CURRENT DENSITY: 2 X 105A/cm2 LEAD TEMPERATURE: (10s Soldering): ≤ 300oC 80C286/883 Metallization Mask Layout All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Spec Number 3-140