ISL12022

® ISL12022 Real Time Clock with On Chip ±5ppm Temp Compensation Data Sheet June 23, 2009 FN6659.2 Low Power RTC with Battery-Backed SRAM and Embedded Temp Compensation ±5ppm with Auto Daylight Saving The ISL12022 device is a low power real time clock with an embedded Temp sensor for oscillator compensation, clock/calendar, power fail, low battery monitor, brownout indicator, single periodic or polled alarms, intelligent battery-backup switching, Battery Reseal™ function and 128 bytes of battery-backed user SRAM. The oscillator uses an external, low-cost 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes, and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction. Daylight Savings time adjustment is done automatically, using parameters entered by the user. Power fail and battery monitors offer user-selectable trip levels. A time stamp function records the time and date of switchover from VDD to VBAT power, and also from VBAT to VDD power. Features • Real Time Clock/Calendar - Tracks Time in Hours, Minutes and Seconds - Day of the Week, Day, Month and Year • On-chip Oscillator Compensation Over the Operating Temp Range - ±5ppm Over -40°C to +85°C • 10-bit Digital Temperature Sensor Output - ±2°C Accuracy • Customer Programmable Day Light Saving Time • 15 Selectable Frequency Outputs • 1 Alarm - Settable to the Second, Minute, Hour, Day of the Week, Day, or Month - Single Event or Pulse Interrupt Mode • Battery Reseal™ Function to Extend Battery Shelf Life • Automatic Backup to Battery or Super Capacitor - Operation to VBAT = 1.8V - 1.0µA Battery Supply Current • Battery Status Monitor - 2 User Programmable Levels - Seven Selectable Voltages for Each Level Pinout ISL12022 (8 LD SOIC) TOP VIEW X1 X2 VBAT GND 1 2 3 4 8 7 6 5 VDD IRQ/FOUT SCL SDA • Power Status Brownout Monitor - Six Selectable Trip Levels, from 2.295V to 4.675V • Oscillator Failure Detection • Time Stamp for First VDD to VBAT, and Last VBAT to VDD • 128 Bytes Battery-Backed User SRAM • I2C Bus™ - 400kHz Clock Frequency • 8 Ld SOIC Package • Pb-Free (RoHS Compliant) Applications • Utility Meters • POS Equipment • Medical Devices • Security Systems • Vending Machines • White Goods • Printers and Copiers 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. I2C Bus™ is a trademark owned by NXP Semiconductors Netherlands, B.V. Copyright Intersil Americas Inc. 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL12022 Ordering Information PART NUMBER (Note) ISL12022IBZ* PART MARKING 12022 IBZ VDD RANGE (V) 2.7 to 5.5 TEMP RANGE (°C) -40 to +85 PACKAGE (Pb-free) 8 Ld SOIC M8.15 PKG. DWG. # *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Block Diagram SDA SCL SDA BUFFER SCL BUFFER I2C INTERFACE SECONDS CONTROL LOGIC REGISTERS MINUTES HOURS DAY OF WEEK CRYSTAL OSCILLATOR RTC DIVIDER DATE MONTH VDD VTRIP SWITCH VBAT GND INTERNAL SUPPLY TEMPERATURE SENSOR FREQUENCY CONTROL POR FREQUENCY OUT YEAR ALARM CONTROL REGISTERS USER SRAM IRQ/FOUT X1 X2 Pin Descriptions PIN NUMBER 1 2 3 4 5 6 7 8 SYMBOL X1 X2 VBAT GND SDA SCL IRQ/FOUT VDD DESCRIPTION Crystal Input. The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. X1 can also be driven directly from a 32.768kHz source. Crystal Output. The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. X2 should be left open when X1 is driven from external source. Backup Supply. This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the VDD supply fails. This pin should be tied to ground if not used. Ground. Serial Data. SDA is a bi-directional pin used to transfer serial data into and out of the device. It has an open drain output and may be wire OR’ed with other open drain or open collector outputs. Serial Clock. The SCL input is used to clock all serial data into and out of the device. Interrupt Output/Frequency Output. Multi-functional pin that can be used as interrupt or frequency output pin. The function is set via the configuration register. It is an open-drain output. Power Supply. 2 FN6659.2 June 23, 2009 ISL12022 Absolute Maximum Ratings Voltage on VDD, VBAT and IRQ/FOUT pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on SCL and SDA pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V Voltage on X1 and X2 pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V ESD Rating Human Body Model (Per MIL-STD-883 Method 3014) . . . . .>3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>300V Thermal Information Thermal Resistance (Typical, Note 1) θJA (°C/W) 8 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. DC Operating Characteristics - RTC Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise stated. SYMBOL VDD VBAT IDD1 PARAMETER Main Power Supply Battery Supply Voltage Supply Current. (I2C not Active, Temperature Conversion not Active, FOUT not Active) IDD2 Supply Current. (I2C Active, Temperature Conversion not Active, FOUT not Active) Supply Current. (I2C not Active, Temperature Conversion Active, FOUT not Active) Battery Supply Current (Note 11) (Note 11) VDD = 5V VDD = 3V VDD = 5V CONDITIONS MIN (Note 9) 2.7 1.8 4.1 3.5 200 TYP (Note 5) MAX (Note 9) 5.5 5.5 7 6 500 UNITS V V µA µA µA 2 3, 4 3, 4 3, 4 NOTES IDD3 VDD = 5V 120 400 µA 3, 4 IBAT VDD = 0V, VBAT = 3V, TA = +25°C VDD = 0V, VBAT = 3V 1.0 1.0 1.6 5.0 100 µA µA nA µA µA mV mV V mV mV 3 3 IBATLKG ILI ILO VBATM VPBM VTRIP VTRIPHYS VBATHYS ΔFoutT ΔFoutV ΔATLSB Temp Battery Input Leakage Input Leakage Current on SCL I/O Leakage Current on SDA Battery Level Monitor Threshold Brownout Level Monitor Threshold VBAT Mode Threshold VTRIP Hysteresis VBAT Hysteresis Oscillator Stability vs Temperature Oscillator Stability vs Voltage AT Sensitivity per LSB Temperature Sensor Accuracy VDD = 5.5V, VBAT = 1.8V VIL = 0V, VIH = 5.5V VIL = 0V, VIH = 5.5V -1.0 -1.0 -100 -100 (Note 11) 2.0 2.2 30 50 VDD = 3.3V 2.7V ≤ VDD ≤ 5.5V BETA (4:0) = 10000 VDD = VBAT = 3.3V -5 -3 0.5 1 ±2 ±0.1 ±0.1 1.0 1.0 +100 +100 2.4 7 7 10 10 10 7 +5 +3 2 ppm ppm ppm °C IRQ/FOUT (OPEN DRAIN OUTPUT) VOL Output Low Voltage VDD = 5.5V, IOL = 3mA VDD = 2.7V, IOL = 1mA 0.4 0.4 V V 3 FN6659.2 June 23, 2009 ISL12022 Power-Down Timing SYMBOL VDD SRTest Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise stated. PARAMETER VDD Negative Slew rate CONDITIONS MIN (Note 9) TYP (Note 5) MAX (Note 9) 10 UNITS V/ms NOTES 6 I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise specified. SYMBOL VIL VIH Hysteresis VOL CPIN PARAMETER SDA and SCL Input Buffer LOW Voltage SDA and SCL Input Buffer HIGH Voltage SDA and SCL Input Buffer Hysteresis SDA Output Buffer LOW Voltage, Sinking 3mA SDA and SCL Pin Capacitance VDD = 5V, IOL = 3mA TA = +25°C, f = 1MHz, VDD = 5V, VIN = 0V, VOUT = 0V TEST CONDITIONS MIN (Note 9) -0.3 0.7 x VDD 0.05 x VDD 0 0.02 0.4 10 TYP (Note 5) MAX (Note 9) 0.3 x VDD VDD + 0.3 UNITS V V V V pF 7, 8 7, 8 NOTES fSCL tIN tAA SCL Frequency Pulse Width Suppression Time at SDA and SCL Inputs SCL Falling Edge To SDA Output Data Valid Any pulse narrower than the max spec is suppressed. SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of VDD window. 1300 400 50 900 kHz ns ns tBUF Time the Bus Must be Free Before SDA crossing 70% of VDD the Start of a New Transmission during a STOP condition, to SDA crossing 70% of VDD during the following START condition. Clock LOW Time Clock HIGH Time START Condition Setup Time Measured at the 30% of VDD crossing. Measured at the 70% of VDD crossing. SCL rising edge to SDA falling edge. Both crossing 70% of VDD. From SDA falling edge crossing 30% of VDD to SCL falling edge crossing 70% of VDD. From SDA exiting the 30% to 70% of VDD window, to SCL rising edge crossing 30% of VDD. From SCL falling edge crossing 30% of VDD to SDA entering the 30% to 70% of VDD window. From SCL rising edge crossing 70% of VDD, to SDA rising edge crossing 30% of VDD. ns tLOW tHIGH tSU:STA 1300 600 600 ns ns ns tHD:STA START Condition Hold Time 600 ns tSU:DAT Input Data Setup Time 100 ns tHD:DAT Input Data Hold Time 0 900 ns tSU:STO STOP Condition Setup Time 600 ns 4 FN6659.2 June 23, 2009 ISL12022 I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise specified. (Continued) SYMBOL tHD:STO PARAMETER STOP Condition Hold Time TEST CONDITIONS From SDA rising edge to SCL falling edge. Both crossing 70% of VDD. From SCL falling edge crossing 30% of VDD, until SDA enters the 30% to 70% of VDD window. From 30% to 70% of VDD. From 70% to 30% of VDD. Total on-chip and off-chip MIN (Note 9) 600 TYP (Note 5) MAX (Note 9) UNITS ns NOTES tDH Output Data Hold Time 0 ns tR tF Cb RPU SDA and SCL Rise Time SDA and SCL Fall Time Capacitive loading of SDA or SCL 20 + 0.1 x Cb 20 + 0.1 x Cb 10 1 300 300 400 ns ns pF kΩ 8 8 8 8 SDA and SCL Bus Pull-up Resistor Maximum is determined by Off-chip tR and tF. For Cb = 400pF, max is about 2kΩ~2.5kΩ. For Cb = 40pF, max is about 15kΩ~20kΩ NOTES: 2. Temperature Conversion is inactive below VBAT = 2.7V. Device operation is not guaranteed at VBAT VBAT +VBATHYS 5. Specified at +25°C. 6. In order to ensure proper timekeeping, the VDD SR- specification must be followed. 7. Limits should be considered typical and are not production tested. 8. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification. 9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 10. Specifications are typical and require using a recommended crystal (see “Application Section” on page 25). 11. Minimum VDD and/or VBAT of 1V to sustain the SRAM. The value is based on characterization and it is not tested. 5 FN6659.2 June 23, 2009 ISL12022 SDA vs SCL Timing tF tHIGH tLOW tR SCL tSU:STA tHD:STA SDA (INPUT TIMING) tSU:DAT tHD:DAT tSU:STO tAA SDA (OUTPUT TIMING) tDH tBUF Symbol Table WAVEFORM INPUTS Must be steady OUTPUTS Will be steady May change from LOW to HIGH May change from HIGH to LOW Don’t Care: Changes Allowed N/A Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR VDD = 5V 5.0V 1533Ω SDA AND IRQ/FOUT FOR VOL= 0.4V AND IOL = 3mA 100pF FIGURE 1. STANDARD OUTPUT LOAD FOR TESTING THE DEVICE WITH VDD = 5.0V 6 FN6659.2 June 23, 2009 ISL12022 Typical Performance Curves Temperature is +25°C unless otherwise specified. 1050 1000 IBAT (nA) 950 900 850 800 1.8 1600 1400 1200 1000 VBAT = 3.0V 800 VBAT = 1.8V 2.3 2.8 3.3 3.8 4.3 4.8 5.3 600 -40 -20 0 20 40 60 80 VBAT CURRENT (nA) VBAT = 5.5V VBAT VOLTAGE (V) TEMPERATURE (°C) FIGURE 2. IBAT vs VBAT FIGURE 3. IBAT vs TEMPERATURE 6 4.4 4.2 5 VBAT = 5.5V IDD1 (µA) IDD1 (µA) VBAT = 2.7V 3 VDD = 3.3V -20 0 20 40 TEMPERATURE (°C) 60 80 4 4.0 3.8 3.6 3.4 3.2 2 -40 3.0 2.7 3.2 3.7 4.2 VDD (V) 4.7 5.2 FIGURE 4. IDD1 vs TEMPERATURE FIGURE 5. IDD1 vs VDD 6 SUPPLY CURRENT (µA) 5.5 5.0 4.5 4.0 3.5 3.0 2.5 -40 FOUT = 1Hz and 64Hz FOUT = 32kHz 5 IDD (µA) VDD = 5.5V 4 VDD = 3.3V 3 VDD = 2.7V 2 0.01 0.1 1 10 100 1k FREQUENCY OUTPUT (Hz) 10k 100k -20 0 20 40 TEMPERATURE (°C) 60 80 FIGURE 6. FOUT vs IDD FIGURE 7. IDD vs TEMPERATURE, 3 DIFFERENT FOUT 7 FN6659.2 June 23, 2009 ISL12022 Typical Performance Curves Temperature is +25°C unless otherwise specified. (Continued) 110 100 90 IDD (µA) 80 70 60 50 40 -40 -20 0 20 40 60 80 VDD = 3.3V VDD = 5.5V IBAT (µA) VBAT = 2.7V 110 100 90 80 70 60 50 40 30 20 -40 -20 0 20 40 TEMPERATURE (°C) 60 80 VBAT = 3.0V VBAT = 1.8V VBAT = 5.5V TEMPERATURE (°C) FIGURE 8. IDD WITH TSE = 1 vs TEMPERATURE FIGURE 9. IBAT with TSE = 1, BTSE = 1 vs TEMPERATURE General Description The ISL12022 device is a low power real time clock (RTCs) with embedded temperature sensors. It contains crystal frequency compensation circuitry over the operating temperature range, clock/calendar, power fail and low battery monitors, brownout indicator, 1 periodic or polled alarm, intelligent battery-backup switching and 128 Bytes of battery-backed user SRAM. The oscillator uses an external, low cost 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction. In addition, the ISL12022 can be programmed for automatic Daylight Savings Time (DST) adjustment by entering local DST information. The ISL12022’s alarm can be set to any clock/calendar value for a match, for example, every minute, every Tuesday or at 5:23 AM on March 21. The alarm status is available by checking the Status Register, or the device can be configured to provide a hardware interrupt via the IRQ/FOUT pin. There is a repeat mode for the alarm allowing a periodic interrupt every minute, every hour, every day, etc. The device also offers a backup power input pin. This VBAT pin allows the device to be backed up by battery or super capacitor with automatic switchover from VDD to VBAT. The ISL12022 device is specified for VDD = 2.7V to 5.5V and the clock/calendar portion of the device remains fully operational in battery-backup mode down to 1.8V (Standby Mode). The VBAT level is monitored and reported against preselected levels. The first report is registered when the VBAT level falls below 85% of nominal level, the second level is set for 75%. Battery levels are stored in PWR_VBAT registers. The ISL12022 offers a “Brownout” alarm once the VDD falls below a pre-selected trip level. This allows system Micro to save vital information to memory before complete power loss. There are six VDD levels that could be selected for initiation of the Brownout alarm. 8 Pin Descriptions X1, X2 The X1 and X2 pins are the input and output, respectively, of an inverting amplifier. An external 32.768kHz quartz crystal is used with the device to supply a timebase for the real time clock. Internal compensation circuitry with internal temperature sensor provides frequency corrections for selected popular crystals to ±5ppm over the operating temperature range from -40°C to +85°C. (See “Application Section” on page 25 for recommended crystal). The ISL12022 allows the user to input via I2C serial bus the temperature variation profile of an individual crystal. The oscillator compensation network can also be used to calibrate the initial crystal timing accuracy to less than 1ppm error at room temperature. The device can also be driven directly from a 32.768kHz source at pin X1. X1 X2 FIGURE 10. RECOMMENDED CRYSTAL CONNECTION VBAT This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the VDD supply fails. Device power will automatically switch to the VBAT input when VDD drops below the switchover trip level (VTRIP). This pin can be connected to a battery, a super capacitor or tied to ground if not used. IRQ/FOUT (Interrupt Output/Frequency Output) This dual function pin can be used as an interrupt or frequency output pin. The IRQ/FOUT mode is selected via the frequency out control bits of the control/status register. It is an open drain output. FN6659.2 June 23, 2009 ISL12022 • Interrupt Mode. The pin provides an interrupt signal output. This signal notifies a host processor that an alarm has occurred and requests action. It is an active low output. • Frequency Output Mode. The pin outputs a clock signal, which is related to the crystal frequency. The frequency is user selectable and enabled via the I2C bus. Battery-Backup Mode (VBAT) to Normal Mode (VDD) The ISL12022 device will switch from the VBAT to VDD mode when one of the following conditions occurs: Condition 1: VDD > VBAT + VBATHYS where VBATHYS ≈ 50mV Condition 2: VDD > VTRIP + VTRIPHYS where VTRIPHYS ≈ 30mV These power control situations are illustrated in Figures 11 and 12. BATTERY-BACKUP MODE Serial Clock (SCL) The SCL input is used to clock all serial data into and out of the device. The input buffer on this pin is always active (not gated). It is disabled when the backup power supply on the VBAT pin is activated to minimize power consumption. Serial Data (SDA) SDA is a bi-directional pin used to transfer data into and out of the device. It has an open drain output and may be ORed with other open drain or open collector outputs. The input buffer is always active (not gated) in normal mode. An open drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal with the use of a slope controlled pull-down. The circuit is designed for 400kHz I2C interface speeds. It is disabled when the backup power supply on the VBAT pin is activated. VDD VTRIP VBAT VBAT - VBATHYS 2.2V 1.8V VBAT + VBATHYS FIGURE 11. BATTERY SWITCHOVER WHEN VBAT < VTRIP VDD, GND Chip power supply and ground pins. The device will operate with a power supply from VDD = 2.7V to 5.5VDC. A 0.1µF capacitor is recommended on the VDD pin to ground. Functional Description Power Control Operation The power control circuit accepts a VDD and a VBAT input. Many types of batteries can be used with Intersil RTC products. For example, 3.0V or 3.6V Lithium batteries are appropriate, and battery sizes are available that can power the ISL12022 for up to 10 years. Another option is to use a super capacitor for applications where VDD is interrupted for up to a month. See the “Application Section” on page 25 for more information. VDD VBAT VTRIP VTRIP BATTERY-BACKUP MODE 3.0V 2.2V VTRIP + VTRIPHYS FIGURE 12. BATTERY SWITCHOVER WHEN VBAT > VTRIP Normal Mode (VDD) to Battery-Backup Mode (VBAT) To transition from the VDD to VBAT mode, both of the following conditions must be met: Condition 1: VDD < VBAT - VBATHYS where VBATHYS ≈ 50mV Condition 2: VDD < VTRIP where VTRIP ≈ 2.2V The I2C bus is deactivated in battery-backup mode to reduce power consumption. Aside from this, all RTC functions are operational during battery-backup mode. Except for SCL and SDA, all the inputs and outputs of the ISL12022 are active during battery-backup mode unless disabled via the control register. The device Time Stamps the switchover from VDD to VBAT and VBAT to VDD, and the time is stored in tSV2B and tSB2V registers respectively. If multiple VDD power-down sequences occur before status is read, the earliest VDD to VBAT power-down time is stored and the most recent VBAT to VDD time is stored. Temperature conversion and compensation can be enabled in battery-backup mode. Bit BTSE in the BETA register controls this operation, as described in “BETA Register (BETA)” on page 17. 9 FN6659.2 June 23, 2009 ISL12022 Power Failure Detection The ISL12022 provides a Real Time Clock Failure Bit (RTCF) to detect total power failure. It allows users to determine if the device has powered up after having lost all power to the device (both VDD and VBAT). corrects for months having fewer than 31 days and has a bit that controls 24-hour or AM/PM format. When the ISL12022 powers up after the loss of both VDD and VBAT, the clock will not begin incrementing until at least one byte is written to the clock register. Brownout Detection The ISL12022 monitors the VDD level continuously and provides warning if the VDD level drops below prescribed levels. There are six (6) levels that can be selected for the trip level. These values are 85% below popular VDD levels. The LVDD bit in the Status Register will be set to “1” when brownout is detected. Note that the I2C serial bus remains active unless the Battery VTRIP levels are reached. Single Event and Interrupt The alarm mode is enabled via the MSB bit. Choosing single event or interrupt alarm mode is selected via the IM bit. Note that when the frequency output function is enabled, the alarm function is disabled. The standard alarm allows for alarms of time, date, day of the week, month, and year. When a time alarm occurs in single event mode, the IRQ/FOUT pin will be pulled low and the alarm status bit (ALM) will be set to “1”. The pulsed interrupt mode allows for repetitive or recurring alarm functionality. Hence, once the alarm is set, the device will continue to alarm for each occurring match of the alarm and present time. Thus, it will alarm as often as every minute (if only the nth second is set) or as infrequently as once a year (if at least the nth month is set). During pulsed interrupt mode, the IRQ/FOUT pin will be pulled low for 250ms and the alarm status bit (ALM) will be set to “1”. The ALM bit can be reset by the user or cleared automatically using the auto reset mode (see ARST bit). The alarm function can be enabled/disabled during battery-backup mode using the FOBATB bit. For more information on the alarm, please see “ALARM Registers (10h to 15h)” on page 19. Battery Level Monitor The ISL12022 has a built in warning feature once the Back-up battery level drops first to 85% and then to 75% of the battery’s nominal VBAT level. When the battery voltage drops to between 85% and 75%, the LBAT85 bit is set in the status register. When the level drops below 75%, both LBAT85 and LBAT75 bits are set in the status register. The battery level monitor is not functional in battery backup mode. In order to read the monitor bits after powering up VDD, instigate a battery level measurement by setting the TSE bit to "1" (BETA register), and then read the bits. There is a Battery Time Stamp Function available. Once the VDD is low enough to enable switchover to the battery, the RTC time/date are written into the TSV2B register. This information can be read from the TSV2B registers to discover the point in time of the VDD power-down. If there are multiple power-down cycles before reading these registers, the first values stored in these registers will be retained. These registers will hold the original power-down value until they are cleared by setting CLRTS = 1 to clear the registers. The normal power switching of the ISL12022 is designed to switch into battery-backup mode only if the VDD power is lost. This will ensure that the device can accept a wide range of backup voltages from many types of sources while reliably switching into backup mode. Note that the ISL12022 is not guaranteed to operate with VBAT < 1.8V. If the battery voltage is expected to drop lower than this minimum, correct operation of the device, especially after a VDD power-down cycle, is not guaranteed. The minimum VBAT to insure SRAM is stable is 1.0V. Below that, the SRAM may be corrupted when VDD power resumes. Frequency Output Mode The ISL12022 has the option to provide a clock output signal using the IRQ/FOUT open drain output pin. The frequency output mode is set by using the FO bits to select 15 possible output frequency values from 1/32Hz to 32kHz. The frequency output can be enabled/disabled during battery-backup mode using the FOBATB bit. General Purpose User SRAM The ISL12022 provides 128 bytes of user SRAM. The SRAM will continue to operate in battery-backup mode. However, it should be noted that the I2C bus is disabled in battery-backup mode. I2C Serial Interface The ISL12022 has an I2C serial bus interface that provides access to the control and status registers and the user SRAM. The I2C serial interface is compatible with other industry I2C serial bus protocols using a bi-directional data signal (SDA) and a clock signal (SCL). Real Time Clock Operation The Real Time Clock (RTC) uses an external 32.768kHz quartz crystal to maintain an accurate internal representation of second, minute, hour, day of week, date, month, and year. The RTC also has leap-year correction. The clock also Oscillator Compensation The ISL12022 provides both initial timing correction and temperature correction due to variation of the crystal oscillator. Analog and digital trimming control is provided for initial adjustment, and a temperature compensation function is provided to automatically correct for temperature drift of FN6659.2 June 23, 2009 10 ISL12022 the crystal. Initial values are preset and recalled on initial power-up for the Initial AT and DT settings (IATR, IDTR), temperature coefficient (ALPHA), crystal capacitance (BETA), and the crystal turn-over temperature (XTO). These initial values are typical of units available on the market, although the user may program specific values after testing for best accuracy. The function can be enabled/disabled at any time and can be used in battery mode as well. 6. Daylight Savings Time (8 bytes): 20h to 27h. 7. TEMP (2 bytes): 28h to 29h 8. Crystal Net PPM Correction, NPPM (2 bytes): 2Ah, 2Bh 9. Crystal Turnover Temperature, XT0 (1 byte): 2Ch 10. Crystal ALPHA at high temperature, ALPHA_H (1 byte): 2Dh 11. Scratch Pad (2 bytes): Address 2Eh and 2Fh Write capability is allowable into the RTC registers (00h to 06h) only when the WRTC bit (bit 6 of address 08h) is set to “1”. A multi-byte read or write operation should be limited to one section per operation for best RTC time keeping performance. A register can be read by performing a random read at any address at any time. This returns the contents of that register location. Additional registers are read by performing a sequential read. For the RTC and Alarm registers, the read instruction latches all clock registers into a buffer, so an update of the clock does not change the time being read. At the end of a read, the master supplies a stop condition to end the operation and free the bus. After a read, the address remains at the previous address +1 so the user can execute a current address read and continue reading the next register. When the previous address is 2Fh, the next address will wrap around to 00h. It is not necessary to set the WRTC bit prior to writing into the control and status, alarm, and user SRAM registers. Register Descriptions The battery-backed registers are accessible following a slave byte of “1101111x” and reads or writes to addresses [00h:2Fh]. The defined addresses and default values are described in the Table 1. The battery backed general purpose SRAM has a different slave address (1010111x), so it is not possible to read/write that section of memory while accessing the registers. REGISTER ACCESS The contents of the registers can be modified by performing a byte or a page write operation directly to any register address. The registers are divided into 8 sections. They are: 1. Real Time Clock (7 bytes): Address 00h to 06h. 2. Control and Status (9 bytes): Address 07h to 0Fh. 3. Alarm (6 bytes): Address 10h to 15h. 4. Time Stamp for Battery Status (5 bytes): Address 16h to 1Ah. 5. Time Stamp for VDD Status (5 bytes): Address 1Bh to 1Fh. TABLE 1. REGISTER MEMORY MAP REG NAME SC MN HR RTC DT MO YR DW SR INT PWR_VDD PWR_VBAT CSR ITRO ALPHA BETA FATR FDTR IDTR01 D TSE 0 0 BIT 7 0 0 MIL 0 0 YR23 0 BUSY ARST CLRTS 6 SC22 MN22 0 0 0 YR22 0 OSCF WRTC D RESEALB IDTR00 ALPHA6 BTSE 0 0 5 SC21 MN21 HR21 DT21 0 YR21 0 DSTADJ IM D VB85Tp2 IATR05 ALPHA5 BTSR FFATR5 0 4 SC20 MN20 HR20 DT20 MO20 YR20 0 ALM FOBATB D VB85Tp1 IATR04 ALPHA4 BETA4 FATR4 FDTR4 3 SC13 MN13 HR13 DT13 MO13 YR13 0 LVDD FO3 D VB85Tp0 IATR03 ALPHA3 BETA3 FATR3 FDTR3 2 SC12 MN12 HR12 DT12 MO12 YR12 DW2 LBAT85 FO2 VDDTrip2 VB75Tp2 IATR02 ALPHA2 BETA2 FATR2 FDTR2 1 SC11 MN11 HR11 DT11 MO11 YR11 DW1 LBAT75 FO1 VDDTrip1 VB75Tp1 IATR01 ALPHA1 BETA1 FATR1 FDTR1 0 SC10 MN10 HR10 DT10 MO10 YR10 DW0 RTCF FO0 VDDTrip0 VB75Tp0 IATR00 ALPHA0 BETA0 FATR0 FDTR0 RANGE 0 to 59 0 to 59 0 to 23 1 to 31 1 to 12 0 to 99 0 to 6 N/A N/A N/A N/A N/A N/A N/A N/A N/A DEFAULT 00h 00h 00h 01h 01h 00h 00h 01h 01h 00h 00h 20h 46h 00h 00h 00h ADDR. SECTION 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 11 FN6659.2 June 23, 2009 ISL12022 TABLE 1. REGISTER MEMORY MAP (Continued) REG NAME SCA0 MNA0 HRA0 ALARM DTA0 MOA0 DWA0 VSC VMN TSV2B VHR VDT VMO BSC BMN TSB2V BHR BDT BMO DstMoFd DstDwFd DstDtFd DstHrFd DSTCR DstMoRv DstDwRv DstDtRv DstHrRv TK0L TEMP TK0M NPPML NPPM XT0 ALPHAH GPM NPPMH XT0 ALPHAH GPM1 GPM2 BIT 7 ESCA0 EMNA0 EHRA0 EDTA0 EMOA00 EDWA0 0 0 VMIL 0 0 0 0 BMIL 0 0 DSTE D D D D D D D TK07 0 NPPM7 0 D D GPM17 GPM27 6 SCA022 MNA022 D D D D VSC22 VMN22 0 0 0 BSC22 BMN22 0 0 0 D DstDwFdE D D D DstDwRvE D D TK06 0 NPPM6 0 D ALP_H6 GPM16 GPM26 5 SCA021 MNA021 HRA021 DTA021 D D VSC21 VMN21 VHR21 VDT21 0 BSC21 BMN21 BHR21 BDT21 0 D 4 SCA020 MNA020 HRA020 DTA020 MOA020 D VSC20 VMN20 VHR20 VDT20 VMO20 BSC20 BMN20 BHR20 BDT20 BMO20 3 SCA013 MNA013 HRA013 DTA013 MOA013 D VSC13 VMN13 VHR13 VDT13 VMO13 BSC13 BMN13 BHR13 BDT13 BMO13 2 SCA012 MNA012 HRA012 DTA012 MOA012 DWA02 VSC12 VMN12 VHR12 VDT12 VMO12 BSC12 BMN12 BHR12 BDT12 BMO12 1 SCA011 MNA011 HRA011 DTA011 MOA011 DWA01 VSC11 VMN11 VHR11 VDT11 VMO11 BSC11 BMN11 BHR11 BDT11 BMO11 0 SCA010 MNA010 HRA010 DTA010 MOA010 DWA00 VSC10 VMN10 VHR10 VDT10 VMO10 BSC10 BMN10 BHR10 BDT10 BMO10 RANGE 00 to 59 00 to 59 0 to 23 01 to 31 01 to 12 0 to 6 0 to 59 0 to 59 0 to 23 1 to 31 1 to 12 0 to 59 0 to 59 0 to 23 1 to 31 1 to 12 1 to 12 0 to 6 1 to 31 0 to 23 01 to 12 0 to 6 01 to 31 0 to 23 00 to FF 00 to 03 00 to FF 00 to 07 00 to FF 00 to 7F 00 to FF 00 to FF DEFAULT 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 46h 00h 00h ADDR. SECTION 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh DstMoFd20 DstMoFd13 DstMoFd12 DstMoFd11 DstMoFd10 DstWkFd12 DstWkFd11 DstWkFd10 DstDwFd12 DstDwFd11 DstDwFd10 DstDtFd21 DstHrFd21 D DstDtFd20 DstHrFd20 DstDtFd13 DstHrFd13 DstDtFd12 DstHrFd12 DstDtFd11 DstHrFd11 DstDtFd10 DstHrFd10 XDstMoRv2 DstMoRv13 DstMoR12v DstMoRv11 DstMoRv10 0 DstWkrv12 DstWkRv11 DstWkRv10 DstDwRv12 DstDwRv11 DstDwRv10 DstDtRv21 DstHrRv21 TK05 0 NPPM5 0 D ALP_H5 GPM15 GPM25 DstDtRv20 DstHrRv20 TK04 0 NPPM4 0 XT4 ALP_H4 GPM14 GPM24 DstDtRv13 DstHrRv13 TK03 0 NPPM3 0 XT3 ALP_H3 GPM13 GPM23 DstDtRv12 DstHrRv12 TK02 0 NPPM2 NPPM10 XT2 ALP_H2 GPM12 GPM22 DstDtRv11 DstHrRv11 TK01 TK09 NPPM1 NPPM9 XT1 ALP_H1 GPM11 GPM21 DstDtRv10 DstHrRv10 TK00 TK08 NPPM0 NPPM8 XT0 ALP_H0 GPM10 GPM20 12 FN6659.2 June 23, 2009 ISL12022 Real Time Clock Registers Addresses [00h to 06h] RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW) These registers depict BCD representations of the time. As such, SC (Seconds) and MN (Minutes) range from 0 to 59, HR (Hour) can either be a 12-hour or 24-hour mode, DT (Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99, and DW (Day of the Week) is 0 to 6. The DW register provides a Day of the Week status and uses three bits DW2 to DW0 to represent the seven days of the week. The counter advances in the cycle 0-1-2-3-4-5-6-0-12-… The assignment of a numerical value to a specific day of the week is arbitrary and may be decided by the system software designer. The default value is defined as “0”. 24 HOUR TIME If the MIL bit of the HR register is “1”, the RTC uses a 24-hour format. If the MIL bit is “0”, the RTC uses a 12-hour format and HR21 bit functions as an AM/PM indicator with a “1” representing PM. The clock defaults to 12-hour format time with HR21 = “0”. LEAP YEARS Leap years add the day February 29 and are defined as those years that are divisible by 4. Years divisible by 100 are not leap years, unless they are also divisible by 400. This means that the year 2000 is a leap year and the year 2100 is not. The ISL12022 does not correct for the leap year in the year 2100. OSCILLATOR FAIL BIT (OSCF) Oscillator Fail Bit indicates that the oscillator has stopped. DAYLIGHT SAVINGS TIME CHANGE BIT (DSTADJ) DSTADJ is the Daylight Savings Time Adjusted Bit. It indicates the daylight saving time forward adjustment has happened. If a DST Forward event happens, DSTADJ will be set to “1”. The DSTADJ bit will stay high after the DSTFD event happens, and will be reset to “0” when the DST Reverse event happens. DSTADJ can be set to “1” for instances where the RTC device is initialized during the DST Forward period. The DSTE bit must be enabled when the RTC time is more than one hour before the DST Forward or DST Reverse event time setting, or the DST event correction will not happen. DSTADJ is reset to “0” upon power-up. It will reset to ”0” when the DSTE bit in Register 15h is set to “0” (DST disabled), but no time adjustment will happen. ALARM BIT (ALM) This bit announces if the alarm matches the real time clock. If there is a match, the respective bit is set to “1”. This bit can be manually reset to “0” by the user or automatically reset by enabling the auto-reset bit (see ARST bit). A write to this bit in the SR can only set it to “0”, not “1”. An alarm bit that is set by an alarm occurring during an SR read operation will remain set after the read operation is complete. LOW VDD INDICATOR BIT (LVDD) This bit indicates when VDD has dropped below the pre-selected trip level (Brownout Mode). The trip points for the brownout levels are selected by three bits: VDD Trip2, VDD Trip1 and VDD Trip0 in PWR_ VDD registers. The LVDD detection is only enabled in VDD mode and the detection happens in real time. The LVDD bit is set whenever the VDD has dropped below the pre-selected trip level, and self clears whenever the VDD is above the preselected trip level. LOW BATTERY INDICATOR 85% BIT (LBAT85) In Normal Mode (VDD), this bit indicates when the battery level has dropped below the pre-selected trip levels. The trip points are selected by three bits: VB85Tp2, VB85Tp1 and VB85Tp0 in the PWR_VBAT registers. The LBAT85 detection happens automatically once every minute when seconds register reaches 59. The detection can also be manually triggered by setting the TSE bit in BETA register to “1”. The LBAT85 bit is set when the VBAT has dropped below the pre-selected trip level, and will self clear when the VBAT is above the pre-selected trip level at the next detection cycle either by manual or automatic trigger. In Battery Mode (VBAT), this bit indicates the device has entered into battery mode by polling once every 10 minutes. The LBAT85 detection happens automatically once when the minute register reaches x9h or x0h minutes. Control and Status Registers (CSR) Addresses [07h to 0Fh] The Control and Status Registers consist of the Status Register, Interrupt and Alarm Register, Analog Trimming and Digital Trimming Registers. Status Register (SR) The Status Register is located in the memory map at address 07h. This is a volatile register that provides either control or status of RTC failure (RTCF), Battery Level Monitor (LBAT85, LBAT75), alarm trigger, Daylight Savings Time, crystal oscillator enable and temperature conversion in progress bit. TABLE 2. STATUS REGISTER (SR) ADDR 07h 7 6 5 4 3 2 1 0 BUSY OSCF DSTDJ ALM LVDD LBAT85 LBAT75 RTCF BUSY BIT (BUSY) Busy Bit indicates temperature sensing is in progress. In this mode, Alpha, Beta and ITRO registers are disabled and cannot be accessed. 13 FN6659.2 June 23, 2009 ISL12022 Example - When the LBAT85 is Set To “1” In Battery Mode: The minute the register changes to 19h when the device is in battery mode, the LBAT85 is set to “1” the next time the device switches back to Normal Mode. Example - When the LBAT85 Remains at “0” In Battery Mode: If the device enters into battery mode after the minute register reaches 20h and switches back to Normal Mode before the minute register reaches 29h, then the LBAT85 bit will remain at “0” the next time the device switches back to Normal Mode. LOW BATTERY INDICATOR 75% BIT (LBAT75) In Normal Mode (VDD), this bit indicates when the battery level has dropped below the pre-selected trip levels. The trip points are selected by three bits: VB75Tp2, VB75Tp1 and VB75Tp0 in the PWR_VBAT registers. The LBAT75 detection happens automatically once every minute when seconds register reaches 59. The detection can also be manually triggered by setting the TSE bit in BETA register to “1”. The LBAT75 bit is set when the VBAT has dropped below the pre-selected trip level, and will self clear when the VBAT is above the pre-selected trip level at the next detection cycle either by manual or automatic trigger. In Battery Mode (VBAT), this bit indicates the device has entered into battery mode by polling once every 10 minutes. The LBAT85 detection happens automatically once when the minute register reaches x9h or x0h minutes. Example - When the LBAT75 is Set to “1” in Battery Mode: The minute register changes to 30h when the device is in battery mode, the LBAT75 is set to “1” the next time the device switches back to Normal Mode. Example - When the LBAT75 Remains at “0” in Battery Mode: If the device enters into battery mode after the minute register reaches 49h and switches back to Normal Mode before minute register reaches 50h, then the LBAT75 bit will remain at “0” the next time the device switches back to Normal Mode. REAL TIME CLOCK FAIL BIT (RTCF) This bit is set to a “1” after a total power failure. This is a read only bit that is set by hardware (ISL12022 internally) when the device powers up after having lost all power (defined as VDD = 0V and VBAT = 0V). The bit is set regardless of whether VDD or VBAT is applied first. The loss of only one of the supplies does not set the RTCF bit to “1”. The first valid write to the RTC section after a complete power failure resets the RTCF bit to “0” (writing one byte is sufficient). AUTOMATIC RESET BIT (ARST) This bit enables/disables the automatic reset of the ALM, LVDD, LBAT85, and LBAT75 status bits only. When ARST bit is set to “1”, these status bits are reset to “0” after a valid read of the respective status register (with a valid STOP condition). When the ARST is cleared to “0”, the user must manually reset the ALM, LVDD, LBAT85, and LBAT75 bits. WRITE RTC ENABLE BIT (WRTC) The WRTC bit enables or disables write capability into the RTC Timing Registers. The factory default setting of this bit is “0”. Upon initialization or power-up, the WRTC must be set to “1” to enable the RTC. Upon the completion of a valid write (STOP), the RTC starts counting. The RTC internal 1Hz signal is synchronized to the STOP condition during a valid write cycle. INTERRUPT/ALARM MODE BIT (IM) This bit enables/disables the interrupt mode of the alarm function. When the IM bit is set to “1”, the alarm will operate in the interrupt mode, where an active low pulse width of 250ms will appear at the IRQ/FOUT pin when the RTC is triggered by the alarm, as defined by the alarm registers (0Ch to 11h). When the IM bit is cleared to “0”, the alarm will operate in standard mode, where the IRQ/FOUT pin will be set low until the ALM status bit is cleared to “0”. TABLE 4. IM BIT 0 1 INTERRUPT/ALARM FREQUENCY Single Time Event Set By Alarm Repetitive/Recurring Time Event Set By Alarm FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB) This bit enables/disables the IRQ/FOUT pin during battery-backup mode (i.e. VBAT power source active). When the FOBATB is set to “1”, the IRQ/FOUT pin is disabled during battery-backup mode. This means that both the frequency output and alarm output functions are disabled. When the FOBATB is cleared to “0”, the IRQ/FOUT pin is enabled during battery-backup mode. Note that the open drain IRQ/FOUT pin will need a pull-up to the battery voltage to operate in battery-backup mode. FREQUENCY OUT CONTROL BITS (FO) These bits enable/disable the frequency output function and select the output frequency at the IRQ/FOUT pin. See Table 5 for frequency selection. Default for the ISL12022 is FO = 1h, or 32.768kHz output. When the frequency mode is enabled, it will override the alarm mode at the IRQ/FOUT pin. Interrupt Control Register (INT) TABLE 3. INTERRUPT CONTROL REGISTER (INT) ADDR 08h 7 6 5 IM 4 3 2 1 0 ARST WRTC FOBATB FO3 FO2 FO1 FO0 14 FN6659.2 June 23, 2009 ISL12022 TABLE 5. FREQUENCY SELECTION OF IRQ/FOUT PIN FREQUENCY, FOUT UNITS 0 32768 4096 1024 64 32 16 8 4 2 1 1/2 1/4 1/8 1/16 1/32 Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz FO3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FO2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FO1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FO0 0 1 ADDR 7 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0Ah 6 5 Battery Voltage Trip Voltage Register (PWR_VBAT) This register controls the trip points for the two VBAT alarms, with levels set to approximately 85% and 75% of the nominal battery level. TABLE 7. 4 3 2 1 0 D RESEALB VB85Tp2 VB85Tp1 VB85Tp0 VB75Tp2 VB75Tp1 VB75Tp0 RESEAL BIT (RESEALB) This is the Reseal bit for actively disconnecting VBAT pin from the internal circuitry. Setting this bit allows the device to disconnect the battery and eliminate standby current drain while the device is unused. Once VDD is powered up, this bit is reset and the VBAT pin is then connected to the internal circuitry. The application for this bit involves placing the chip on a board with a battery and testing the board. Once the board is tested and ready to ship, it is desirable to disconnect the battery to keep it fresh until the board or unit is placed into final use. Setting RESEALB = “1” initiates the battery disconnect, and after VDD power is cycled down and up again, the RESEAL bit is cleared to “0”. BATTERY LEVEL MONITOR TRIP BITS (VB85TP) Three bits select the first alarm (85% of Nominal VBAT) level for the battery voltage monitor. There are total of 7 levels that could be selected for the first alarm. Any of the of levels could be selected as the first alarm with no reference as to nominal Battery voltage level. See Table 8. TABLE 8. VB85T ALARM LEVEL BATTERY ALARM TRIP LEVEL (V) 2.125 2.295 2.550 2.805 3.060 4.250 4.675 POWER SUPPLY CONTROL REGISTER (PWR_VDD) Clear Time Stamp Bit (CLRTS) ADDR 09h 7 CLRTS 6 0 5 0 4 0 3 0 2 1 0 VDDTrip2 VDDTrip1 VDDTrip0 This bit clears Time Stamp VDD to Battery (TSV2B) and Time Stamp Battery to VDD Registers (TSB2V). The default setting is 0 (CLRTS = 0) and the Enabled setting is 1 (CLRTS = 1). VB85Tp2 0 0 0 0 VB85Tp1 0 0 1 1 0 0 1 VB85Tp0 0 1 0 1 0 1 0 VDD Brownout Trip Voltage BITS (VDDTrip 2.7V. Note that the device is not guaranteed to operate with a VBAT < 1.8V, so the battery should be changed before discharging to that level. It is strongly advised to monitor the low battery indicators in the status registers and take action to replace discharged batteries. If a supercapacitor is used, it is possible that it may discharge to below 1.8V during prolonged power-down. Once powered up, the device may lose serial bus communications until both VDD and VBAT are powered down together. To avoid that situation, including situations where a battery may discharge deeply, the circuit in Figure 18 can be used. VDD = 2.7V TO 5.5V CIN 0.1µF GND ISL12022 VDD VBAT CBAT 0.1µF JBAT DBAT BAT43W + VBAT = 1.8V TO 3.2V lists some recommended surface mount crystals and the parameters of each. This list is not exhaustive and other surface mount devices can be used with the ISL12022 if their specifications are very similar to the devices listed. The crystal should have a required parallel load capacitance of 12.5pF and an equivalent series resistance of less than 50k. The crystal’s temperature range specification should match the application. Many crystals are rated for -10°C to +60°C (especially through-hole and tuning fork types), so an appropriate crystal should be selected if extended temperature range is required. Layout Considerations The crystal input at X1 has a very high impedance, and oscillator circuits operating at low frequencies (such as 32.768kHz) are known to pick up noise very easily if layout precautions are not followed. Most instances of erratic clocking or large accuracy errors can be traced to the susceptibility of the oscillator circuit to interference from adjacent high speed clock or data lines. Careful layout of the RTC circuit will avoid noise pickup and insure accurate clocking. Figure 19 shows a suggested layout for the ISL12022 device using a surface mount crystal. Two main precautions should be followed: • Do not run the serial bus lines or any high speed logic lines in the vicinity of the crystal. These logic level lines can induce noise in the oscillator circuit, causing misclocking. • Add a ground trace around the crystal with one end terminated at the chip ground. This will provide termination for emitted noise in the vicinity of the RTC device. FIGURE 18. SUGGESTED BATTERY-BACKUP CIRCUIT The diode, DBAT will add a small drop to the battery voltage but will protect the circuit should battery voltage drop below 1.8V. The jumper is added as a safeguard should the battery ever need to be disconnect from the circuit. The VDD negative slew rate should be limited to below the data sheet spec (10V/ms) otherwise battery switchover can be delayed, resulting in SRAM contents corruption and oscillator operation interruption. Some applications will require separate supplies for the RTC VDD and the I2C pull-ups. This is not advised, as it may compromise the operation of the I2C bus. For applications that do require serial bus communication with the RTC VDD powered down, the SDA pin must be pulled low during the time the RTC VDD ramps down to 0V. Otherwise, the device may lose serial bus communications once VDD is powered up, and will return to normal operation ONLY once VDD and VBAT are both powered down together. FIGURE 19. SUGGESTED LAYOUT FOR ISL12022 AND CRYSTAL In addition, it is a good idea to avoid a ground plane under the X1 and X2 pins and the crystal, as this will affect the load capacitance and therefore the oscillator accuracy of the circuit. If the ~IRQ/FOUT pin is used as a clock, it should be routed away from the RTC device as well. The traces for the VBAT and VDD pins can be treated as a ground, and should be routed around the crystal. Applications Information Crystal Oscillator Frequency Compensation CRYSTAL CHARACTERISTICS The ISL12022 device contains a complete system for adjusting the frequency of the crystal oscillator to FN6659.2 June 23, 2009 Oscillator Crystal Requirements The ISL12022 uses a standard 32.768kHz crystal. Either through hole or surface mount crystals can be used. Table 26 25 ISL12022 compensate for temperature variation. A typical 32.768kHz crystal used with RTC devices has a temperature versus frequency curve, as shown in Figure 21. 0 -20 -40 -60 PPM -80 -100 -120 -140 -160 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) capacitance to change the frequency in increments of 1ppm. The adjustment range for the ISL12022 is +32/-31ppm. The AT can be further refined using the BETA register. the BETA register function is to allow for changes in CM (motional capacitance) which will affect the incremental frequency change of the AT adjustment. A simple test procedure uses the BETA register to bring the step size back to 1ppm. Normally, the crystal frequency is adjusted at room temperature to zero out the frequency error using the IATRxx register bits (initial Analog Trimming). In addition, the IATRxx setting is varied up and down to record the variation in oscillator frequency compared to the step change in IATRxx. Once that value is known then the BETA register is used to adjust the step size to be as close to 1ppm per IATRxx step as possible. After that adjustment is made, then any ISL12022 temperature compensation adjustments will use a 1ppm change for each bit change in the internal AT adjustment. The Digital Trimming (DT) uses clock pulse add/subtract logic to change the RTC timing during temperature compensation. The DT steps are much coarser than the AT steps and are therefore used for large adjustments. The DT steps are 30.5ppm, and the range is from -305ppm to +305ppm. The Frequency Output function will show the clock variation with DT settings, except for the 32,768Hz setting which only shows the AT control. ACTIVE TEMPERATURE COMPENSATION The ISL12022 contains an intelligent logic circuit which takes the temperature sensor digital value as the only input variable. It then uses the register values for the crystal variables α and T0, and combines those with calibration from the BETA and ITR0 registers to produce “Final” values for the AT and DT, known as FATR (Final AT Register) and FDTR (Final DT Register). Those AT and DT values combine to directly compensate for the temperature error shown in Figure 21. The temperature sensor produces a new value every 60s (or up to 10 minutes in battery mode), which triggers the logic to calculate a new AT/DT value set. For every temperature calculation result, there can only be one corresponding AT/DT correction value. FIGURE 21. RTC CRYSTAL TEMPERATURE DRIFT The curve in Figure 21 follows Equation 7: Δ f = α • ( T – T0 ) 2 (EQ. 7) Where α is the temperature constant, with a typical value of 0.034 ppm/°C. T0 is the turnover temperature of the crystal, which is the apex of the parabolic curve. If the two factors α and T0 are known, it is possible to correct for crystal temperature error to very high accuracy. The crystal will have an initial accuracy error at room temperature, typically specified at ±20°C. The other important characteristic is the capacitances associated with the crystal. The load capacitance is normally specified at 12.5pF, although it can be lower in some cases. There is also a motional capacitance which affects the ability of the load capacitance to pull the oscillation frequency, and it is usually in the range of 2.2fF to 4.0fF. RTC CLOCK CONTROL The ISL12022 uses two mechanisms to adjust the RTC clock and correct for the temperature error of the external crystal. The Analog Trimming (AT) adjusts the load capacitance seen by the crystal. Analog switches connect the appropriate SIGNALS FROM THE MASTER S T A R T IDENTIFICATION BYTE WITH R/W = 0 ADDRESS BYTE S T IDENTIFICATION A BYTE WITH R R/W = 1 T A C K A C K S T O P SIGNAL AT SDA SIGNALS FROM THE SLAVE 11011110 A C K A C K 11011111 A C K FIRST READ DATA BYTE LAST READ DATA BYTE FIGURE 20. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN) 26 FN6659.2 June 23, 2009 ISL12022 Measuring Oscillator Accuracy The best way to analyze the ISL12022 frequency accuracy is to set the IRQ/FOUT pin for a specific frequency, and look at the output of that pin on a high accuracy frequency counter (at least 7 digits accuracy). Note that the IRQ/FOUT is a drain output and will require a pull-up resistor. Using the 1.0Hz output frequency is the most convenient as the ppm error is as expressed in Equation 8: ppm error = ( F OUT – 1 ) • 1e6 (EQ. 8) temperature for aging or board mounting. The original recalled value can be re-written if desired after testing. For further information on the operation of the ISL12022 and temperature compensated RTC’s, see Intersil Application Note AN1389, “Using Intersil’s High Accuracy Real Time Clock Module”. http://www.intersil.com/data/an/AN1389.pdf Daylight Savings Time (DST) Example DST involves setting the forward and back times and allowing the RTC device to automatically advance the time or set the time back. This can be done for current year, and future years. Many regions have DST rules that use standard months, weeks and time of the day which permit a pre-programmed, permanent setting. Table 27 shows the example setup for the ISL12022. TABLE 27. DST EXAMPLE VARIABLE VALUE REGISTER 15h 16h VALUE 84h 48h Other frequencies may be used for measurement but the error calculation becomes more complex. When the proper layout guidelines are observed, the oscillator should start up in most circuits in less than 1s. When testing RTC circuits, a common impulse is to apply a scope probe to the circuit at the X2 pin (oscillator output) and observe the waveform. DO NOT DO THIS! Although in some cases you may see a usable waveform, due to the parasitics (usually 10pF to ground) applied with the scope probe, there will be no useful information in that waveform other than the fact that the circuit is oscillating. The X2 output is sensitive to capacitive impedance so the voltage levels and the frequency will be affected by the parasitic elements in the scope probe. Use the FOUT output and a frequency counter for the most accurate results. Month Forward and DST April Enable Week and Day Forward 1st Week and and select Day/Week, not Sunday Date Date Forward Hour Forward Month Reverse not used 2am October 17h 18h 19h 00h 02h 10h 78h Temperature Compensation Operation The ISL12022 temperature compensation feature needs to be enabled by the user. This must be done in a specific order as follows. 1. Read register 0Dh, the BETA register. This register contains the 5-bit BETA trimmed value which is automatically loaded on initial power-up. Mask off the 5LSB’s of the value just read. 2. Bit 7 of the BETA register is the master enable control for temperature sense operation. Set this to “1” to allow continuous temperature frequency correction. Frequency correction will then happen every 60s with VDD applied. 3. Bits 5 and 6 of the BETA register control temperature compensation in battery-backup mode (see Table 15). Set the values for the operation desired. 4. Write back to register 0Dh making sure not to change the 5 LSB values, and include the desired compensation control bits. Note that every time the BETA register is written with the TSE bit = 1, a temperature compensation cycle is instigated and a new correction value will be loaded into the FATR/FDTR registers (if the temperature changed since the last conversion). Also note that registers 0Bh and 0Ch, the ITR0 and ALPHA registers, should not be changed. If they must be written be sure to write the same values that are recalled from initial power-up. The ITR0 register may be written if the user wishes to re-calibrate the oscillator frequency at room 27 Week and Day Reverse Last Week and 1Ah and select Day/Week, not Sunday Date Date Reverse Hour Reverse not used 2am 1Bh 1Ch 00h 02h The Enable bit (DSTE) is in the Month forward register, so the BCD value for that register is altered with the additional bit. The Week and Day values along with Week/Day vs Date select bit is in the Week/Day register, so that value is also not straight BCD. Hour and Month are normal BCD, but the Hour doesn’t use the MIL bit since Military time PM values are already discretely different from AM/PM time PM values. The DST reverse setting utilizes the option to select the last week of the month for October, which could have 4 or 5 weeks but needs to have the time change on the last Sunday. Note that the DSTADJ bit in the status register monitors whether the DST forward adjustment has happened. When it is “1”, DST forward has taken place. When it is “0”, then either DST reverse has happened, or it has been reset either by initial power-up or if the DSTE bit has been set to “0”. FN6659.2 June 23, 2009 ISL12022 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45° H 0.25(0.010) M BM M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 L MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 8 8° 0° 8° MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05 MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 0.2284 0.0099 0.016 8 0° MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 0.2440 0.0196 0.050 B C D E e H C α A1 0.10(0.004) 0.050 BSC 1.27 BSC e B 0.25(0.010) M C AM BS h L N NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 28 FN6659.2 June 23, 2009