ISL12022
FN6659
Rev.3.01
Oct 24, 2019
Low Power RTC with Battery-Backed SRAM and Embedded Temp Compensation
±5ppm with Auto Daylight Saving
Features
The ISL12022 device is a low power real time clock with an
embedded Temp sensor for oscillator compensation,
clock/calendar, power fail, low battery monitor, brownout
indicator, single periodic or polled alarms, intelligent
battery-backup switching, Battery Reseal™ function, and
128 bytes of battery-backed user SRAM.
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes and Seconds
- Day of the Week, Day, Month, and Year
• On-chip Oscillator Compensation Over the Operating
Temperature Range
- ±5ppm Over -40°C to +85°C
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year, and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
• 10-bit Digital Temperature Sensor Output
- ±2°C Accuracy
• Customer Programmable Day Light Saving Time
Daylight Savings time adjustment is done automatically, using
parameters entered by the user. Power fail and battery
monitors offer user-selectable trip levels. A time stamp
function records the time and date of switchover from VDD to
VBAT power, and also from VBAT to VDD power.
• 15 Selectable Frequency Outputs
Applications
• Battery Reseal™ Function to Extend Battery Shelf Life
• 1 Alarm
- Settable to the Second, Minute, Hour, Day of the Week,
Day, or Month
- Single Event or Pulse Interrupt Mode
• Automatic Backup to Battery or Super Capacitor
- Operation to VBAT = 1.8V
- 1.0µA Battery Supply Current
• Utility Meters
• POS Equipment
• Medical Devices
• Battery Status Monitor
- 2 User Programmable Levels
- Seven Selectable Voltages for Each Level
• Security Systems
• Vending Machines
• White Goods
• Power Status Brownout Monitor
- Six Selectable Trip Levels, from 2.295V to 4.675V
• Printers and Copiers
• Oscillator Failure Detection
Related Literature
• Time Stamp for First VDD to VBAT, and Last VBAT to VDD
For a full list of related documents, visit our website
• 128 Bytes Battery-Backed User SRAM
• ISL12022 device page
• I2C Bus™
- 400kHz Clock Frequency
• 1µA Typical Battery Current
• Pb-Free (RoHS Compliant)
VDD = 2.7V
TO 5.5V
ISL12022
VDD
JBAT
DBAT
BAT43W
VBAT
CIN
0.1µF
CBAT
0.1µF
+ VBAT = 1.8V
TO 3.2V
GND
FIGURE 1. TYPICAL APPLICATION CIRCUIT
FN6659 Rev.3.01
Oct 24, 2019
Page 1 of 32
ISL12022
Table of Contents
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DC Operating Characteristics - RTC . . . . . . . . . . . . . . . . . . . . 5
Power-Down Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
I2C Interface Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SDA vs SCL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Symbol Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Control and Status Registers (CSR). . . . . . . . . . . . . . . . . . . 15
Addresses [07h to 0Fh] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Control Register (INT) . . . . . . . . . . . . . . . . . . . . . . . .
VDD Brownout Trip Voltage BITS (VDDTrip3kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300V
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
8 Ld SOIC (Notes 4, 5) . . . . . . . . . . . . . . . . .
102
46
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See TB379 for details.
5. For JC, the “case temp” location is taken at the package top center.
DC Operating Characteristics - RTC Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise stated.
Boldface limits apply over the operating temperature range, -40°C to +85°C
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 13)
TYP
(Note 9)
MAX
(Note 13)
UNIT
NOTES
VDD
Main Power Supply
(Note 15)
2.7
5.5
V
VBAT
Battery Supply Voltage
(Note 15)
1.8
5.5
V
6
IDD1
Supply Current. (I2C not Active, Temperature
VDD = 5V
4.1
15
µA
7, 8
VDD = 3V
3.5
14
µA
7, 8
IDD2
Supply Current. (I2C Active, Temperature
VDD = 5V
200
500
µA
7, 8
IDD3
Supply Current. (I2C not Active, Temperature
Conversion Active, FOUT not Active)
VDD = 5V
120
400
µA
7, 8
IBAT
Battery Supply Current
VDD = 0V, VBAT = 3V, TA = +25°C
1.0
1.6
µA
7
VDD = 0V, VBAT = 3V
1.0
5.0
µA
7
100
nA
IBATLKG
Conversion not Active, FOUT not Active)
Conversion not Active, FOUT not Active)
Battery Input Leakage
VDD = 5.5V, VBAT = 1.8V
ILI
Input Leakage Current on SCL
VIL = 0V, VIH = 5.5V
-1.0
±0.1
1.0
µA
ILO
I/O Leakage Current on SDA
VIL = 0V, VIH = 5.5V
-1.0
±0.1
1.0
µA
VBATM
Battery Level Monitor Threshold
-100
+100
mV
VPBM
Brownout Level Monitor Threshold
-100
+100
mV
V TRIP
VBAT Mode Threshold
2.4
V
(Note 15)
2.0
2.2
V TRIPHYS V TRIP Hysteresis
30
mV
11
VBATHYS
50
mV
11
VBAT Hysteresis
FoutT
Oscillator Stability vs Temperature
VDD 3.3V
-5
+5
ppm
14
FoutV
Oscillator Stability vs Voltage
2.7V VDD 5.5V
-3
+3
ppm
14
ATLSB
AT Sensitivity per LSB
BETA (4:0) = 10000
2
ppm
14
Temperature Sensor Accuracy
VDD = VBAT = 3.3V
°C
11
Temp
0.5
1
±2
IRQ/FOUT (OPEN DRAIN OUTPUT)
VOL
Output Low Voltage
FN6659 Rev.3.01
Oct 24, 2019
VDD = 5.5V, IOL = 3mA
0.4
V
VDD = 2.7V, IOL = 1mA
0.4
V
Page 5 of 32
ISL12022
Power-Down Timing Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise stated. Boldface limits apply over the
operating temperature range, -40°C to +85°C
SYMBOL
PARAMETER
VDD SR-
VDD Negative Slew Rate
VDDSR+
VDD Positive Slew Rate, Minimum
CONDITIONS
MIN
(Note 13)
TYP
(Note 9)
MAX
(Note 13)
UNIT
NOTES
10
V/ms
10
V/ms
16
0.05
I2C Interface Specifications
Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +85°C
SYMBOL
PARAMETER
VIL
SDA and SCL Input Buffer LOW Voltage
VIH
SDA and SCL Input Buffer HIGH Voltage
Hysteresis
TEST CONDITIONS
SDA and SCL Input Buffer Hysteresis
MIN
(Note 13)
TYP
(Note 9)
MAX
(Note 13)
UNIT
-0.3
0.3 x VDD
V
0.7 x VDD
VDD + 0.3
V
0.05 x VDD
VOL
SDA Output Buffer LOW Voltage,
Sinking 3mA
VDD = 5V, IOL = 3mA
CPIN
SDA and SCL Pin Capacitance
TA = +25°C, f = 1MHz, VDD = 5V,
VIN = 0V, VOUT = 0V
fSCL
SCL Frequency
0
V
0.02
0.4
V
10
pF
400
kHz
tIN
Pulse Width Suppression Time at SDA
and SCL Inputs
Any pulse narrower than the max
spec is suppressed.
50
ns
tAA
SCL Falling Edge To SDA Output Data
Valid
SCL falling edge crossing 30% of
VDD, until SDA exits the 30% to
70% of VDD window.
900
ns
tBUF
Time the Bus Must be Free Before the
Start of a New Transmission
SDA crossing 70% of VDD during
a STOP condition, to SDA
crossing 70% of VDD during the
following START condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VDD
crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VDD
crossing.
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling
edge. Both crossing 70% of VDD.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing
30% of VDD to SCL falling edge
crossing 70% of VDD.
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to
70% of VDD window, to SCL rising
edge crossing 30% of VDD.
100
ns
tHD:DAT
Input Data Hold Time
From SCL falling edge crossing
30% of VDD to SDA entering the
30% to 70% of VDD window.
0
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing
70% of VDD, to SDA rising edge
crossing 30% of VDD.
600
ns
tHD:STO
STOP Condition Hold Time
From SDA rising edge to SCL
falling edge. Both crossing 70%
of VDD.
600
ns
Output Data Hold Time
From SCL falling edge crossing
30% of VDD, until SDA enters the
30% to 70% of VDD window.
0
ns
tDH
FN6659 Rev.3.01
Oct 24, 2019
900
NOTES
11, 12
11, 12
ns
Page 6 of 32
ISL12022
I2C Interface Specifications
Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +85°C (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 13)
TYP
(Note 9)
MAX
(Note 13)
UNIT
NOTES
tR
SDA and SCL Rise Time
From 30% to 70% of VDD.
20 + 0.1 x Cb
300
ns
12
tF
SDA and SCL Fall Time
From 70% to 30% of VDD.
20 + 0.1 x Cb
300
ns
12
Cb
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
12
RPU
SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by tR
and tF.
For Cb = 400pF, max is about
2kΩ~2.5kΩ.
For Cb = 40pF, max is about
15kΩ~20kΩ
1
kΩ
12
NOTES:
6. Temperature Conversion is inactive below VBAT = 2.7V. Device operation is not guaranteed at VBAT VBAT +VBATHYS.
9. Specified at +25°C.
10. To ensure proper timekeeping, the VDD SR- specification must be followed.
11. Limits should be considered typical and are not production tested.
12. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification.
13. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
14. Specifications are typical and require using a recommended crystal (see “Application Section” on page 26).
15. Minimum VDD and/or VBAT of 1V to sustain the SRAM. The value is based on characterization and it is not tested.
16. To avoid EEPROM recall issues, it is advised to use this minimum power up slew rate. Not tested, shown as typical only.
FN6659 Rev.3.01
Oct 24, 2019
Page 7 of 32
ISL12022
SDA vs SCL Timing
tHIGH
tF
SCL
tLOW
tR
tSU:DAT
tSU:STA
tHD:DAT
tHD:STA
SDA
(INPUT TIMING)
tSU:STO
tAA
tDH
tBUF
SDA
(OUTPUT TIMING)
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be steady
Will be steady
May change
from LO W
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LO W
Will change
from HIGH
to LOW
Don’t Care:
Changes Allowed
Changing:
State Not Known
N/A
Center Line is
High Impedance
EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR VDD = 5V
5.0V
1533
SDA
AND
IRQ/FOUT
FOR VOL= 0.4V
AND IOL = 3mA
100pF
FIGURE 2. STANDARD OUTPUT LOAD FOR TESTING THE DEVICE
WITH VDD = 5.0V
FN6659 Rev.3.01
Oct 24, 2019
Page 8 of 32
ISL12022
Temperature is +25°C unless otherwise specified.
1050
1600
1000
1400
950
1200
IBAT (nA)
VBAT CURRENT (nA)
Typical Performance Curves
900
VBAT = 5.5V
1000
VBAT = 3.0V
850
800
800
1.8
600
-40
VBAT = 1.8V
2.3
2.8
3.3
3.8
4.3
4.8
5.3
-20
VBAT VOLTAGE (V)
0
20
40
60
80
TEMPERATURE (°C)
FIGURE 4. IBAT vs TEMPERATURE
FIGURE 3. IBAT vs VBAT
6
4.4
4.2
4.0
VDD = 5.5V
IDD1 (µA)
IDD1 (µA)
5
4
VDD = 2.7V
3
3.8
3.6
3.4
VDD = 3.3V
3.2
2
-40
-20
0
20
40
TEMPERATURE (°C)
60
3.0
2.7
80
3.2
SUPPLY CURRENT (µA)
IDD (µA)
5.2
5.5
VDD = 5.5V
4
2
0.01
4.7
FIGURE 6. IDD1 vs VDD
6
3
4.2
VDD (V)
FIGURE 5. IDD1 vs TEMPERATURE
5
3.7
VDD = 3.3V
0.1
VDD = 2.7V
1
10
100
1k
FREQUENCY OUTPUT (Hz)
FIGURE 7. FOUT vs IDD
FN6659 Rev.3.01
Oct 24, 2019
10k
100k
5.0
FOUT = 32kHz
4.5
4.0
FOUT = 1Hz and 64Hz
3.5
3.0
2.5
-40
-20
0
20
40
TEMPERATURE (°C)
60
80
FIGURE 8. IDD vs TEMPERATURE, 3 DIFFERENT FOUT
Page 9 of 32
ISL12022
Typical Performance Curves
110
110
100
100
90
VDD = 5.5V
VDD = 2.7V
70
VDD = 3.3V
60
70
60
VBAT = 3.0V
50
VBAT = 1.8V
40
50
40
-40
VBAT = 5.5V
80
80
IBAT (µA)
90
IDD (µA)
Temperature is +25°C unless otherwise specified. (Continued)
30
-20
0
20
40
60
20
80
TEMPERATURE (°C)
-40
-20
0
20
40
TEMPERATURE (°C)
General Description
Pin Descriptions
The ISL12022 device is a low power real time clock (RTCs) with
embedded temperature sensors. It contains crystal frequency
compensation circuitry over the operating temperature range,
clock/calendar, power fail and low battery monitors, brownout
indicator, 1 periodic or polled alarm, intelligent battery-backup
switching and 128 Bytes of battery-backed user SRAM.
X1, X2
The X1 and X2 pins are the input and output, respectively, of an
inverting amplifier. An external 32.768kHz quartz crystal is used
with the device to supply a timebase for the real time clock.
Internal compensation circuitry with internal temperature sensor
provides frequency corrections for selected popular crystals to
±5ppm over the operating temperature range from -40°C to
+85°C. (See “Application Section” on page 26 for recommended
crystal). The ISL12022 allows the user to input via I2C serial bus
the temperature variation profile of an individual crystal. The
oscillator compensation network can also be used to calibrate
the initial crystal timing accuracy to less than 1ppm error at
room temperature. The device can also be driven directly from a
32.768kHz source at pin X1.
The ISL12022’s alarm can be set to any clock/calendar value for
a match, for example, every minute, every Tuesday or at 5:23 AM
on March 21. The alarm status is available by checking the
Status Register, or the device can be configured to provide a
hardware interrupt via the IRQ/FOUT pin. There is a repeat mode
for the alarm allowing a periodic interrupt every minute, every
hour, every day, etc.
The device also offers a backup power input pin. This VBAT pin
allows the device to be backed up by battery or super capacitor
with automatic switchover from VDD to VBAT. The ISL12022
device is specified for VDD = 2.7V to 5.5V and the clock/calendar
portion of the device remains fully operational in battery-backup
mode down to 1.8V (Standby Mode). The VBAT level is monitored
and reported against preselected levels. The first report is
registered when the VBAT level falls below 85% of nominal level,
the second level is set for 75%. Battery levels are stored in
PWR_VBAT registers.
The ISL12022 offers a “Brownout” alarm once the VDD falls
below a pre-selected trip level. This allows system Micro to save
vital information to memory before complete power loss. There
are six VDD levels that could be selected for initiation of the
Brownout alarm.
FN6659 Rev.3.01
Oct 24, 2019
80
FIGURE 10. IBAT with TSE = 1, BTSE = 1 vs TEMPERATURE
FIGURE 9. IDD WITH TSE = 1 vs TEMPERATURE
The oscillator uses an external, low cost 32.768kHz crystal. The
real time clock tracks time with separate registers for hours,
minutes and seconds. The device has calendar registers for date,
month, year and day of the week. The calendar is accurate
through 2099, with automatic leap year correction. In addition,
the ISL12022 can be programmed for automatic Daylight
Savings Time (DST) adjustment by entering local DST
information.
60
X1
X2
FIGURE 11. RECOMMENDED CRYSTAL CONNECTION
VBAT
This input provides a backup supply voltage to the device. VBAT
supplies power to the device in the event that the VDD supply
fails. Device power will automatically switch to the VBAT input
when VDD drops below the switchover trip level (VTRIP). This pin
can be connected to a battery, a super capacitor or tied to ground
if not used.
IRQ/FOUT (Interrupt Output/Frequency
Output)
This dual function pin can be used as an interrupt or frequency
output pin. The IRQ/FOUT mode is selected via the frequency out
control bits of the control/status register. It is an open drain
output.
Page 10 of 32
ISL12022
• Interrupt Mode. The pin provides an interrupt signal output.
This signal notifies a host processor that an alarm has
occurred and requests action. It is an active low output.
• Frequency Output Mode. The pin outputs a clock signal, which
is related to the crystal frequency. The frequency is user
selectable and enabled via the I2C bus.
Serial Clock (SCL)
The SCL input is used to clock all serial data into and out of the
device. The input buffer on this pin is always active (not gated). It
is disabled when the backup power supply on the VBAT pin is
activated to minimize power consumption.
Serial Data (SDA)
SDA is a bi-directional pin used to transfer data into and out of
the device. It has an open drain output and may be ORed with
other open drain or open collector outputs. The input buffer is
always active (not gated) in normal mode.
An open drain output requires the use of a pull-up resistor. The
output circuitry controls the fall time of the output signal with the
use of a slope controlled pull-down. The circuit is designed for
400kHz I2C interface speeds. It is disabled when the backup
power supply on the VBAT pin is activated.
Condition 1:
VDD > VBAT + VBATHYS
where VBATHYS 50mV
Condition 2:
VDD > V TRIP + V TRIPHYS
where V TRIPHYS 30mV
These power control situations are illustrated in Figures 12
and 13.
BATTERY-BACKUP
MODE
VDD
VTRIP
2.2V
VBAT
1.8V
FIGURE 12. BATTERY SWITCHOVER WHEN VBAT < V TRIP
VDD, GND
Chip power supply and ground pins. The device will operate with
a power supply from VDD = 2.7V to 5.5VDC. A 0.1µF capacitor is
recommended on the VDD pin to ground. The VDD Negative and
VDD Positive Slew Rate specifications have to be observed.
Functional Description
Power Control Operation
The power control circuit accepts a VDD and a VBAT input. Many
types of batteries can be used with Intersil RTC products. For
example, 3.0V or 3.6V Lithium batteries are appropriate, and
battery sizes are available that can power the ISL12022 for up to
10 years. Another option is to use a super capacitor for
applications where VDD is interrupted for up to a month. See the
“Application Section” on page 26 for more information.
Normal Mode (VDD) to Battery-Backup Mode
(VBAT)
To transition from the VDD to VBAT mode, both of the following
conditions must be met:
Condition 1:
VDD < VBAT - VBATHYS
where VBATHYS 50mV
Condition 2:
VDD < V TRIP
where VTRIP 2.2V
Battery-Backup Mode (VBAT) to Normal Mode
(VDD)
VBAT + VBATHYS
VBAT - VBATHYS
BATTERY-BACKUP
MODE
VDD
VBAT
3.0V
VTRIP
2.2V
VTRIP
VTRIP + VTRIPHYS
FIGURE 13. BATTERY SWITCHOVER WHEN VBAT > V TRIP
The I2C bus is deactivated in battery-backup mode to reduce
power consumption. Aside from this, all RTC functions are
operational during battery-backup mode. Except for SCL and SDA,
all the inputs and outputs of the ISL12022 are active during
battery-backup mode unless disabled via the control register.
The device Time Stamps the switchover from VDD to VBAT and
VBAT to VDD, and the time is stored in tSV2B and tSB2V registers
respectively. If multiple VDD power-down sequences occur before
status is read, the earliest VDD to VBAT power-down time is stored
and the most recent VBAT to VDD time is stored.
Temperature conversion and compensation can be enabled in
battery-backup mode. Bit BTSE in the BETA register controls this
operation, as described in “BETA Register (BETA)” on page 19.
Power Failure Detection
The ISL12022 provides a Real Time Clock Failure Bit (RTCF) to
detect total power failure. It allows users to determine if the
device has powered up after having lost all power to the device
(both VDD and VBAT).
The ISL12022 device will switch from the VBAT to VDD mode
when one of the following conditions occurs:
FN6659 Rev.3.01
Oct 24, 2019
Page 11 of 32
ISL12022
Brownout Detection
The ISL12022 monitors the VDD level continuously and provides
warning if the VDD level drops below prescribed levels. There are
six (6) levels that can be selected for the trip level. These values
are 85% below popular VDD levels. The LVDD bit in the Status
Register will be set to “1” when brownout is detected. Note that
the I2C serial bus remains active unless the Battery V TRIP levels
are reached.
Battery Level Monitor
The ISL12022 has a built in warning feature once the Back-up
battery level drops first to 85% and then to 75% of the battery’s
nominal VBAT level. When the battery voltage drops to between
85% and 75%, the LBAT85 bit is set in the status register. When
the level drops below 75%, both LBAT85 and LBAT75 bits are set
in the status register.
The battery level monitor is not functional in battery backup
mode. In order to read the monitor bits after powering up VDD,
instigate a battery level measurement by setting the TSE bit to
"1" (BETA register), and then read the bits.
There is a Battery Time Stamp Function available. Once the VDD
is low enough to enable switchover to the battery, the RTC
time/date are written into the TSV2B register. This information
can be read from the TSV2B registers to discover the point in
time of the VDD power-down. If there are multiple power-down
cycles before reading these registers, the first values stored in
these registers will be retained. These registers will hold the
original power-down value until they are cleared by setting CLRTS
= 1 to clear the registers.
The normal power switching of the ISL12022 is designed to
switch into battery-backup mode only if the VDD power is lost.
This will ensure that the device can accept a wide range of
backup voltages from many types of sources while reliably
switching into backup mode.
when the frequency output function is enabled, the alarm
function is disabled.
The standard alarm allows for alarms of time, date, day of the
week, month, and year. When a time alarm occurs in single
event mode, the IRQ/FOUT pin will be pulled low and the alarm
status bit (ALM) will be set to “1”.
The pulsed interrupt mode allows for repetitive or recurring alarm
functionality. Hence, once the alarm is set, the device will
continue to alarm for each occurring match of the alarm and
present time. Thus, it will alarm as often as every minute (if only
the nth second is set) or as infrequently as once a year (if at least
the nth month is set). During pulsed interrupt mode, the
IRQ/FOUT pin will be pulled low for 250ms and the alarm status
bit (ALM) will be set to “1”.
The ALM bit can be reset by the user or cleared automatically
using the auto reset mode (see ARST bit). The alarm function can
be enabled/disabled during battery-backup mode using the
FOBATB bit. For more information on the alarm, please see
“ALARM Registers (10h to 15h)” on page 21.
Frequency Output Mode
The ISL12022 has the option to provide a clock output signal
using the IRQ/FOUT open drain output pin. The frequency output
mode is set by using the FO bits to select 15 possible output
frequency values from 1/32Hz to 32kHz. The frequency output
can be enabled/disabled during battery-backup mode using the
FOBATB bit.
General Purpose User SRAM
The ISL12022 provides 128 bytes of user SRAM. The SRAM will
continue to operate in battery-backup mode. However, it should
be noted that the I2C bus is disabled in battery-backup mode.
I2C Serial Interface
Note that the ISL12022 is not guaranteed to operate with
VBAT < 1.8V. If the battery voltage is expected to drop lower than
this minimum, correct operation of the device, especially after a
VDD power-down cycle, is not guaranteed.
The ISL12022 has an I2C serial bus interface that provides
access to the control and status registers and the user SRAM.
The I2C serial interface is compatible with other industry I2C
serial bus protocols using a bi-directional data signal (SDA) and a
clock signal (SCL).
The minimum VBAT to insure SRAM is stable is 1.0V. Below that,
the SRAM may be corrupted when VDD power resumes.
Oscillator Compensation
Real Time Clock Operation
The Real Time Clock (RTC) uses an external 32.768kHz quartz
crystal to maintain an accurate internal representation of
second, minute, hour, day of week, date, month, and year. The
RTC also has leap-year correction. The clock also corrects for
months having fewer than 31 days and has a bit that controls
24-hour or AM/PM format. When the ISL12022 powers up after
the loss of both VDD and VBAT, the clock will not begin
incrementing until at least one byte is written to the clock
register.
Single Event and Interrupt
The ISL12022 provides both initial timing correction and
temperature correction due to variation of the crystal oscillator.
Analog and digital trimming control is provided for initial
adjustment, and a temperature compensation function is
provided to automatically correct for temperature drift of the
crystal. Initial values are preset and recalled on initial power-up
for the Initial AT and DT settings (IATR, IDTR), temperature
coefficient (ALPHA), crystal capacitance (BETA), and the crystal
turn-over temperature (XTO). These initial values are typical of
units available on the market, although the user may program
specific values after testing for best accuracy. The function can
be enabled/disabled at any time and can be used in battery
mode as well.
The alarm mode is enabled via the MSB bit. Choosing single
event or interrupt alarm mode is selected via the IM bit. Note that
FN6659 Rev.3.01
Oct 24, 2019
Page 12 of 32
ISL12022
Register Descriptions
8. Crystal Net PPM Correction, NPPM (2 bytes): 2Ah, 2Bh
The battery-backed registers are accessible following a slave
byte of “1101111x” and reads or writes to addresses [00h:2Fh].
The defined addresses and default values are described in the
Table 1. The battery backed general purpose SRAM has a
different slave address (1010111x), so it is not possible to
read/write that section of memory while accessing the registers.
REGISTER ACCESS
The contents of the registers can be modified by performing a
byte or a page write operation directly to any register address.
The registers are divided into 8 sections. They are:
1. Real Time Clock (7 bytes): Address 00h to 06h.
2. Control and Status (9 bytes): Address 07h to 0Fh.
3. Alarm (6 bytes): Address 10h to 15h.
4. Time Stamp for Battery Status (5 bytes): Address 16h to 1Ah.
5. Time Stamp for VDD Status (5 bytes): Address 1Bh to 1Fh.
6. Daylight Savings Time (8 bytes): 20h to 27h.
9. Crystal Turnover Temperature, XT0 (1 byte): 2Ch
10. Crystal ALPHA at high temperature, ALPHA_H (1 byte): 2Dh
11. Scratch Pad (2 bytes): Address 2Eh and 2Fh
Write capability is allowable into the RTC registers (00h to 06h)
only when the WRTC bit (bit 6 of address 08h) is set to “1”. A
multi-byte read or write operation should be limited to one
section per operation for best RTC time keeping performance.
A register can be read by performing a random read at any
address at any time. This returns the contents of that register
location. Additional registers are read by performing a sequential
read. For the RTC and Alarm registers, the read instruction
latches all clock registers into a buffer, so an update of the clock
does not change the time being read. At the end of a read, the
master supplies a stop condition to end the operation and free
the bus. After a read, the address remains at the previous
address +1 so the user can execute a current address read and
continue reading the next register. When the previous address is
2Fh, the next address will wrap around to 00h.
It is not necessary to set the WRTC bit prior to writing into the
control and status, alarm, and user SRAM registers.
7. TEMP (2 bytes): 28h to 29h
TABLE 1. REGISTER MEMORY MAP
BIT
REG
NAME
7
6
5
4
3
2
1
0
00h
SC
0
SC22
SC21
SC20
SC13
SC12
SC11
SC10
01h
MN
0
MN22
MN21
MN20
MN13
MN12
MN11
MN10
0 to 59
00h
02h
HR
MIL
0
HR21
HR20
HR13
HR12
HR11
HR10
0 to 23
00h
DT
0
0
DT21
DT20
DT13
DT12
DT11
DT10
1 to 31
01h
MO
0
0
0
MO20
MO13
MO12
MO11
MO10
1 to 12
01h
05h
YR
YR23
YR22
YR21
YR20
YR13
YR12
YR11
YR10
0 to 99
00h
06h
DW
0
0
0
0
0
DW2
DW1
DW0
0 to 6
00h
07h
SR
BUSY
OSCF
DSTADJ
ALM
LVDD
LBAT85
LBAT75
RTCF
N/A
01h
08h
INT
ARST
WRTC
IM
FOBATB
FO3
FO2
FO1
FO0
N/A
01h
09h
PWR_VDD
CLRTS
0Ah
PWR_VBAT
ADDR. SECTION
03h
RTC
04h
0Bh
RANGE DEFAULT
0 to 59
00h
D
D
D
D
VDDTrip2
VDDTrip1
VDDTrip0
N/A
00h
RESEALB
VB85Tp2
VB85Tp1
VB85Tp0
VB75Tp2
VB75Tp1
VB75Tp0
N/A
00h
ITRO
IDTR01
IDTR00
IATR05
IATR04
IATR03
IATR02
IATR01
IATR00
N/A
20h
0Ch
ALPHA
D
ALPHA6
ALPHA5
ALPHA4
ALPHA3
ALPHA2
ALPHA1
ALPHA0
N/A
46h
0Dh
BETA
TSE
BTSE
BTSR
BETA4
BETA3
BETA2
BETA1
BETA0
N/A
00h
0Eh
FATR
0
0
FFATR5
FATR4
FATR3
FATR2
FATR1
FATR0
N/A
00h
0Fh
FDTR
0
0
0
FDTR4
FDTR3
FDTR2
FDTR1
FDTR0
N/A
00h
10h
SCA0
ESCA0
SCA022
SCA021
SCA020
SCA013
SCA012
SCA011
SCA010
00 to 59
00h
11h
MNA0
EMNA0
MNA022
MNA021
MNA020
MNA013
MNA012
MNA011
MNA010
00 to 59
00h
12h
HRA0
EHRA0
D
HRA021
HRA020
HRA013
HRA012
HRA011
HRA010
0 to 23
00h
DTA0
EDTA0
D
DTA021
DTA020
DTA013
DTA012
DTA011
DTA010
01 to 31
00h
14h
MOA0
EMOA00
D
D
MOA020
MOA013
MOA012
MOA011
MOA010
01 to 12
00h
15h
DWA0
EDWA0
D
D
D
D
DWA02
DWA01
DWA00
0 to 6
00h
13h
CSR
ALARM
FN6659 Rev.3.01
Oct 24, 2019
Page 13 of 32
ISL12022
TABLE 1. REGISTER MEMORY MAP (Continued)
BIT
REG
NAME
7
6
5
4
3
2
1
0
VSC
0
VSC22
VSC21
VSC20
VSC13
VSC12
VSC11
VSC10
0 to 59
VMN
0
VMN22
VMN21
VMN20
VMN13
VMN12
VMN11
VMN10
0 to 59
00h
VHR
VMIL
0
VHR21
VHR20
VHR13
VHR12
VHR11
VHR10
0 to 23
00h
19h
VDT
0
0
VDT21
VDT20
VDT13
VDT12
VDT11
VDT10
1 to 31
00h
1Ah
VMO
0
0
0
VMO20
VMO13
VMO12
VMO11
VMO10
1 to 12
00h
ADDR. SECTION
16h
17h
18h
TSV2B
RANGE DEFAULT
00h
1Bh
BSC
0
BSC22
BSC21
BSC20
BSC13
BSC12
BSC11
BSC10
0 to 59
00h
1Ch
BMN
0
BMN22
BMN21
BMN20
BMN13
BMN12
BMN11
BMN10
0 to 59
00h
BHR
BMIL
0
BHR21
BHR20
BHR13
BHR12
BHR11
BHR10
0 to 23
00h
BDT
0
0
BDT21
BDT20
BDT13
BDT12
BDT11
BDT10
1 to 31
00h
BMO20
BMO13
BMO12
BMO11
BMO10
1 to 12
00h
DstMoFd20 DstMoFd13 DstMoFd12 DstMoFd11 DstMoFd10 1 to 12
00h
1Dh
TSB2V
1Eh
1Fh
BMO
0
0
0
20h
DstMoFd
DSTE
D
D
21h
DstDwFd
D
22h
DstDtFd
D
D
DstDtFd21
23h
DstDwFdE DstWkFd12 DstWkFd11 DstWkFd10 DstDwFd12 DstDwFd11 DstDwFd10
DstHrFd
D
D
DstHrFd21
DstMoRv
D
D
D
25h
DstDwRv
D
26h
DstDtRv
D
27h
DstHrRv
28h
TK0L
TK0M
NPPML
24h
29h
2Ah
2Bh
DSTCR
TEMP
NPPM
0 to 6
00h
DstDtFd20
DstDtFd13 DstDtFd12 DstDtFd11 DstDtFd10
1 to 31
00h
DstHrFd20
DstHrFd13
0 to 23
00h
XDstMoRv20 DstMoRv13 DstMoR12v DstMoRv11 DstMoRv10 01 to 12
00h
DstHrFd12 DstHrFd11 DstHrFd10
DstDwRvE DstWkrv12 DstWkRv11 DstWkRv10 DstDwRv12 DstDwRv11 DstDwRv10
0 to 6
00h
D
DstDtRv21
DstDtRv20
DstDtRv13 DstDtRv12 DstDtRv11 DstDtRv10 01 to 31
00h
D
D
DstHrRv21
DstHrRv20
DstHrRv13 DstHrRv12 DstHrRv11 DstHrRv10
0 to 23
00h
TK07
TK06
TK05
TK04
TK03
TK02
TK01
TK00
00 to FF
00h
0
0
0
0
0
0
TK09
TK08
00 to 03
00h
NPPM7
NPPM6
NPPM5
NPPM4
NPPM3
NPPM2
NPPM1
NPPM0
00 to FF
00h
NPPMH
0
0
0
0
0
NPPM10
NPPM9
NPPM8
00 to 07
00h
2Ch
XT0
XT0
D
D
D
XT4
XT3
XT2
XT1
XT0
00 to FF
00h
2Dh
ALPHAH
ALPHAH
D
ALP_H6
ALP_H5
ALP_H4
ALP_H3
ALP_H2
ALP_H1
ALP_H0
00 to 7F
46h
GPM1
GPM17
GPM16
GPM15
GPM14
GPM13
GPM12
GPM11
GPM10
00 to FF
00h
GPM2
GPM27
GPM26
GPM25
GPM24
GPM23
GPM22
GPM21
GPM20
00 to FF
00h
2Eh
2Fh
GPM
FN6659 Rev.3.01
Oct 24, 2019
Page 14 of 32
ISL12022
Real Time Clock Registers
OSCILLATOR FAIL BIT (OSCF)
Oscillator Fail Bit indicates that the oscillator has failed. The
oscillator frequency is either zero or very far from the desired
32.768kHz due to failure, PC board contamination or mechanical
issues.
Addresses [00h to 06h]
RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW)
These registers depict BCD representations of the time. As such,
SC (Seconds) and MN (Minutes) range from 0 to 59, HR (Hour)
can either be a 12-hour or 24-hour mode, DT (Date) is 1 to 31,
MO (Month) is 1 to 12, YR (Year) is 0 to 99, and DW (Day of the
Week) is 0 to 6.
The DW register provides a Day of the Week status and uses three
bits DW2 to DW0 to represent the seven days of the week. The
counter advances in the cycle 0-1-2-3-4-5-6-0-1-2-…
The assignment of a numerical value to a specific day of the
week is arbitrary and may be decided by the system software
designer. The default value is defined as “0”.
24 HOUR TIME
If the MIL bit of the HR register is “1”, the RTC uses a
24-hour format. If the MIL bit is “0”, the RTC uses a 12-hour
format and HR21 bit functions as an AM/PM indicator with a “1”
representing PM. The clock defaults to 12-hour format time with
HR21 = “0”.
LEAP YEARS
Leap years add the day February 29 and are defined as those years
that are divisible by 4. Years divisible by 100 are not leap years,
unless they are also divisible by 400. This means that the year 2000
is a leap year and the year 2100 is not. The ISL12022 does not
correct for the leap year in the year 2100.
Addresses [07h to 0Fh]
The Control and Status Registers consist of the Status Register,
Interrupt and Alarm Register, Analog Trimming and Digital
Trimming Registers.
Status Register (SR)
TABLE 2. STATUS REGISTER (SR)
6
07h
BUSY
OSCF
5
4
3
2
1
0
DSTDJ ALM LVDD LBAT85 LBAT75 RTCF
BUSY BIT (BUSY)
Busy Bit indicates temperature sensing is in progress. In this
mode, Alpha, Beta and ITRO registers are disabled and cannot be
accessed.
FN6659 Rev.3.01
Oct 24, 2019
The DSTE bit must be enabled when the RTC time is more than
one hour before the DST Forward or DST Reverse event time
setting, or the DST event correction will not happen.
DSTADJ is reset to “0” upon power-up. It will reset to ”0” when the
DSTE bit in Register 15h is set to “0” (DST disabled), but no time
adjustment will happen.
ALARM BIT (ALM)
This bit announces if the alarm matches the real time clock. If
there is a match, the respective bit is set to “1”. This bit can be
manually reset to “0” by the user or automatically reset by
enabling the auto-reset bit (see ARST bit). A write to this bit in the
SR can only set it to “0”, not “1”. An alarm bit that is set by an
alarm occurring during an SR read operation will remain set after
the read operation is complete.
This bit indicates when VDD has dropped below the pre-selected
trip level (Brownout Mode). The trip points for the brownout levels
are selected by three bits: VDD Trip2, VDD Trip1 and VDD Trip0 in
PWR_ VDD registers. The LVDD detection is only enabled in VDD
mode and the detection happens in real time. The LVDD bit is set
whenever the VDD has dropped below the pre-selected trip level,
and self clears whenever the VDD is above the pre-selected trip
level.
LOW BATTERY INDICATOR 85% BIT (LBAT85)
The Status Register is located in the memory map at address
07h. This is a volatile register that provides either control or
status of RTC failure (RTCF), Battery Level Monitor (LBAT85,
LBAT75), alarm trigger, Daylight Savings Time, crystal oscillator
enable and temperature conversion in progress bit.
7
DSTADJ is the Daylight Savings Time Adjusted Bit. It indicates the
daylight saving time forward adjustment has happened. If a DST
Forward event happens, DSTADJ will be set to “1”. The DSTADJ bit
will stay high after the DSTFD event happens, and will be reset to
“0” when the DST Reverse event happens. It is read-only and
cannot be written. Setting time during a DST forward period will
not set this bit to “1”.
LOW VDD INDICATOR BIT (LVDD)
Control and Status Registers
(CSR)
ADDR
DAYLIGHT SAVINGS TIME CHANGE BIT (DSTADJ)
In Normal Mode (VDD), this bit indicates when the battery level
has dropped below the pre-selected trip levels. The trip points are
selected by three bits: VB85Tp2, VB85Tp1 and VB85Tp0 in the
PWR_VBAT registers. The LBAT85 detection happens
automatically once every minute when seconds register reaches
59. The detection can also be manually triggered by setting the
TSE bit in BETA register to “1”. The LBAT85 bit is set when the
VBAT has dropped below the pre-selected trip level, and will self
clear when the VBAT is above the pre-selected trip level at the
next detection cycle either by manual or automatic trigger.
In Battery Mode (VBAT), this bit indicates the device has entered
into battery mode by polling once every 10 minutes. The LBAT85
detection happens automatically once when the minute register
reaches x9h or x0h minutes.
Page 15 of 32
ISL12022
Example - When the LBAT85 is Set To “1” In Battery Mode:
The minute the register changes to 19h when the device is in
battery mode, the LBAT85 is set to “1” the next time the device
switches back to Normal Mode.
ARST is cleared to “0”, the user must manually reset the ALM,
LVDD, LBAT85, and LBAT75 bits.
WRITE RTC ENABLE BIT (WRTC)
If the device enters into battery mode after the minute register
reaches 20h and switches back to Normal Mode before the
minute register reaches 29h, then the LBAT85 bit will remain at
“0” the next time the device switches back to Normal Mode.
The WRTC bit enables or disables write capability into the RTC
Timing Registers. The factory default setting of this bit is “0”.
Upon initialization or power-up, the WRTC must be set to “1” to
enable the RTC. Upon the completion of a valid write (STOP), the
RTC starts counting. The RTC internal 1Hz signal is synchronized
to the STOP condition during a valid write cycle.
LOW BATTERY INDICATOR 75% BIT (LBAT75)
INTERRUPT/ALARM MODE BIT (IM)
In Normal Mode (VDD), this bit indicates when the battery level
has dropped below the pre-selected trip levels. The trip points are
selected by three bits: VB75Tp2, VB75Tp1 and VB75Tp0 in the
PWR_VBAT registers. The LBAT75 detection happens
automatically once every minute when seconds register reaches
59. The detection can also be manually triggered by setting the
TSE bit in BETA register to “1”. The LBAT75 bit is set when the
VBAT has dropped below the pre-selected trip level, and will self
clear when the VBAT is above the pre-selected trip level at the
next detection cycle either by manual or automatic trigger.
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarm will operate in
the interrupt mode, where an active low pulse width of 250ms
will appear at the IRQ/FOUT pin when the RTC is triggered by the
alarm, as defined by the alarm registers (0Ch to 11h). When the
IM bit is cleared to “0”, the alarm will operate in standard mode,
where the IRQ/FOUT pin will be set low until the ALM status bit is
cleared to “0”.
Example - When the LBAT85 Remains at “0” In Battery Mode:
In Battery Mode (VBAT), this bit indicates the device has entered
into battery mode by polling once every 10 minutes. The LBAT85
detection happens automatically once when the minute register
reaches x9h or x0h minutes.
TABLE 4.
IM BIT
INTERRUPT/ALARM FREQUENCY
0
Single Time Event Set By Alarm
1
Repetitive/Recurring Time Event Set By Alarm
Example - When the LBAT75 is Set to “1” in Battery Mode:
FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)
The minute register changes to 30h when the device is in battery
mode, the LBAT75 is set to “1” the next time the device switches
back to Normal Mode.
This bit enables/disables the IRQ/FOUT pin during
battery-backup mode (i.e., VBAT power source active). When the
FOBATB is set to “1”, the IRQ/FOUT pin is disabled during
battery-backup mode. This means that both the frequency output
and alarm output functions are disabled. When the FOBATB is
cleared to “0”, the IRQ/FOUT pin is enabled during battery-backup
mode. Note that the open drain IRQ/FOUT pin will need a pull-up
to the battery voltage to operate in battery-backup mode.
Example - When the LBAT75 Remains at “0” in Battery Mode:
If the device enters into battery mode after the minute register
reaches 49h and switches back to Normal Mode before minute
register reaches 50h, then the LBAT75 bit will remain at “0” the
next time the device switches back to Normal Mode.
REAL TIME CLOCK FAIL BIT (RTCF)
This bit is set to a “1” after a total power failure. This is a read
only bit that is set by hardware (ISL12022 internally) when the
device powers up after having lost all power (defined as VDD = 0V
and VBAT = 0V). The bit is set regardless of whether VDD or VBAT
is applied first. The loss of only one of the supplies does not set
the RTCF bit to “1”. The first valid write to the RTC section after a
complete power failure resets the RTCF bit to “0” (writing one
byte is sufficient).
Interrupt Control Register (INT)
TABLE 3. INTERRUPT CONTROL REGISTER (INT)
ADDR
7
6
5
4
08h
ARST
WRTC
IM
FOBATB
3
2
1
0
FO3 FO2 FO1 FO0
AUTOMATIC RESET BIT (ARST)
This bit enables/disables the automatic reset of the ALM, LVDD,
LBAT85, and LBAT75 status bits only. When ARST bit is set to “1”,
these status bits are reset to “0” after a valid read of the
respective status register (with a valid STOP condition). When the
FN6659 Rev.3.01
Oct 24, 2019
FREQUENCY OUT CONTROL BITS (FO)
These bits enable/disable the frequency output function and select
the output frequency at the IRQ/FOUT pin. See Table 5 for frequency
selection. Default for the ISL12022 is FO = 1h, or 32.768kHz
output. When the frequency mode is enabled, it will override the
alarm mode at the IRQ/FOUT pin.
TABLE 5. FREQUENCY SELECTION OF IRQ/FOUT PIN
FREQUENCY,
FOUT
UNITS
FO3
FO2
FO1
FO0
0
Hz
0
0
0
0
32768
Hz
0
0
0
1
4096
Hz
0
0
1
0
1024
Hz
0
0
1
1
64
Hz
0
1
0
0
32
Hz
0
1
0
1
16
Hz
0
1
1
0
8
Hz
0
1
1
1
Page 16 of 32
ISL12022
unused. Once VDD is powered up, this bit is reset and the VBAT pin is
then connected to the internal circuitry.
TABLE 5. FREQUENCY SELECTION OF IRQ/FOUT PIN (Continued)
FREQUENCY,
FOUT
UNITS
FO3
FO2
FO1
FO0
4
Hz
1
0
0
0
2
Hz
1
0
0
1
1
Hz
1
0
1
0
1/2
Hz
1
0
1
1
1/4
Hz
1
1
0
0
1/8
Hz
1
1
0
1
1/16
Hz
1
1
1
0
1/32
Hz
1
1
1
1
The application for this bit involves placing the chip on a board
with a battery and testing the board. Once the board is tested
and ready to ship, it is desirable to disconnect the battery to keep
it fresh until the board or unit is placed into final use. Setting
RESEALB = “1” initiates the battery disconnect, and after VDD
power is cycled down and up again, the RESEAL bit is cleared
to “0”.
BATTERY LEVEL MONITOR TRIP BITS (VB85TP)
Three bits select the first alarm (85% of Nominal VBAT) level for the
battery voltage monitor. There are total of 7 levels that could be
selected for the first alarm. Any of the of levels could be selected as
the first alarm with no reference as to nominal Battery voltage level.
See Table 8.
POWER SUPPLY CONTROL REGISTER (PWR_VDD)
TABLE 8. VB85T ALARM LEVEL
Clear Time Stamp Bit (CLRTS)
ADDR
09h
7
6
5
4
3
2
1
0
CLRTS
0
0
0
0
VDDTrip2
VDDTrip1
VDDTrip0
This bit clears Time Stamp VDD to Battery (TSV2B) and Time
Stamp Battery to VDD Registers (TSB2V). The default setting is 0
(CLRTS = 0) and the Enabled setting is 1 (CLRTS = 1).
VDD Brownout Trip Voltage BITS (VDDTrip 2.7V.
Note that the device is not guaranteed to operate with a
VBAT < 1.8V, so the battery should be changed before
S
T IDENTIFICATION
A
BYTE WITH
R
R/W = 1
T
ADDRESS
BYTE
A
C
K
S
T
O
P
A
C
K
1 1 0 1 1 1 1 1
1 1 0 1 1 1 1 0
A
C
K
A
C
K
A
C
K
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 19. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN)
FN6659 Rev.3.01
Oct 24, 2019
Page 26 of 32
ISL12022
discharging to that level. It is strongly advised to monitor the low
battery indicators in the status registers and take action to
replace discharged batteries.
If a supercapacitor is used, it is possible that it may discharge to
below 1.8V during prolonged power-down. Once powered up, the
device may lose serial bus communications until both VDD and VBAT
are powered down together. To avoid that situation, including
situations where a battery may discharge deeply, the circuit in
Figure 20 can be used.
VDD = 2.7V
TO 5.5V
ISL12022
VDD
JBAT
DBAT
BAT43W
VBAT
CIN
0.1µF
CBAT
0.1µF
+ VBAT = 1.8V
TO 3.2V
GND
FIGURE 20. SUGGESTED BATTERY-BACKUP CIRCUIT
The diode, DBAT will add a small drop to the battery voltage but
will protect the circuit should battery voltage drop below 1.8V.
The jumper is added as a safeguard should the battery ever need
to be disconnect from the circuit.
The VDD negative slew rate should be limited to below the data
sheet spec (10V/ms) otherwise battery switchover can be
delayed, resulting in SRAM contents corruption and oscillator
operation interruption.
Some applications will require separate supplies for the RTC VDD
and the I2C pull-ups. This is not advised, as it may compromise
the operation of the I2C bus. For applications that do require
serial bus communication with the RTC VDD powered down, the
SDA pin must be pulled low during the time the RTC VDD ramps
down to 0V. Otherwise, the device may lose serial bus
communications once VDD is powered up, and will return to
normal operation ONLY once VDD and VBAT are both powered
down together.
TABLE 26. SUGGESTED SURFACE MOUNT CRYSTALS
MANUFACTURER
PART NUMBER
Citizen
CM200S
Epson
MC-405, MC-406
Raltron
RSM-200S
SaRonix
32S12
Ecliptek
ECPSM29T-32.768K
ECS
ECX-306
Fox
FSM-327
Layout Considerations
The crystal input at X1 has a very high impedance, and oscillator
circuits operating at low frequencies (such as 32.768kHz) are
known to pick up noise very easily if layout precautions are not
followed. Most instances of erratic clocking or large accuracy errors
can be traced to the susceptibility of the oscillator circuit to
interference from adjacent high speed clock or data lines. Careful
layout of the RTC circuit will avoid noise pickup and insure accurate
clocking.
Figure 21 shows a suggested layout for the ISL12022 device using
a surface mount crystal. Two main precautions should be followed:
• Do not run the serial bus lines or any high speed logic lines in
the vicinity of the crystal. These logic level lines can induce noise
in the oscillator circuit, causing misclocking.
• Add a ground trace around the crystal with one end terminated
at the chip ground. This will provide termination for emitted
noise in the vicinity of the RTC device.
Oscillator Crystal Requirements
The ISL12022 uses a standard 32.768kHz crystal. Either through
hole or surface mount crystals can be used. Table 26 lists some
recommended surface mount crystals and the parameters of each.
This list is not exhaustive and other surface mount devices can be
used with the ISL12022 if their specifications are very similar to the
devices listed. The crystal should have a required parallel load
capacitance of 12.5pF and an equivalent series resistance of less
than 50k. The crystal’s temperature range specification should
match the application. Many crystals are rated for -10°C to +60°C
(especially through-hole and tuning fork types), so an appropriate
crystal should be selected if extended temperature range is
required.
FN6659 Rev.3.01
Oct 24, 2019
FIGURE 21. SUGGESTED LAYOUT FOR ISL12022 AND CRYSTAL
In addition, it is a good idea to avoid a ground plane under the X1
and X2 pins and the crystal, as this will affect the load
capacitance and therefore the oscillator accuracy of the circuit. If
the ~IRQ/FOUT pin is used as a clock, it should be routed away
from the RTC device as well. The traces for the VBAT and VDD pins
can be treated as a ground, and should be routed around the
crystal.
Page 27 of 32
ISL12022
Applications Information
Crystal Oscillator Frequency Compensation
CRYSTAL CHARACTERISTICS
The ISL12022 device contains a complete system for adjusting
the frequency of the crystal oscillator to compensate for
temperature variation. A typical 32.768kHz crystal used with RTC
devices has a temperature versus frequency curve, as shown in
Figure 22.
The Digital Trimming (DT) uses clock pulse add/subtract logic to
change the RTC timing during temperature compensation. The
DT steps are much coarser than the AT steps and are therefore
used for large adjustments. The DT steps are 30.5ppm, and the
range is from -305ppm to +305ppm. The Frequency Output
function will show the clock variation with DT settings, except for
the 32,768Hz setting which only shows the AT control.
0
-20
-40
PPM
-60
-80
ACTIVE TEMPERATURE COMPENSATION
-100
The ISL12022 contains an intelligent logic circuit which takes the
temperature sensor digital value as the only input variable. It
then uses the register values for the crystal variables and T0,
and combines those with calibration from the BETA and ITR0
registers to produce “Final” values for the AT and DT, known as
FATR (Final AT Register) and FDTR (Final DT Register). Those AT
and DT values combine to directly compensate for the
temperature error shown in Figure 22.
-120
-140
-160
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
TEMPERATURE (°C)
FIGURE 22. RTC CRYSTAL TEMPERATURE DRIFT
The curve in Figure 22 follows Equation 7:
f = T – T 0
Normally, the crystal frequency is adjusted at room temperature
to zero out the frequency error using the IATRxx register bits
(initial Analog Trimming). In addition, the IATRxx setting is varied
up and down to record the variation in oscillator frequency
compared to the step change in IATRxx. Once that value is known
then the BETA register is used to adjust the step size to be as
close to 1ppm per IATRxx step as possible. After that adjustment
is made, then any ISL12022 temperature compensation
adjustments will use a 1ppm change for each bit change in the
internal AT adjustment.
2
(EQ. 7)
Where is the temperature constant, with a typical value of
0.034 ppm/°C.
T0 is the turnover temperature of the crystal, which is the apex of
the parabolic curve. If the two factors and T0 are known, it is
possible to correct for crystal temperature error to very high
accuracy.
The crystal will have an initial accuracy error at room temperature,
typically specified at ±20°C. The other important characteristic is
the capacitances associated with the crystal. The load capacitance
is normally specified at 12.5pF, although it can be lower in some
cases. There is also a motional capacitance which affects the
ability of the load capacitance to pull the oscillation frequency, and
it is usually in the range of 2.2fF to 4.0fF.
RTC CLOCK CONTROL
The ISL12022 uses two mechanisms to adjust the RTC clock and
correct for the temperature error of the external crystal.
The Analog Trimming (AT) adjusts the load capacitance seen by
the crystal. Analog switches connect the appropriate capacitance
to change the frequency in increments of 1ppm. The adjustment
range for the ISL12022 is +32/-31ppm.
The AT can be further refined using the BETA register. the BETA
register function is to allow for changes in CM (motional
capacitance) which will affect the incremental frequency change
of the AT adjustment. A simple test procedure uses the BETA
register to bring the step size back to 1ppm.
FN6659 Rev.3.01
Oct 24, 2019
The temperature sensor produces a new value every 60s (or up to
10 minutes in battery mode), which triggers the logic to calculate
a new AT/DT value set. For every temperature calculation result,
there can only be one corresponding AT/DT correction value.
Measuring Oscillator Accuracy
The best way to analyze the ISL12022 frequency accuracy is to
set the IRQ/FOUT pin for a specific frequency, and look at the
output of that pin on a high accuracy frequency counter (at least
7 digits accuracy). Note that the IRQ/FOUT is a drain output and
will require a pull-up resistor.
Using the 1.0Hz output frequency is the most convenient as the
ppm error is as expressed in Equation 8:
ppm error = F OUT – 1 1e6
(EQ. 8)
Other frequencies may be used for measurement but the error
calculation becomes more complex.
When the proper layout guidelines are observed, the oscillator
should start up in most circuits in less than 1s. When testing RTC
circuits, a common impulse is to apply a scope probe to the circuit
at the X2 pin (oscillator output) and observe the waveform. DO
NOT DO THIS! Although in some cases you may see a usable
waveform, due to the parasitics (usually 10pF to ground) applied
with the scope probe, there will be no useful information in that
waveform other than the fact that the circuit is oscillating. The X2
output is sensitive to capacitive impedance so the voltage levels
and the frequency will be affected by the parasitic elements in the
scope probe. Use the FOUT output and a frequency counter for the
most accurate results.
Page 28 of 32
ISL12022
Temperature Compensation Operation
The ISL12022 temperature compensation feature needs to be
enabled by the user. This must be done in a specific order as
follows.
1. Read register 0Dh, the BETA register. This register contains the
5-bit BETA trimmed value which is automatically loaded on initial
power-up. Mask off the 5LSB’s of the value just read.
2. Bit 7 of the BETA register is the master enable control for
temperature sense operation. Set this to “1” to allow
continuous temperature frequency correction. Frequency
correction will then happen every 60s with VDD applied.
3. Bits 5 and 6 of the BETA register control temperature
compensation in battery-backup mode (see Table 15). Set the
values for the operation desired.
4. Write back to register 0Dh making sure not to change the 5
LSB values, and include the desired compensation control bits.
Note that every time the BETA register is written with the TSE
bit = 1, a temperature compensation cycle is instigated and a
new correction value will be loaded into the FATR/FDTR registers
(if the temperature changed since the last conversion).
Also note that registers 0Bh and 0Ch, the ITR0 and ALPHA
registers, should not be changed. If they must be written be sure
to write the same values that are recalled from initial power-up.
The ITR0 register may be written if the user wishes to re-calibrate
the oscillator frequency at room temperature for aging or board
mounting. The original recalled value can be re-written if desired
after testing.
For further information on the operation of the ISL12022 and
temperature compensated RTC’s, see Intersil Application Note
AN1389, “Using Intersil’s High Accuracy Real Time Clock
Module”.
Daylight Savings Time (DST) Example
DST involves setting the forward and back times and allowing the
RTC device to automatically advance the time or set the time back.
This can be done for current year, and future years. Many regions
have DST rules that use standard months, weeks and time of the
day which permit a pre-programmed, permanent setting.
Table 27 shows the example setup for the ISL12022.
TABLE 27. DST EXAMPLE
VARIABLE
Month Forward and DST Enable
VALUE
REGISTER VALUE
April
15h
84h
Week and Day Forward and select 1st Week and
Day/Week, not Date
Sunday
16h
48h
Date Forward
not used
17h
00h
Hour Forward
2am
18h
02h
Month Reverse
October
19h
10h
Week and Day Reverse and select Last Week and 1Ah
Day/Week, not Date
Sunday
78h
Date Reverse
not used
1Bh
00h
Hour Reverse
2am
1Ch
02h
The Enable bit (DSTE) is in the Month forward register, so the BCD
value for that register is altered with the additional bit. The Week
and Day values along with Week/Day vs Date select bit is in the
Week/Day register, so that value is also not straight BCD. Hour
and Month are normal BCD, but the Hour doesn’t use the MIL bit
since Military time PM values are already discretely different
from AM/PM time PM values. The DST reverse setting utilizes the
option to select the last week of the month for October, which
could have 4 or 5 weeks but needs to have the time change on
the last Sunday.
Note that the DSTADJ bit in the status register monitors whether
the DST forward adjustment has happened. When it is “1”, DST
forward has taken place. When it is “0”, then either DST reverse
has happened, or it has been reset either by initial power-up or if
the DSTE bit has been set to “0”.
FN6659 Rev.3.01
Oct 24, 2019
Page 29 of 32
ISL12022
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure
you have the latest revision.
DATE
REVISION
Oct 24, 2019
FN6659.3.01
FN6659 Rev.3.01
Oct 24, 2019
CHANGE
Updated links throughout.
Added Related Literature section.
Updated Ordering information by adding tape and reel information and updating notes.
Updated labels on Figures 5 and 9.
Added Revision History
Updated POD M8.15 to latest revision changes are as follows:
-Updated Note 1 changed 1982 to 1994.
Updated Disclaimer.
Page 30 of 32
ISL12022
Package Outline Drawing
For the most recent package outline drawing, see M8.15.
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
6.20 (0.244)
5.80 (0.228)
AREA
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
1
2
8°
0°
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
SEATING PLANE
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
1
8
2
7
0.60 (0.023)
1.27 (0.050)
3
6
4
5
-C-
1.27 (0.050)
0.51(0.020)
0.33(0.013)
SIDE VIEW “A
0.25(0.010)
0.10(0.004)
5.20(0.205)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
17. Dimensioning and tolerancing per ANSI Y14.5M-1994.
18. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
19. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
20. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
21. Terminal numbers are shown for reference only.
22. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
23. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
24. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
FN6659 Rev.3.01
Oct 24, 2019
Page 31 of 32
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