DATASHEET
ISL12024
FN6370
Rev 3.00
August 18, 2008
Real-Time Clock/Calendar with Embedded Unique ID
The ISL12024 device is a micro-power real-time clock with
embedded 64-bit unique ID, timing and crystal
compensation, clock/calender, power-fail indicator, two
periodic or polled alarms, intelligent battery backup
switching, and integrated 512x8-bit EEPROM configured in
16 Bytes per page.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real-time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
Ordering Information
PART
NUMBER
(Note)
TEMP
RANGE
PART
VDD
(°C)
MARKING RANGE
PACKAGE PKG.
(Pb-free) DWG. #
ISL12024IBZ* 12024 IBZ 2.7V to -40 to +85 8 Ld SOIC
5.5V
ISL12024IVZ* 2024 IVZ
M8.15
2.7V to -40 to +85 8 Ld TSSOP M8.173
5.5V
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish,
which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
Pinouts
ISL12024
(8 LD SOIC)
TOP VIEW
Features
• Real-Time Clock/Calendar
- Tracks Time in Hours, Minutes, and Seconds
- Day of the Week, Day, Month and Year
- 3 Selectable Frequency Outputs
• 64-bit Unique ID
• Two Non-Volatile Alarms
- Settable on the Second, Minute, Hour, Day of the Week,
Day or Month
- Repeat Mode (Periodic Interrupts)
• Automatic Backup to Battery or Super Cap
• On-Chip Oscillator Compensation
- Internal Feedback Resistor and Compensation
Capacitors
- 64 Position Digitally Controlled Trim Capacitor
- 6 Digital Frequency Adjustment Settings to ±30ppm
• 512x8-Bits of EEPROM
- 16-Bytes Page Write Mode (32 total pages)
- 8 Modes of BlockLock™ Protection
- Single Byte Write Capability
• High Reliability
- Data Retention: 50 years
- Endurance: 2,000,000 Cycles Per Byte
• I2C Bus™
- 400kHz Data Transfer Rate
• 800nA Battery Supply Current
• Package Options
- 8 Ld SOIC and 8 Ld TSSOP Packages
- Pin-Compatible with the ISL12026
• Pb-Free (RoHS Compliant)
Applications
X1
1
8
VDD
X2
2
7
VBAT
IRQ/FOUT
3
6
SCL
GND
4
5
SDA
• Utility Meters
• Audio Video Equipment
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
ISL12024
(8 LD TSSOP)
TOP VIEW
• Fixed Broadband Wireless Equipment
• Pagers/PDA
VBAT
1
8
SCL
VDD
2
7
SDA
• POS Equipment
X1
3
6
GND
• Test Meters/Fixtures
X2
4
5
IRQ/FOUT
• Office Automation (Copiers, Fax)
• Computer Products
• Security Related Application
FN6370 Rev 3.00
August 18, 2008
Page 1 of 25
ISL12024
Block Diagram
OSC
COMPENSATION
X1
OSCILLATOR
X2
IRQ/FOUT
SELECT
SCL
SERIAL
INTERFACE
DECODER
SDA
CONTROL
DECODE
LOGIC
CONTROL/
REGISTERS
(EEPROM)
8
TIMER
FREQUENCY 1Hz
CALENDAR
DIVIDER
LOGIC
STATUS
REGISTERS
(SRAM)
TIME
KEEPING
REGISTERS
(SRAM)
BATTERY
SWITCH
CIRCUITRY
VDD
VBAT
COMPARE
ALARM
MASK
32.768kHz
ALARM REGS
(EEPROM)
4k
EEPROM
ARRAY
Pin Descriptions
PIN NUMBER
SOIC
TSSOP
SYMBOL
DESCRIPTION
1
3
X1
The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external
32.768kHz quartz crystal. X1 can also be driven directly from a 32.768kHz source. (See “Application Section”
on page 20.)
2
4
X2
The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external
32.768kHz quartz crystal. (See “Application Section” on page 20.)
3
5
IRQ/FOUT
4
6
GND
Ground.
5
7
SDA
Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an
open drain output and may be wire OR’ed with other open drain or open collector outputs.
6
8
SCL
The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on
this pin is always active (not gated).
7
1
VBAT
This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event
that the VDD supply fails. This pin should be tied to ground if not used.
8
2
VDD
Power Supply.
FN6370 Rev 3.00
August 18, 2008
Interrupt Output/Frequency Output is a multi-functional pin that can be used as interrupt or frequency
output pin. The function is set via the control register. This output is an open drain configuration.
Page 2 of 25
ISL12024
Absolute Maximum Ratings
Thermal Information
Voltage on VDD, VBAT, SCL, SDA, and IRQ/FOUT Pins
(respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on X1 and X2 Pins
(respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V
Latchup (Note 1) . . . . . . . . . . . . . . . . . . . Class II, Level B @ +85°C
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175V
Thermal Resistance (Typical, Note 2)
JA°C/W
8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . .
120
8 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . .
140
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: Using a max positive pulse of 8.35V on all pins except X1 and
X2, Using a max positive pulse of 2.75V on X1 and X2, and using a max negative pulse of -1V for all pins.
2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Operating Specifications
SYMBOL
Unless otherwise noted, VDD = +2.7V to +5.5V, TA = -40°C to +85°C, Typical values are @ TA = +25°C and
VDD = 3.3V.
PARAMETER
CONDITIONS
MIN
(Note 12)
TYP
MAX
(Note 12)
UNIT
VDD
Main Power Supply
2.7
5.5
V
VBAT
Backup Power Supply
1.8
5.5
V
Electrical Specifications
MAX
(Note 12)
UNIT
NOTES
VDD = 2.7V
500
µA
3, 4, 5
VDD = 5.5V
800
µA
Supply Current for Non-Volatile
Programming
VDD = 2.7V
2.5
mA
VDD = 5.5V
3.5
mA
Supply Current for Main
Timekeeping (Low Power Mode)
VDD = VSDA = VSCL = 2.7V
10
µA
5
VDD = VSDA = VSCL = 5.5V
20
µA
5
SYMBOL
IDD1
IDD2
IDD3
IBAT
PARAMETER
Supply Current with I2C Active
Battery Supply Current
IBATLKG
Battery Input Leakage
VTRIP
VBAT Mode Threshold
CONDITIONS
MIN
(Note 12)
TYP
3, 4, 5
VBAT = 1.8V, VDD = VSDA = VSCL =
0V
800
1000
nA
3, 6, 7
VBAT = 3.0V,
VDD = VSDA = VSCL = 0V
850
1200
nA
3, 6, 7
100
nA
2.6
V
7
VDD = 5.5V, VBAT = 1.8V
1.8
2.2
VTRIPHYS VTRIP Hysteresis
30
mV
7,10
VBATHYS
VBAT Hysteresis
50
mV
7,10
VDD SR-
VDD Negative Slew Rate
10
V/ms
8
VDD = 5V
IOL = 3mA
0.4
V
VDD = 1.8V
IOL = 1mA
0.4
V
400
nA
IRQ/FOUT
VOL
ILO
Output Low Voltage
Output Leakage Current
FN6370 Rev 3.00
August 18, 2008
VDD = 5.5V
VOUT = 5.5V
100
Page 3 of 25
ISL12024
EEPROM Specifications
PARAMETER
TEST CONDITIONS
EEPROM Endurance
MIN
(Note 12)
MAX
UNITS
2,000,000
Cycles
50
Years
Temperature 75°C
EEPROM Retention
TYP
Serial Interface (I2C) Specifications
DC Electrical Specifications
SYMBOL
PARAMETER
MIN
(Note 12)
TEST CONDITIONS
TYP
MAX
(Note 12)
UNITS
VIL
SDA, and SCL Input Buffer LOW
Voltage
-0.3
0.3 x VDD
V
VIH
SDA, and SCL Input Buffer HIGH
Voltage
0.7 x VDD
VDD + 0.3
V
SDA and SCL Input Buffer Hysteresis
0.05 x VDD
Hysteresis
V
SDA Output Buffer LOW Voltage
IOL = 4mA
ILI
Input Leakage Current on SCL
VIN = 5.5V
100
nA
ILO
I/O Leakage Current on SDA
VIN = 5.5V
100
nA
VOL
0
0.4
V
AC Electrical Specifications
SYMBOL
fSCL
PARAMETER
TEST CONDITIONS
MIN
(Note 12)
TYP
MAX
(Note 12)
UNITS NOTES
SCL Frequency
400
kHz
tIN
Pulse width Suppression Time at Any pulse narrower than the max spec is
SDA and SCL Inputs
suppressed.
50
ns
tAA
SCL Falling Edge to SDA Output SCL falling edge crossing 30% of VDD, until SDA
Data Valid
exits the 30% to 70% of VDD window.
900
ns
tBUF
Time the Bus Must be Free
Before the Start of a New
Transmission
SDA crossing 70% of VDD during a STOP
condition, to SDA crossing 70% of VDD during
the following START condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VDD crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VDD crossing.
600
ns
tSU:STA
START Condition Set-up Time
SCL rising edge to SDA falling edge. Both
crossing 70% of VDD.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VDD to
SCL falling edge crossing 70% of VDD.
600
ns
tSU:DAT
Input Data Set-up Time
From SDA exiting the 30% to 70% of VDD
window, to SCL rising edge crossing 30% of
VDD.
100
ns
tHD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of VDD to
SDA entering the 30% to 70% of VDD window.
0
ns
tSU:STO
STOP Condition Set-up Time
From SCL rising edge crossing 70% of VDD, to
SDA rising edge crossing 30% of VDD.
600
ns
tHD:STO
STOP Condition Hold Time for
Read, or Volatile Only Write
From SDA rising edge to SCL falling edge. Both
crossing 70% of VDD.
600
ns
Output Data Hold Time
From SCL falling edge crossing 30% of VDD,
until SDA enters the 30% to 70% of VDD window.
0
ns
tDH
FN6370 Rev 3.00
August 18, 2008
Page 4 of 25
ISL12024
AC Electrical Specifications
SYMBOL
(Continued)
PARAMETER
MIN
(Note 12)
TEST CONDITIONS
Cpin
SDA and SCL Pin Capacitance
tWC
Non-Volatile Write Cycle Time
TYP
12
MAX
(Note 12)
UNITS NOTES
10
pF
20
ms
tR
SDA and SCL Rise Time
From 30% to 70% of VDD (Note 11)
20 +
0.1 x Cb
300
ns
11
tF
SDA and SCL Fall Time
From 70% to 30% of VDD (Note 11)
20 +
0.1 x Cb
300
ns
11
Cb
Capacitive Loading of SDA or
SCL
Total on-chip and off-chip. (Note 11)
10
400
pF
11
SDA and SCL Bus Pull-up
Resistor Off-chip
Maximum is determined by tR and tF.
For Cb = 400pF, max is about 2k~2.5k.
For Cb = 40pF, max is about 15k~20k
1
k
11
RPU
NOTES:
3. IRQ/FOUT Inactive.
4. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz
5. VDD > VBAT +VBATHYS
6. Bit BSW = 0 (Standard Mode), ATR = 00h, VBAT 1.8V
7. Specified at +25°C.
8. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
9. Parameter is not 100% tested.
10. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user (it is the time from valid STOP condition at the end
of Write sequence of a serial interface Write operation) to the end of the self-timed internal non-volatile write cycle.
11. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device
specification.
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
Timing Diagrams
Bus Timing
tHIGH
tF
SCL
tLOW
tR
tHD:STO
tSU:DAT
tSU:STA
SDA
(INPUT TIMING)
tHD:DAT
tHD:STA
tSU:STO
tAA
tDH
tBUF
SDA
(OUTPUT TIMING)
Write Cycle Timing
SCL
SDA
8TH BIT OF LAST BYTE
ACK
tWC
STOP
CONDITION
FN6370 Rev 3.00
August 18, 2008
START
CONDITION
Page 5 of 25
ISL12024
Typical Performance Curves
Temperature is +25°C unless otherwise specified.
0.9
4.0
BSW = 0 OR 1
3.5
0.8
0.7
SCL, SDA PULL-UPS = 0V
3.0
IBAT (µA)
2.5
IBAT (µA)
SCL, SDA PULL-UPS = 0V
BSW = 0 OR 1
0.6
2.0
1.5
1.0
SCL, SDA PULL-UPS = VBAT
0.5
BSW = 0 OR 1
0.0
1.8
2.3
2.8
3.3
3.8
0.5
0.4
0.3
0.2
0.1
4.3
4.8
0.0
1.8
5.3
2.3
2.8
3.3
VBAT (V)
FIGURE 1. IBAT vs VBAT, SBIB = 0
5.3
1.2
VDD = 5.5V
4.0
VBAT = 3.0V
1.0
IBAT (µA)
3.5
IDD (µA)
4.8
1.4
4.5
VDD = 3.3V
3.0
2.5
2.0
1.5
0.8
0.6
0.4
1.0
0.2
0.5
0.0
-45 -35 -25 -15
-5
5 15 25 35 45
TEMPERATURE (°C)
55
65
75
0.0
-45 -35 -25 -15
85
FIGURE 3. IDD3 vs TEMPERATURE
-5
5 15 25 35 45
TEMPERATURE (°C)
55
65
75
FIGURE 4. IBAT vs TEMPERATURE
80
4.5
PPM CHANGE FROM ATR = 0
4.0
3.5
3.0
IDD (µA)
4.3
FIGURE 2. IBAT vs VBAT, SBIB = 1
5.0
2.5
2.0
1.5
1.0
0.5
0.0
3.8
VBAT(V)
1.8
2.3
2.8
3.3
3.8
4.3
VDD (V)
FIGURE 5. IDD3 vs VDD
FN6370 Rev 3.00
August 18, 2008
4.8
5.3
60
40
20
0
-20
-40
-32 -28 -24 -20 -16 -12 -8 -4
0
4
8
12 16 20 24 28
ATR SETTING
FIGURE 6. FOUT vs ATR SETTING
Page 6 of 25
85
ISL12024
Description
VBAT
The ISL12024 device is a Real-Time Clock with clock/calendar,
64-bit unique ID, two polled alarms with integrated 512x8
EEPROM, oscillator compensation and battery backup switch.
This input provides a backup supply voltage to the device.
VBAT supplies power to the device in the event the VDD supply
fails. This pin can be connected to a battery, a Super Cap or
tied to ground if not used.
The oscillator uses an external, low-cost 32.768kHz crystal. All
compensation and trim components are integrated on the chip.
This eliminates several external discrete components and a
trim capacitor, saving board area and component cost.
The Real-Time Clock keeps track of time with separate
registers for Hours, Minutes and Seconds. The Calendar has
separate registers for Date, Month, Year and Day-of-week. The
calendar is correct through 2099, with automatic leap year
correction.
The 64-bit unique ID is a random numbers programmed,
verified and Locked at the factory and it is only accessible for
reading and cannot be altered by the customer.
The Dual Alarms can be set to any Clock/Calendar value for a
match. For instance, every minute, every Tuesday, or 5:23 AM
on March 21. The alarms can be polled in the Status Register
or can provide a hardware interrupt (IRQ/FOUT Pin). There is a
pulse mode for the alarms allowing for repetitive alarm
functionality.
The IRQ/FOUT pin may be software selected to provide a
frequency output of 1Hz, 4096Hz, or 32,768Hz or inactive.
The device offers a backup power input pin. This VBAT pin
allows the device to be backed up by battery or Super Cap.
The entire ISL12024 device is fully operational from 2.7V to
5.5V and the clock/calendar portion of the ISL12024 device
remains fully operational down to 1.8V (Standby Power Mode).
The ISL12024 device provides 4k bits of EEPROM with eight
modes of BlockLock™ control. The BlockLock allows a safe,
secure memory for critical user and configuration data, while
allowing a large user storage area.
Pin Descriptions
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device. The input buffer on this pin is always active (not gated).
The pull-up resistor on this pin must use the same voltage
source as VDD.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out of
the device. It has an open drain output and may be wire ORed
with other open drain or open collector outputs. The input
buffer is always active (not gated).
This open drain output requires the use of a pull-up resistor. The
pull-up resistor on this pin must use the same voltage source as
VDD. The output circuitry controls the fall time of the output
signal with the use of a slope controlled pull-down. The circuit is
designed to comply with 400kHz I2C interface speed.
FN6370 Rev 3.00
August 18, 2008
IRQ/FOUT (Interrupt Output/Frequency Output)
This dual function pin can be used as an interrupt or frequency
output pin. The IRQ/FOUT mode is selected via the frequency
out control bits of the INT register.
• Interrupt Mode. The pin provides an interrupt signal output.
This signal notifies a host processor that an alarm has
occurred and requests action. It is an open drain active low
output.
• Frequency Output Mode. The pin outputs a clock signal
which is related to the crystal frequency. The frequency
output is user selectable and enabled via the I2C bus. It is an
open drain output.
X1, X2
The X1 and X2 pins are the input and output, respectively, of an
inverting amplifier. An external 32.768kHz quartz crystal is used
with the ISL12024 to supply a timebase for the real-time clock.
Internal compensation circuitry provides high accuracy over the
operating temperature range from -40°C to +85°C. This
oscillator compensation network can be used to calibrate the
crystal timing accuracy over-temperature either during
manufacturing or with an external temperature sensor and
microcontroller for active compensation. X2 is intended to drive
a crystal only, and should not drive any external circuit.
X1
X2
FIGURE 7. RECOMMENDED CRYSTAL CONNECTION
Real-Time Clock Operation
The Real-Time Clock (RTC) uses an external 32.768kHz
quartz crystal to maintain an accurate internal representation of
the second, minute, hour, day, date, month and year. The RTC
has leap-year correction. The clock also corrects for months
having fewer than 31 days and has a bit that controls 24 hour
or AM/PM format. When the ISL12024 powers up after the loss
of both VDD and VBAT, the clock will not operate until at least
one byte is written to the clock register.
Reading the Real-Time Clock
The RTC is read by initiating a Read command and specifying
the address corresponding to the register of the Real-Time
Clock. The RTC Registers can then be read in a Sequential
Read Mode. Since the clock runs continuously and a read
takes a finite amount of time, there is the possibility that the
clock could change during the course of a read operation. In
this device, the time is latched by the read command (falling
Page 7 of 25
ISL12024
edge of the clock on the ACK bit prior to RTC data output) into
a separate latch to avoid time changes during the read
operation. The clock continues to run. Alarms occurring during
a read are unaffected by the read operation.
1. Alarm 0 (8 bytes; non-volatile)
Writing to the Real-Time Clock
5. Real-Time Clock (8 bytes; volatile)
The time and date may be set by writing to the RTC registers.
RTC Register should be written ONLY with Page Write. To
avoid changing the current time by an uncompleted write
operation, write to the all 8 bytes in one write operation. When
writing the RTC registers, the new time value is loaded into a
separate buffer at the falling edge of the clock during the
Acknowledge. This new RTC value is loaded into the RTC
Register by a stop bit at the end of a valid write sequence. An
invalid write operation aborts the time update procedure and
the contents of the buffer are discarded. After a valid write
operation the RTC will reflect the newly loaded data beginning
with the next “one second” clock cycle after the stop bit is
written. The RTC continues to update the time while an RTC
register write is in progress and the RTC continues to run
during any non-volatile write sequences.
6. Status (1 byte; volatile)
Accuracy of the Real-Time Clock
The accuracy of the Real-Time Clock depends on the accuracy
of the quartz crystal that is used as the time base for the RTC.
Since the resonant frequency of a crystal is temperature
dependent, the RTC performance will also be dependent upon
temperature. The frequency deviation of the crystal is a
function of the turnover temperature of the crystal from the
crystal’s nominal frequency. For example, a >20ppm frequency
deviation translates into an accuracy of >1 minute per month.
These parameters are available from the crystal manufacturer.
Intersil’s RTC family provides on-chip crystal compensation
networks to adjust load-capacitance to tune oscillator
frequency from -34ppm to +80ppm when using a 12.5pF load
crystal. For more detailed information see the “Application
Section” on page 20.
Clock/Control Registers (CCR)
The Control/Clock Registers are located in an area separate
from the EEPROM array and are only accessible following a
slave byte of “1101111x” and reads or writes to addresses
[0000h:003Fh]. The clock/control memory map has memory
addresses from 0000h to 003Fh. The defined addresses are
described in the Table 1. Writing to and reading from the
undefined addresses are not recommended.
CCR Access
The contents of the CCR can be modified by performing a byte
or a page write operation directly to any address in the CCR.
Prior to writing to the CCR (except the status register),
however, the WEL and RWEL bits must be set using a three
step process (“Writing to the Clock/Control Registers” on
page 12.”)
The CCR is divided into 6 sections. These are:
FN6370 Rev 3.00
August 18, 2008
2. Alarm 1 (8 bytes; non-volatile)
3. Control (5 bytes; non-volatile)
4. Unique ID (8 bytes; non-volatile)
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one section
of the CCR per operation. Access to another section requires a
new operation. A read or write can begin at any address in the
CCR.
It is not necessary to set the RWEL bit prior to writing the
status register. Section 5 (status register) supports a single
byte read or write only. Continued reads or writes from this
section terminates the operation.
The state of the CCR can be read by performing a random
read at any address in the CCR at any time. This returns the
contents of that register location. Additional registers are read
by performing a sequential read. The read instruction latches
all Clock registers into a buffer, so an update of the clock does
not change the time being read. A sequential read of the CCR
will not result in the output of data from the memory array. At
the end of a read, the master supplies a stop condition to end
the operation and free the bus. After a read of the CCR, the
address remains at the previous address +1 so the user can
execute a current address read of the CCR and continue
reading the next Register.
Real-Time Clock Registers
SC, MN, HR, DT, MO, YR: - Clock/Calendar Registers
These registers depict BCD representations of the time. As
such, SC (Seconds) and MN (Minutes) range from 00 to 59,
HR (Hour) is 1 to 12 with an AM or PM indicator (H21-bit) or 0
to 23 (with MIL = 1), DT (Date) is 1 to 31, MO (Month) is 1 to
12, YR (Year) is 0 to 99.
DW: Day of the Week Register
This register provides a Day of the Week status and uses three
bits DY2 to DY0 to represent the seven days of the week. The
counter advances in the cycle
0-1-2-3-4-5-6-0-1-2-… The assignment of a numerical value to
a specific day of the week is arbitrary and may be decided by
the system software designer. The default value is defined as
‘0’.
24 Hour Time
If the MIL bit of the HR register is 1, the RTC uses a 24-hour
format. If the MIL bit is 0, the RTC uses a 12-hour format and
H21-bit functions as an AM/PM indicator with a ‘1’ representing
PM. The clock defaults to standard time with H21 = 0.
Page 8 of 25
ISL12024
Leap Years
Leap years add the day February 29 and are defined as those
years that are divisible by 4.
RTCF: Real-Time Clock Fail Bit - Volatile
Status Register (SR)
The Status Register is located in the CCR memory map at
address 003Fh. This is a volatile register only and is used to
control the WEL and RWEL write enable latches, read power
status and two alarm bits. This register is separate from both
the array and the Clock/Control Registers (CCR).
TABLE 1. STATUS REGISTER (SR)
ADDR
7
6
003Fh
BAT
AL1
Default
0
0
5
4
AL0 OSCF
0
the part powers up again. Writes to WEL bit do not cause a
non-volatile write cycle, so the device is ready for the next
operation immediately after the stop condition.
0
3
2
1
0
0
RWEL
WEL
RTCF
0
0
0
1
This bit is set to a ‘1’ after a total power failure. This is a read
only bit that is set internally when the device powers up after
having lost all power to the device. The bit is set regardless of
whether VDD or VBAT is applied first. The loss of only one of
the supplies does not result in setting the RTCF bit. The first
valid write to the RTC after a complete power failure (writing
one byte is sufficient) resets the RTCF bit to ‘0’.
Unused Bits:
Bit 3 in the SR is not used, but must be zero. The Data Byte
output during a SR read will contain a zero in this bit location.
BAT: Battery Supply - Volatile
This bit set to “1” indicates that the device is operating from
VBAT, not VDD. It is a read-only bit and is set/reset by hardware
(ISL12024 internally). Once the device begins operating from
VDD, the device sets this bit to “0”.
AL1, AL0: Alarm bits - Volatile
These bits announce if either alarm 0 or alarm 1 match the
real-time clock. If there is a match, the respective bit is set to
‘1’. The falling edge of the last data bit in a SR Read operation
resets the flags. Note: Only the AL bits that are set when an SR
read starts will be reset. An alarm bit that is set by an alarm
occurring during an SR read operation will remain set after the
read operation is complete.
OSCF: Oscillator Fail Indicator
This bit is set to “1” if the oscillator is not operating, or is
operating but has clock jitter which does not affect the
accuracy of RTC counting. The bit is set to “0” if the oscillator is
functioning, and does not have clock jitter. This bit is read only,
and is set/reset by hardware.
RWEL: Register Write Enable Latch-Volatile
This bit is a volatile latch that powers up in the LOW (disabled)
state. The RWEL bit must be set to “1” prior to any writes to the
Clock/Control Registers. Writes to RWEL bit do not cause a
non-volatile write cycle, so the device is ready for the next
operation immediately after the stop condition. A write to the
CCR requires both the RWEL and WEL bits to be set in a
specific sequence.
WEL: Write Enable Latch - Volatile
The WEL bit controls the access to the CCR during a write
operation. This bit is a volatile latch that powers up in the LOW
(disabled) state. While the WEL bit is LOW, writes to the CCR
address will be ignored, although acknowledgment is still
issued. The WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the Status Register. Once set, WEL
remains set until either reset to 0 (by writing a “0” to the WEL
bit and zeroes to the other bits of the Status Register) or until
FN6370 Rev 3.00
August 18, 2008
Page 9 of 25
ISL12024
TABLE 2. CLOCK/CONTROL MEMORY MAP
REG
NAME
7
6
Status
SR
BAT
AL1
AL0
RTC
(SRAM)
Y2K
0
0
Y2K21
DW
0
0
0
0
0035
YR
Y23
Y22
Y21
Y20
Y13
Y12
0034
MO
0
0
0
G20
G13
G12
ADDR.
TYPE
003F
0037
0036
5
4
0
DEFAULT
BIT
3
2
1
OSCF
0
RWEL
WEL
RTCF
Y2K20
Y2K13
0
0
Y2K10
19/20
20h
0
DY2
DY1
DY0
0-6
00h
Y11
Y10
0-99
00h
G11
G10
1-12
00h
RANGE
01h
0033
DT
0
0
D21
D20
D13
D12
D11
D10
1-31
01h
0032
HR
MIL
0
H21
H20
H13
H12
H11
H10
0-23
00h
0031
MN
0
M22
M21
M20
M13
M12
M11
M10
0-59
00h
0-59
00h
0030
SC
0
S22
S21
S20
S13
S12
S11
S10
0027
ID7
ID77
ID76
ID75
ID74
ID73
ID72
ID71
ID70
*
0026
ID6
ID67
ID66
ID65
ID64
ID63
ID62
ID61
ID60
*
0025
ID5
ID57
ID56
ID55
ID54
ID53
ID52
ID51
ID50
*
ID4
ID47
ID46
ID45
ID44
ID43
ID42
ID41
ID40
*
0024
0023
Device ID
ID3
ID37
ID36
ID35
ID34
ID33
ID32
ID31
ID30
*
0022
ID2
ID27
ID26
ID25
ID24
ID23
ID22
ID21
ID20
*
0021
ID1
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
*
0020
ID0
ID07
ID06
ID05
ID04
ID03
ID02
ID01
ID00
*
PWR
SBIB
BSW
0
0
0
0
0
0
40h
0014
0013
Control
(EEPROM)
DTR
0
0
0
0
0
DTR2
DTR1
DTR0
00h
0012
ATR
0
0
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
00h
0011
INT
IM
AL1E
AL0E
FO1
FO0
0
0
0
00h
0010
BL
BP2
BP1
BP0
0
0
0
0
0
00h
Y2K1
0
0
A1Y2K21
A1Y2K20
A1Y2K13
0
0
A1Y2K10
19/20
20h
DWA1
EDW1
0
0
0
0
DY2
DY1
DY0
0-6
00h
000F
000E
Alarm1
(EEPROM)
000D
YRA1
000C
MOA1
Unused - Default = RTC Year value (No EEPROM) - Future expansion
EMO1
0
0
A1G20
A1G13
A1G12
A1G11
A1G10
1-12
00h
000B
DTA1
EDT1
0
A1D21
A1D20
A1D13
A1D12
A1D11
A1D10
1-31
00h
000A
HRA1
EHR1
0
A1H21
A1H20
A1H13
A1H12
A1H11
A1H10
0-23
00h
0009
MNA1
EMN1
A1M22
A1M21
A1M20
A1M13
A1M12
A1M11
A1M10
0-59
00h
SCA1
ESC1
A1S22
A1S21
A1S20
A1S13
A1S12
A1S11
A1S10
0-59
00h
Y2K0
0
0
A0Y2K21
A0Y2K20
A0Y2K13
0
0
A0Y2K10
19/20
20h
DWA0
EDW0
0
0
0
0
DY2
DY1
DY0
0-6
00h
0008
0007
0006
Alarm0
(EEPROM)
0005
YRA0
0004
MOA0
Unused - Default = RTC Year value (No EEPROM) - Future expansion
EMO0
0
0
A0G20
A0G13
A0G12
A0G11
A0G10
1-12
00h
0003
DTA0
EDT0
0
A0D21
A0D20
A0D13
A0D12
A0D11
A0D10
1-31
00h
0002
HRA0
EHR0
0
A0H21
A0H20
A0H13
A0H12
A0H11
A0H10
0-23
00h
0001
MNA0
EMN0
A0M22
A0M21
A0M20
A0M13
A0M12
A0M11
A0M10
0-59
00h
0000
SCA0
ESC0
A0S22
A0S21
A0S20
A0S13
A0S12
A0S11
A0S10
0-59
00h
NOTE: Shaded cells indicate that NO other value is to be written to that bit. * indicates set at the factory, read-only.
FN6370 Rev 3.00
August 18, 2008
Page 10 of 25
ISL12024
Alarm Registers (Non-Volatile)
Alarm0 and Alarm1
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make the
comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the alarm
registers and the RTC registers. As the RTC advances, the
alarm will be triggered once a match occurs between the alarm
registers and the RTC registers. Any one alarm register,
multiple registers, or all registers can be enabled for a match.
See “Device Operation” on page 12 and “Application Section”
on page 20 for more information.
Control Registers (Non-Volatile)
The Control Bits and Registers described under this section
are non-volatile.
The IM bit enables the pulsed interrupt mode. To enter this
mode, the AL0E or AL1E bits are set to “1”, and the IM bit to
“1”. The IRQ/FOUT output will now be pulsed each time an
alarm occurs. This means that once the interrupt mode alarm
is set, it will continue to alarm for each occurring match of the
alarm and present time. This mode is convenient for hourly or
daily hardware interrupts in microcontroller applications such
as security cameras or utility meter reading.
In this case both Alarms are enabled.
FO1, FO0 - Programmable Frequency Output Bits
These are two output control bits. They select one of three
divisions of the internal oscillator, that is applied to the
IRQ/FOUT output pin. Table 4 shows the selection bits for this
output. When using this function, the Alarm output function is
disabled.
TABLE 4. PROGRAMMABLE FREQUENCY OUTPUT BITS
FO1
FO0
OUTPUT FREQUENCY
0
0
BL Register
Alarm output (FOUT disabled)
0
1
32.768kHz
BP2, BP1, BP0 - Block Protect Bits
1
0
4096Hz
The Block Protect Bits, BP2, BP1 and BP0, determine which
blocks of the array are write protected. A write to a protected
block of memory is ignored. The block protect bits will prevent
write operations to one of eight segments of the array. The
partitions are described in Table 3.
1
1
1Hz
TABLE 3.
Oscillator Compensation Registers
There are two trimming options.
• ATR. Analog Trimming Register
BP2
BP1
BP0
• DTR. Digital Trimming Register
PROTECTED ADDRESSES
ISL12024
0
0
0
None (Default)
None
0
0
1
180h – 1FFh
Upper 1/4
0
1
0
100h – 1FFh
Upper 1/2
0
1
1
000h – 1FFh
Full Array
1
0
0
000h – 03Fh
First 4 Pages
1
0
1
000h – 07Fh
First 8 Pages
1
1
0
000h – 0FFh
First 16 Pages
1
1
1
000h – 1FFh
Full Array
ARRAY LOCK
INT Register: Interrupt Control and
Frequency Output Register
These registers are non-volatile. The combination of analog
and digital trimming can give up to -64ppm to +110 ppm of total
adjustment.
ATR Register - ATR5, ATR4, ATR3, ATR2, ATR1,
ATR0: Analog Trimming Register
Six analog trimming bits, ATR0 to ATR5, are provided in order
to adjust the on-chip load capacitance value for frequency
compensation of the RTC. Each bit has a different weight for
capacitance adjustment. For example, using a Citizen CFS206 crystal with different ATR bit combinations provides an
estimated ppm adjustment range from -34ppm to +80ppm to
the nominal frequency compensation.
X1
CX1
IM, AL1E, AL0E - Interrupt Control and Status Bits
There are two Interrupt Control bits, Alarm 1 Interrupt Enable
(AL1E) and Alarm 0 Interrupt Enable (AL0E) to specifically
enable or disable the alarm interrupt signal output (IRQ/FOUT).
The interrupts are enabled when either the AL1E or AL0E or
both bits are set to ‘1’ and both the FO1 and FO0 bits are set to
0 (FOUT disabled).
FN6370 Rev 3.00
August 18, 2008
CRYSTAL
OSCILLATOR
X2
CX2
FIGURE 8. DIAGRAM OF ATR
Page 11 of 25
ISL12024
The effective on-chip series load capacitance, CLOAD, ranges
from 4.5pF to 20.25pF with a mid-scale value of 12.5pF
(default). CLOAD is changed via two digitally controlled
capacitors, CX1 and CX2, connected from the X1 and X2 pins
to ground (see Figure 8). The value of CX1 and CX2 is given
Equation 1:
C
X
= 16 b5 + 8 b4 + 4 b3 + 2 b2 + 1 b1 + 0.5 b0 + 9 pF
PWR Register: SBIB, BSW
SBIB: Serial Bus Interface (Enable)
The serial bus can be disabled in Battery Backup Mode by
setting this bit to “1”. This will minimize power drain on the
battery. The Serial Interface can be enabled in Battery Backup
Mode by setting this bit to “0” (default is “0”). See “Power
Control Operation” on page 13.
(EQ. 1)
BSW: Power Control Bit
The effective series load capacitance is the combination of CX1
and CX2:
C
LOAD
1
1
1
---------- + -----------
C
C
= ----------------------------------X1
C
LOAD
(EQ. 2)
X2
16 b5 + 8 b4 + 4 b3 + 2 b2 + 1 b1 + 0.5 b0 + 9
= ----------------------------------------------------------------------------------------------------------------------------- pF
2
For example:
CLOAD(ATR = 00000) = 12.5pF,
CLOAD(ATR = 100000) = 4.5pF, and
CLOAD(ATR = 011111) = 20.25pF.
DTR Register - DTR2, DTR1, DTR0: Digital Trimming
Register
The digital trimming Bits DTR2, DTR1 and DTR0 adjust the
number of counts per second and average the ppm error to
achieve better accuracy.
DTR2 is a sign bit, where:
DTR2 = 0 means frequency compensation is >0.
DTR2 = 1 means frequency compensation is
