DATASHEET
ISL12026, ISL12026A
FN8231
Rev 9.00
November 30, 2010
Real Time Clock/Calendar with I2C Bus™ and EEPROM
The ISL12026 and the ISL12026A devices are micro power
real time clocks with timing and crystal compensation,
clock/calender, power-fail indicator, two periodic or polled
alarms, intelligent battery backup switching, and integrated
512x8-bit EEPROM configured in 16 Bytes per page.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
The ISL12026 and ISL12026A have different types of Power
Control Settings. The ISL12026 uses the Legacy Mode
Setting, which follows conditions set in X1226 products. The
ISL12026A uses the Standard Mode Setting. Please refer to
“Power Control Operation” on page 13 for more details. Also,
please refer to “I2C Communications During Battery Backup”
on page 22 for important details.
Pinouts
ISL12026, ISL12026A
(8 LD SOIC)
TOP VIEW
X1
1
8
VDD
X2
2
7
VBAT
3
6
SCL
4
5
SDA
IRQ/FOUT
GND
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes and Seconds
- Day of the Week, Day, Month and Year
- 3 Selectable Frequency Outputs
• Two Non-Volatile Alarms
- Settable on the Second, Minute, Hour, Day of the Week,
Day or Month
- Repeat Mode (Periodic Interrupts)
• Automatic Backup to Battery or SuperCap
• On-Chip Oscillator Compensation
- Internal Feedback Resistor and Compensation
Capacitors
- 64 Position Digitally Controlled Trim Capacitor
- 6 Digital Frequency Adjustment Settings to ±30ppm
• 512x8 Bits of EEPROM
- 16-Byte Page Write Mode (32 total pages)
- 8 Modes of BlockLock™ Protection
- Single Byte Write Capability
• High Reliability
- Data Retention: 50 years
- Endurance: >2,000,000 Cycles Per Byte
• I2C Interface
- 400kHz Data Transfer Rate
• 800nA Battery Supply Current
• Package Options
- 8 Ld SOIC and 8 Ld TSSOP Packages
ISL12026, ISL12026A
(8 LD TSSOP)
TOP VIEW
• Pb-Free (RoHS Compliant)
VBAT
1
8
SCL
VDD
2
7
SDA
X1
3
6
GND
X2
4
5
IRQ/FOUT
FN8231 Rev 9.00
November 30, 2010
Features
Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Utility Meters
HVAC Equipment
Audio/Video Components
Set-Top Box/Television
Modems
Network Routers, Hubs, Switches, Bridges
Cellular Infrastructure Equipment
Fixed Broadband Wireless Equipment
Pagers/PDA
POS Equipment
Test Meters/Fixtures
Office Automation (Copiers, Fax)
Home Appliances
Computer Products
Other Industrial/Medical/Automotive
Page 1 of 24
ISL12026, ISL12026A
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
VBAT TRIP POINT
(V)
BSW BIT DEFAULT TEMP RANGE
SETTING
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL12026IBZ
12026 IBZ
VDD < VBAT
BSW = 1
-40 to +85
8 Ld SOIC
M8.15
ISL12026IVZ
2026 IVZ
VDD < VBAT
BSW = 1
-40 to +85
8 Ld TSSOP
M8.173
ISL12026AIBZ
12026A IBZ
2.2
BSW = 0
-40 to +85
8 Ld SOIC
M8.15
ISL12026AIVZ
2026A IVZ
2.2
BSW = 0
-40 to +85
8 Ld TSSOP
M8.173
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL12026, ISL12026A. For more information on MSL please see
techbrief TB363.
Block Diagram
OSC
COMPENSATION
X1
OSCILLATOR
X2
IRQ/FOUT
SELECT
SCL
SERIAL
INTERFACE
DECODER
SDA
CONTROL
DECODE
LOGIC
CONTROL/
REGISTERS
(EEPROM)
8
TIMER
FREQUENCY 1Hz
CALENDAR
DIVIDER
LOGIC
STATUS
REGISTERS
(SRAM)
TIME
KEEPING
REGISTERS
(SRAM)
BATTERY
SWITCH
CIRCUITRY
VDD
VBAT
COMPARE
ALARM
MASK
32.768kHz
ALARM REGS
(EEPROM)
4k
EEPROM
ARRAY
Pin Descriptions
PIN NUMBER
SOIC
TSSOP
SYMBOL
DESCRIPTION
1
3
X1
The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external
32.768kHz quartz crystal. X1 can also be driven directly from a 32.768kHz source (see “Application Section”
on page 19.)
2
4
X2
The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external
32.768kHz quartz crystal (see “Application Section” on page 19.)
3
5
IRQ/FOUT
4
6
GND
Ground.
5
7
SDA
Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an open
drain output and may be wire OR’ed with other open drain or open collector outputs.
6
8
SCL
The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on
this pin is always active (not gated).
7
1
VBAT
This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event
that the VDD supply fails. This pin should be tied to ground if not used.
8
2
VDD
Power Supply.
FN8231 Rev 9.00
November 30, 2010
Interrupt Output/Frequency Output is a multi-functional pin that can be used as interrupt or frequency
output pin. The function is set via the control register. This output is an open drain configuration.
Page 2 of 24
ISL12026, ISL12026A
Absolute Maximum Ratings
Thermal Information
Voltage on VDD, VBAT, SCL, SDA, and IRQ/FOUT Pins
(respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on X1 and X2 Pins
(respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V
Latchup (Note 4) . . . . . . . . . . . . . . . . . . . Class II, Level B @ +85°C
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175V
Thermal Resistance (Typical)
JA (°C/W)
JC (°C/W)
8 Ld SOIC Package (Notes 5, 6) . . . . .
115
50
8 Ld TSSOP Package (Notes 5, 6) . . .
140
48
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: Using a max positive pulse of 8.35V on all pins except X1 and
X2, Using a max positive pulse of 2.75V on X1 and X2, and using a max negative pulse of -1V for all pins.
5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. For JC, the “case temp” location is taken at the package top center.
DC Electrical Specifications
Unless otherwise noted, VDD = +2.7V to +5.5V, TA = -40°C to +85°C, Typical values are @ TA = +25°C
and VDD = 3.3V.
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 16)
TYP
MAX
(Note 16)
UNIT
NOTES
VDD
Main Power Supply
2.7
5.5
V
VBAT
Backup Power Supply
1.8
5.5
V
MAX
(Note 16)
UNIT
NOTES
VDD = 2.7V
500
µA
7, 8, 9
VDD = 5.5V
800
µA
VDD = 2.7V
2.5
mA
VDD = 5.5V
3.5
mA
VDD = VSDA = VSCL = 2.7V
10
µA
VDD = VSDA = VSCL = 5.5V
20
µA
Electrical Specifications
SYMBOL
IDD1
IDD2
IDD3
IBAT
PARAMETER
Supply Current with I2C Active
Supply Current for Non-Volatile
Programming
Supply Current for Main
Timekeeping (Low Power Mode)
Battery Supply Current
IBATLKG
Battery Input Leakage
VTRIP
VBAT Mode Threshold
CONDITIONS
MIN
(Note 16)
TYP
7, 8, 9
9
VBAT = 1.8V,
VDD = VSDA = VSCL = VRESET = 0
800
1000
nA
VBAT = 3.0V,
VDD = VSDA = VSCL = VRESET = 0
850
1200
nA
100
nA
2.6
V
11
VDD = 5.5V, VBAT = 1.8V
1.8
2.2
7, 10, 11
VTRIPHYS
VTRIP Hysteresis
30
mV
11, 14
VBATHYS
VBAT Hysteresis
50
mV
11, 14
VDD SR-
VDD Negative Slew Rate
10
V/ms
12
VDD = 5V
IOL = 3mA
0.4
V
VDD = 1.8V
IOL = 1mA
0.4
V
400
nA
IRQ/FOUT
VOL
ILO
Output Low Voltage
Output Leakage Current
FN8231 Rev 9.00
November 30, 2010
VDD = 5.5V
VOUT = 5.5V
100
Page 3 of 24
ISL12026, ISL12026A
EEPROM Specifications
PARAMETER
TEST CONDITIONS
EEPROM Endurance
MIN
(Note 16)
UNITS
>2,000,000
Cycles
50
Years
Temperature 75°C
EEPROM Retention
MAX
(Note 16)
TYP
NOTES
Serial Interface (I2C) Specifications
DC Electrical Specifications
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 16)
TYP
MAX
(Note 16)
UNITS
VIL
SDA and SCL Input Buffer LOW
Voltage
-0.3
0.3xVDD
V
VIH
SDA and SCL Input Buffer HIGH
Voltage
0.7 x VDD
VDD + 0.3
V
Hysteresis SDA and SCL Input Buffer
Hysteresis
V
0.05 x VDD
SDA Output Buffer LOW Voltage
IOL = 4mA
ILI
Input Leakage Current on SCL
VIN = 5.5V
100
nA
ILO
I/O Leakage Current on SDA
VIN = 5.5V
100
nA
VOL
NOTES
0
0.4
V
AC Electrical Specifications
SYMBOL
fSCL
PARAMETER
TEST CONDITIONS
MIN
(Note 16)
SCL Frequency
TYP
MAX
(Note 16)
UNITS
400
kHz
tIN
Pulse width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max
spec is suppressed.
50
ns
tAA
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of
VDD, until SDA exits the 30% to 70%
of VDD window.
900
ns
tBUF
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VDD during a
STOP condition, to SDA crossing
70% of VDD during the following
START condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VDD
crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VDD
crossing.
600
ns
tSU:STA
START Condition Set-up Time
SCL rising edge to SDA falling edge.
Both crossing 70% of VDD.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing
30% of VDD to SCL falling edge
crossing 70% of VDD.
600
ns
tSU:DAT
Input Data Set-up Time
From SDA exiting the 30% to 70% of
VDD window, to SCL rising edge
crossing 30% of VDD.
100
ns
tHD:DAT
Input Data Hold Time
From SCL rising edge crossing 70%
of VDD to SDA entering the 30% to
70% of VDD window.
0
ns
FN8231 Rev 9.00
November 30, 2010
NOTES
Page 4 of 24
ISL12026, ISL12026A
AC Electrical Specifications
SYMBOL
(Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 16)
TYP
MAX
(Note 16)
UNITS
tSU:STO
STOP Condition Set-up Time
From SCL rising edge crossing 70%
of VDD, to SDA rising edge crossing
30% of VDD.
600
ns
tHD:STO
STOP Condition Hold Time for
Read or Volatile Only Write
From SDA rising edge to SCL falling
edge. Both crossing 70% of VDD.
600
ns
tDH
Output Data Hold Time
From SCL falling edge crossing 30%
of VDD, until SDA enters the 30% to
70% of VDD window.
0
ns
Cpin
SDA and SCL Pin Capacitance
tWC
Non-volatile Write Cycle Time
12
10
pF
20
ms
NOTES
14
tR
SDA and SCL Rise Time
From 30% to 70% of VDD
20 + 0.1xCb
300
ns
tF
SDA and SCL Fall Time
From 70% to 30% of VDD
20 +0.1xCb
300
ns
15
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
400
pF
15
SDA and SCL Bus Pull-up Resistor Maximum is determined by tR and tF.
Off-chip
For Cb = 400pF, max is about
2k~2.5k.
For Cb = 40pF, max is about
15k~20k
1
k
15
RPU
NOTES:
7. IRQ/FOUT Inactive.
8. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz
9. VDD > VBAT +VBATHYS
10. Bit BSW = 0 (Standard Mode), ATR = 00h, VBAT 1.8V
11. Specified at +25°C.
12. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
13. Parameter is not 100% tested.
14. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid STOP condition at the end of Write
sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.
15. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
16. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Timing Diagrams
Bus Timing
tHIGH
tF
SCL
tLOW
tR
tHD:STO
tSU:DAT
tSU:STA
SDA
(INPUT TIMING)
tHD:STA
tHD:DAT
tSU:STO
tAA
tDH
tBUF
SDA
(OUTPUT TIMING)
FN8231 Rev 9.00
November 30, 2010
Page 5 of 24
ISL12026, ISL12026A
Write Cycle Timing
SCL
8TH BIT OF LAST BYTE
SDA
ACK
tWC
STOP
CONDITION
Typical Performance Curves
Temperature is +25°C unless otherwise specified.
0.9
4.0
BSW = 0 OR 1
3.5
0.7
2.5
2.0
1.5
0.5
0.4
0.3
1.0
SCL, SDA PULL-UPS = VBAT
0.5
BSW = 0 OR 1
2.3
2.8
3.3
3.8
VBAT (V)
0.2
0.1
4.3
4.8
0.0
1.8
5.3
2.3
2.8
3.3
3.8
4.3
4.8
5.3
VBAT (V)
FIGURE 1. IBAT vs VBAT, SBIB = 0
FIGURE 2. IBAT vs VBAT, SBIB = 1
1.4
5.0
4.5
1.2
VDD = 5.5V
4.0
VBAT = 3.0V
1.0
3.5
VDD = 3.3V
3.0
IBAT (µA)
IDD (µA)
SCL, SDA PULL-UPS = 0V
BSW = 0 OR 1
0.6
IBAT (µA)
IBAT (µA)
0.8
SCL, SDA PULL-UPS = 0V
3.0
0.0
1.8
START
CONDITION
2.5
2.0
1.5
0.8
0.6
0.4
1.0
0.2
0.5
0.0
-45 -35 -25 -15
-5
5
15
25
35
45
55
TEMPERATURE (°C)
FIGURE 3. IDD3 vs TEMPERATURE
FN8231 Rev 9.00
November 30, 2010
65
75
85
0.0
-45 -35 -25 -15
-5
5
15
25
35
45
55
65
75
TEMPERATURE (°C)
FIGURE 4. IBAT vs TEMPERATURE
Page 6 of 24
85
ISL12026, ISL12026A
Typical Performance Curves
(Continued)Temperature is +25°C unless otherwise specified.
4.5
80
PPM CHANGE FROM ATR = 0
4.0
3.5
IDD (µA)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.8
2.3
2.8
3.3
3.8
4.3
4.8
60
40
20
0
-20
-40
5.3
-32 -28 -24 -20 -16 -12 -8 -4
VDD (V)
The ISL12026 device is a Real Time Clock with clock/calendar,
two polled alarms with integrated 512x8 EEPROM, oscillator
compensation and battery backup switch.
The oscillator uses an external, low-cost 32.768kHz crystal. All
compensation and trim components are integrated on the chip.
This eliminates several external discrete components and a
trim capacitor, saving board area and component cost.
The Real Time Clock keeps track of time with separate
registers for Hours, Minutes and Seconds. The Calendar has
separate registers for Date, Month, Year and Day-of-week. The
calendar is correct through 2099, with automatic leap year
correction.
The Dual Alarms can be set to any Clock/Calendar value for a
match. For instance, every minute, every Tuesday, or 5:23 AM
on March 21. The alarms can be polled in the Status Register
or can provide a hardware interrupt (IRQ/FOUT Pin). There is a
pulse mode for the alarms allowing for repetitive alarm
functionality.
The IRQ/FOUT pin may be software selected to provide a
frequency output of 1Hz, 4096Hz, or 32,768Hz or inactive.
The device offers a backup power input pin. This VBAT pin
allows the device to be backed up by battery or SuperCap. The
entire ISL12026 device is fully operational from 2.7V to 5.5V
and the clock/calendar portion of the ISL12026 device remains
fully operational down to 1.8V (Standby Mode).
The ISL12026 device provides 4k bits of EEPROM with 8
modes of BlockLock™ control. The BlockLock™ allows a safe,
secure memory for critical user and configuration data, while
allowing a large user storage area.
4
8
12 16 20 24 28
FIGURE 6. FOUT vs ATR SETTING
FIGURE 5. IDD3 vs VDD
Description
0
ATR SETTING
Pin Descriptions
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the device.
The input buffer on this pin is always active (not gated). The pullup resistor on this pin must use the same voltage source as
VDD.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out of
the device. It has an open drain output and may be wire ORed
with other open drain or open collector outputs. The input
buffer is always active (not gated).
This open drain output requires the use of a pull-up resistor. The
pull-up resistor on this pin must use the same voltage source as
VDD. The output circuitry controls the fall time of the output
signal with the use of a slope controlled pull-down. The circuit is
designed to comply with 400kHz I2C interface speed.
VBAT
This input provides a backup supply voltage to the device.
VBAT supplies power to the device in the event the VDD supply
fails. This pin can be connected to a battery, a SuperCap or
tied to ground if not used.
IRQ/FOUT (Interrupt Output/Frequency Output)
This dual function pin can be used as an interrupt or frequency
output pin. The IRQ/FOUT mode is selected via the frequency
out control bits of the INT register.
• Interrupt Mode. The pin provides an interrupt signal output.
This signal notifies a host processor that an alarm has
occurred and requests action. It is an open drain active low
output.
• Frequency Output Mode. The pin outputs a clock signal
which is related to the crystal frequency. The frequency
output is user selectable and enabled via the I2C bus. It is an
open drain output.
FN8231 Rev 9.00
November 30, 2010
Page 7 of 24
ISL12026, ISL12026A
X1, X2
The X1 and X2 pins are the input and output, respectively, of
an inverting amplifier. An external 32.768kHz quartz crystal is
used with the ISL12026 to supply a timebase for the real time
clock. Internal compensation circuitry provides high accuracy
over the operating temperature range from -40°C to +85°C.
This oscillator compensation network can be used to calibrate
the crystal timing accuracy over-temperature either during
manufacturing or with an external temperature sensor and
microcontroller for active compensation. X2 is intended to drive
a crystal only, and should not drive any external circuit.
X1
X2
FIGURE 7. RECOMMENDED CRYSTAL CONNECTION
register write is in progress and the RTC continues to run
during any non-volatile write sequences.
Accuracy of the Real Time Clock
The accuracy of the Real Time Clock depends on the accuracy
of the quartz crystal that is used as the time base for the RTC.
Since the resonant frequency of a crystal is temperature
dependent, the RTC performance will also be dependent upon
temperature. The frequency deviation of the crystal is a
function of the turnover temperature of the crystal from the
crystal’s nominal frequency. For example, a >20ppm frequency
deviation translates into an accuracy of >1 minute per month.
These parameters are available from the crystal manufacturer.
Intersil’s RTC family provides on-chip crystal compensation
networks to adjust load-capacitance to tune oscillator
frequency from -34ppm to +80ppm when using a 12.5pF load
crystal. For more detailed information, see “Application
Section” on page 19.
Real Time Clock Operation
Clock/Control Registers (CCR)
The Real Time Clock (RTC) uses an external 32.768kHz
quartz crystal to maintain an accurate internal representation of
the second, minute, hour, day, date, month and year. The RTC
has leap-year correction. The clock also corrects for months
having fewer than 31 days and has a bit that controls 24 hour
or AM/PM format. When the ISL12026 powers up after the loss
of both VDD and VBAT, the clock will not operate until at least
one byte is written to the clock register.
The Control/Clock Registers are located in an area separate
from the EEPROM array and are only accessible following a
slave byte of “1101111x” and reads or writes to addresses
[0000h:003Fh]. The clock/control memory map has memory
addresses from 0000h to 003Fh. The defined addresses are
described in the Table 1. Writing to and reading from the
undefined addresses are not recommended.
CCR Access
Reading the Real Time Clock
The RTC is read by initiating a Read command and specifying
the address corresponding to the register of the Real Time
Clock. The RTC Registers can then be read in a Sequential
Read Mode. Since the clock runs continuously and a read takes
a finite amount of time, there is the possibility that the clock
could change during the course of a read operation. In this
device, the time is latched by the read command (falling edge of
the clock on the ACK bit prior to RTC data output) into a
separate latch to avoid time changes during the read operation.
The clock continues to run. Alarms occurring during a read are
unaffected by the read operation.
Writing to the Real Time Clock
The time and date may be set by writing to the RTC registers.
RTC Register should be written ONLY with Page Write. To
avoid changing the current time by an incomplete write
operation, write to the all 8 bytes in one write operation. When
writing the RTC registers, the new time value is loaded into a
separate buffer at the falling edge of the clock during the
Acknowledge. This new RTC value is loaded into the RTC
Register by a stop bit at the end of a valid write sequence. An
invalid write operation aborts the time update procedure and
the contents of the buffer are discarded. After a valid write
operation, the RTC will reflect the newly loaded data beginning
with the next “one second” clock cycle after the stop bit is
written. The RTC continues to update the time while an RTC
FN8231 Rev 9.00
November 30, 2010
The contents of the CCR can be modified by performing a byte
or a page write operation directly to any address in the CCR.
Prior to writing to the CCR (except the status register),
however, the WEL and RWEL bits must be set using a three
step process (see “Writing to the Clock/Control Registers” on
page 12).
The CCR is divided into 5 sections. These are:
1. Alarm 0 (8 bytes; non-volatile)
2. Alarm 1 (8 bytes; non-volatile)
3. Control (5 bytes; non-volatile)
4. Real Time Clock (8 bytes; volatile)
5. Status (1 byte; volatile)
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write operation
and stop bit. A sequential read or page write operation provides
access to the contents of only one section of the CCR per
operation. Access to another section requires a new operation.
A read or write can begin at any address in the CCR.
It is not necessary to set the RWEL bit prior to writing the
status register. See “Status Register (SR)” on page 9. supports
a single byte read or write only. Continued reads or writes from
this section terminates the operation.
Page 8 of 24
ISL12026, ISL12026A
The state of the CCR can be read by performing a random
read at any address in the CCR at any time. This returns the
contents of that register location. Additional registers are read
by performing a sequential read. The read instruction latches
all Clock registers into a buffer, so an update of the clock does
not change the time being read. A sequential read of the CCR
will not result in the output of data from the memory array. At
the end of a read, the master supplies a stop condition to end
the operation and free the bus. After a read of the CCR, the
address remains at the previous address +1 so the user can
execute a current address read of the CCR and continue
reading the next Register.
Real Time Clock Registers
SC, MN, HR, DT, MO, YR: Clock/Calendar Registers
These registers depict BCD representations of the time. As
such, SC (Seconds) and MN (Minutes) range from 00 to 59,
HR (Hour) is 1 to 12 with an AM or PM indicator (H21 bit) or 0
to 23 (with MIL = 1), DT (Date) is 1 to 31, MO (Month) is 1 to
12, YR (Year) is 0 to 99.
DW: Day of the Week Register
This register provides a Day of the Week status and uses three
bits DY2 to DY0 to represent the seven days of the week. The
counter advances in the cycle 0-1-2-3-4-5-6-0-1-2-… The
assignment of a numerical value to a specific day of the week
is arbitrary and may be decided by the system software
designer. The default value is defined as ‘0’.
24 Hour Time
If the MIL bit of the HR register is 1, the RTC uses a 24-hour
format. If the MIL bit is 0, the RTC uses a 12-hour format and H21
bit functions as an AM/PM indicator with a ‘1’ representing PM.
The clock defaults to standard time with H21 = 0.
Leap Years
Leap years add the day February 29 and are defined as those
years that are divisible by 4.
Status Register (SR)
The Status Register is located in the CCR memory map at
address 003Fh. This is a volatile register only and is used to
control the WEL and RWEL write enable latches, read power
status and two alarm bits. This register is separate from both
the array and the Clock/Control Registers (CCR).
TABLE 1. STATUS REGISTER (SR)
ADDR
7
6
003Fh
BAT
AL1
Default
0
0
5
4
AL0 OSCF
0
0
3
2
1
0
0
RWEL
WEL
RTCF
0
0
0
1
AL1, AL0: Alarm Bits - Volatile
These bits announce if either alarm 0 or alarm 1 match the real
time clock. If there is a match, the respective bit is set to ‘1’.
The falling edge of the last data bit in a SR Read operation
resets the flags. Note: Only the AL bits that are set when an SR
read starts will be reset. An alarm bit that is set by an alarm
occurring during an SR read operation will remain set after the
read operation is complete.
OSCF: Oscillator Fail Indicator
This bit is set to “1” if the oscillator is not operating, or is
operating, but has clock jitter which does not affect the
accuracy of RTC counting. The bit is set to “0” if the oscillator is
functioning, and does not have clock jitter. This bit is read only,
and is set/reset by hardware.
RWEL: Register Write Enable Latch - Volatile
This bit is a volatile latch that powers up in the LOW (disabled)
state. The RWEL bit must be set to “1” prior to any writes to the
Clock/Control Registers. Writes to RWEL bit do not cause a
non-volatile write cycle, so the device is ready for the next
operation immediately after the stop condition. A write to the
CCR requires both the RWEL and WEL bits to be set in a
specific sequence.
WEL: Write Enable Latch - Volatile
The WEL bit controls the access to the CCR during a write
operation. This bit is a volatile latch that powers up in the LOW
(disabled) state. While the WEL bit is LOW, writes to the CCR
address will be ignored, although acknowledgment is still issued.
The WEL bit is set by writing a “1” to the WEL bit and zeroes to
the other bits of the Status Register. Once set, WEL remains set
until either reset to 0 (by writing a “0” to the WEL bit and zeroes
to the other bits of the Status Register) or until the part powers
up again. Writes to WEL bit do not cause a non-volatile write
cycle, so the device is ready for the next operation immediately
after the stop condition.
RTCF: Real Time Clock Fail Bit - Volatile
This bit is set to a “1” after a total power failure. This is a read
only bit that is set by hardware (ISL12026 internally) when the
device powers up after having lost all power to the device (both
VDD and VBAT go to 0V). The bit is set regardless of whether
VDD or VBAT is applied first. The loss of only one of the
supplies does not set the RTCF bit to “1”. On power-up after a
total power failure, all registers are set to their default states
and the clock will not increment until at least one byte is written
to the clock register. The first valid write to the RTC section
after a complete power failure resets the RTCF bit to “0”
(writing one byte is sufficient).
Unused Bits
BAT: Battery Supply - Volatile
This bit set to “1” indicates that the device is operating from
VBAT, not VDD. It is a read-only bit and is set/reset by hardware
(ISL12026 internally). Once the device begins operating from
VDD, the device sets this bit to “0”.
FN8231 Rev 9.00
November 30, 2010
Bit 3 in the SR is not used, but must be zero. The Data Byte
output during a SR read will contain a zero in this bit location.
Page 9 of 24
ISL12026, ISL12026A
ADDR.
TYPE
003F
0037
0036
REG NAME
7
6
Status
SR
BAT
AL1
AL0
RTC
(SRAM)
Y2K
0
0
Y2K21
5
4
3
2
1
0
OSCF
0
RWEL
WEL
RTCF
Y2K20
Y2K13
0
0
Y2K10
RANGE
ISL12026
DEFAULT
BIT
ISL12026A
DEFAULT
TABLE 2. CLOCK/CONTROL MEMORY MAP
01h
01h
19/20
20h
20h
DW
0
0
0
0
0
DY2
DY1
DY0
0-6
00h
00h
0035
YR
Y23
Y22
Y21
Y20
Y13
Y12
Y11
Y10
0-99
00h
00h
0034
MO
0
0
0
G20
G13
G12
G11
G10
1-12
00h
00h
0033
DT
0
0
D21
D20
D13
D12
D11
D10
1-31
01h
01h
0032
HR
MIL
0
H21
H20
H13
H12
H11
H10
0-23
00h
00h
0031
MN
0
M22
M21
M20
M13
M12
M11
M10
0-59
00h
00h
0030
SC
0
S22
S21
S20
S13
S12
S11
S10
0-59
00h
00h
PWR
SBIB
BSW
0
0
0
0
0
0
40h
00h
DTR
0
0
0
0
0
DTR2
DTR1
DTR0
00h
00h
0014
0013
Control
(EEPROM)
0012
ATR
0
0
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
00h
00h
0011
INT
IM
AL1E
AL0E
FO1
FO0
0
0
0
00h
00h
BP0
0
0
0010
000F
000E
Alarm1
(EEPROM)
BL
BP2
BP1
Y2K1
0
0
DWA1
EDW1
000D
YRA1
000C
MOA1
0
0
0
0
00h
00h
0
0
A1Y2K10
19/20
20h
20h
DY2
DY1
DY0
0-6
00h
00h
1-12
00h
00h
A1Y2K21 A1Y2K20 A1Y2K13
0
0
0
Unused - Default = RTC Year value (No EEPROM) - Future expansion
EMO1
0
0
A1G20
A1G13
A1G12
A1G11
A1G10
000B
DTA1
EDT1
0
A1D21
A1D20
A1D13
A1D12
A1D11
A1D10
1-31
00h
00h
000A
HRA1
EHR1
0
A1H21
A1H20
A1H13
A1H12
A1H11
A1H10
0-23
00h
00h
0009
MNA1
EMN1
A1M22
A1M21
A1M20
A1M13
A1M12 A1M11
A1M10
0-59
00h
00h
0008
SCA1
ESC1
A1S22
A1S21
A1S20
A1S13
A1S12
A1S11
A1S10
0-59
00h
00h
0
0
A0Y2K10
19/20
20h
20h
DY2
DY1
DY0
0-6
00h
00h
1-12
00h
00h
0007
0006
Alarm0
(EEPROM)
Y2K0
0
0
DWA0
EDW0
0
0005
YRA0
0004
MOA0
A0Y2K21 A0Y2K20 A0Y2K13
0
0
0
Unused - Default = RTC Year value (No EEPROM) - Future expansion
EMO0
0
0
A0G20
A0G13
A0G12
A0G11
A0G10
0003
DTA0
EDT0
0
A0D21
A0D20
A0D13
A0D12
A0D11
A0D10
1-31
00h
00h
0002
HRA0
EHR0
0
A0H21
A0H20
A0H13
A0H12
A0H11
A0H10
0-23
00h
00h
0001
MNA0
EMN0
A0M22
A0M21
A0M20
A0M13
A0M12 A0M11
A0M10
0-59
00h
00h
0000
SCA0
ESC0
A0S22
A0S21
A0S20
A0S13
A0S12
A0S10
0-59
00h
00h
Alarm Registers (Non-Volatile)
Alarm0 and Alarm1
A0S11
See “Device Operation” on page 12 and “Application Section”
on page 19 for more information.
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make the
comparison. Note that there is no alarm byte for year.
Control Registers (Non-Volatile)
The alarm function works as a comparison between the alarm
registers and the RTC registers. As the RTC advances, the
alarm will be triggered once a match occurs between the alarm
registers and the RTC registers. Any one alarm register,
multiple registers, or all registers can be enabled for a match.
BP2, BP1, BP0 - Block Protect Bits
FN8231 Rev 9.00
November 30, 2010
The Control Bits and Registers described in the following are
non-volatile.
BL Register
The Block Protect Bits, BP2, BP1 and BP0, determine which
blocks of the array are write protected. A write to a protected block
of memory is ignored. The block protect bits will prevent write
operations to one of eight segments of the array. The partitions
are described in Table 3.
Page 10 of 24
ISL12026, ISL12026A
Oscillator Compensation Registers
TABLE 3.
BP2
BP1
BP0
There are two trimming options.
PROTECTED ADDRESSES
ISL12026
0
0
0
None (Default)
None
0
0
1
180h – 1FFh
Upper 1/4
0
1
0
100h – 1FFh
Upper 1/2
0
1
1
000h – 1FFh
Full Array
1
0
0
000h – 03Fh
First 4 Pages
1
0
1
000h – 07Fh
First 8 Pages
1
1
0
000h – 0FFh
First 16 Pages
1
1
1
000h – 1FFh
Full Array
ARRAY LOCK
INT Register: Interrupt Control and
Frequency Output Register
IM, AL1E, AL0E - Interrupt Control and Status Bits
• ATR. Analog Trimming Register
• DTR. Digital Trimming Register
These registers are non-volatile. The combination of analog
and digital trimming can give up to -64 to +110 ppm of total
adjustment.
ATR Register - ATR5, ATR4, ATR3, ATR2, ATR1,
ATR0: Analog Trimming Register
6 analog trimming bits, ATR0 to ATR5, are provided in order to
adjust the on-chip load capacitance value for frequency
compensation of the RTC. Each bit has a different weight for
capacitance adjustment. For example, using a Citizen CFS206 crystal with different ATR bit combinations provides an
estimated ppm adjustment range from -34 to +80ppm to the
nominal frequency compensation.
There are two Interrupt Control bits, Alarm 1 Interrupt Enable
(AL1E) and Alarm 0 Interrupt Enable (AL0E) to specifically
enable or disable the alarm interrupt signal output
(IRQ/FOUT). The interrupts are enabled when either the AL1E
or AL0E or both bits are set to ‘1’ and both the FO1 and FO0
bits are set to 0 (FOUT disabled).
The IM bit enables the pulsed interrupt mode. To enter this
mode, the AL0E or AL1E bits are set to “1”, and the IM bit to “1”.
The IRQ/FOUT output will now be pulsed each time an alarm
occurs. This means that once the interrupt mode alarm is set, it
will continue to alarm for each occurring match of the alarm and
present time. This mode is convenient for hourly or daily
hardware interrupts in microcontroller applications such as
security cameras or utility meter reading.
In the case that both Alarm 0 and Alarm 1 are enabled, the
IRQ/FOUT pin will be pulsed each time either alarm matches
the RTC (both alarms can provide hardware interrupt). If the IM
bit is also set to "1", the IRQ/FOUT will be pulsed for each of the
alarms as well.
FO1, FO0 - Programmable Frequency Output Bits
These are two output control bits. They select one of three
divisions of the internal oscillator, that is applied to the
IRQ/FOUT output pin. Table 4 shows the selection bits for this
output. When using this function, the Alarm output function is
disabled.
X1
CX1
X2
CX2
FIGURE 8. DIAGRAM OF ATR
The effective on-chip series load capacitance, CLOAD, ranges
from 4.5pF to 20.25pF with a mid-scale value of 12.5pF
(default). CLOAD is changed via two digitally controlled
capacitors, CX1 and CX2, connected from the X1 and X2 pins
to ground (see Figure 8). The value of CX1 and CX2 is given by
Equation 1:
C X = 16 b5 + 8 b4 + 4 b3 + 2 b2 + 1 b1 + 0.5 b0 + 9 pF
FO0
OUTPUT FREQUENCY
0
0
Alarm output (FOUT disabled)
0
1
32.768kHz
1
0
4096Hz
1
1
1Hz
FN8231 Rev 9.00
November 30, 2010
(EQ. 1)
The effective series load capacitance is the combination of CX1
and CX2:
C
LOAD
1
1
1
---------- + -----------
C
C
= ----------------------------------X1
TABLE 4. PROGRAMMABLE FREQUENCY OUTPUT BITS
FO1
CRYSTAL
OSCILLATOR
C
LOAD
X2
16 b5 + 8 b4 + 4 b3 + 2 b2 + 1 b1 + 0.5 b0 + 9
= ----------------------------------------------------------------------------------------------------------------------------- pF
2
(EQ. 2)
For example, CLOAD(ATR = 00000) = 12.5pF, CLOAD
(ATR = 100000) = 4.5pF, and CLOAD(ATR = 011111) = 20.25pF.
The entire range for the series combination of load capacitance
goes from 4.5pF to 20.25pF in 0.25pF steps. Note that these are
typical values.
Page 11 of 24
ISL12026, ISL12026A
DTR Register - DTR2, DTR1, DTR0: Digital Trimming
Register
The digital trimming Bits DTR2, DTR1 and DTR0 adjust the
number of counts per second and average the ppm error to
achieve better accuracy.
DTR2 is a sign bit. DTR2 = 0 means frequency compensation
is > 0. DTR2 = 1 means frequency compensation is < 0.
DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm
adjustment and DTR0 gives 20 ppm adjustment.
A range from -30ppm to +30ppm can be represented by using
the three DTR bits.
TABLE 5. DIGITAL TRIMMING REGISTERS
DTR REGISTER
DTR2
DTR1
DTR0
ESTIMATED FREQUENCY
PPM
0
0
0
0
0
1
0
+10
0
0
1
+20
0
1
1
+30
1
0
0
0
1
1
0
-10
1
0
1
-20
1
1
1
-30
PWR Register: SBIB, BSW
SBIB: - Serial Bus Interface (Enable)
The serial bus can be disabled in battery backup mode by
setting this bit to “1”. This will minimize power drain on the
battery. The Serial Interface can be enabled in battery backup
mode by setting this bit to “0”. (default is “0”). See “BSW:
Power Control Bit” on page 12.
BSW: Power Control Bit
The Power Control bit, BSW, determines the conditions for
switching between VDD and Backup Battery. There are two
options.
Option 1. Standard Mode: Set “BSW = 0”
Option 2. Legacy Mode: Set “BSW = 1”
See “Power Control Operation” on page 13 for more details.
Also see “I2C Communications During Battery Backup” on
page 22 for important details.
TABLE 6. VBAT TRIP POINT WITH DIFFERENT BSW SETTING
BSW BIT
VBAT TRIP POINT
(V)
0
2.2
1
VDD < VBAT
FN8231 Rev 9.00
November 30, 2010
POWER CONTROL SETTING
Standard Mode (ISL12026A)
Legacy Mode (ISL12026)
Device Operation
Writing to the Clock/Control Registers
Changing any of the bits of the clock/control registers requires
the following steps:
1. Write a 02h to the Status Register to set the Write Enable
Latch (WEL). This is a volatile operation, so there is no
delay after the write (operation preceded by a start and
ended with a stop).
2. Write a 06h to the Status Register to set both the Register
Write Enable Latch (RWEL) and the WEL bit. This is also a
volatile cycle. The zeros in the data byte are required
(operation proceeded by a start and ended with a stop).
Write all 8 bytes to the RTC registers, or one byte to the SR, or
one to five bytes to the control registers. This sequence starts
with a start bit, requires a slave byte of “11011110” and an
address within the CCR and is terminated by a stop bit. A write
to the EEPROM registers in the CCR will initiate a non-volatile
write cycle and will take up to 20ms to complete. A write to the
RTC registers (SRAM) will require much shorter cycle time (t =
tBUF). Writes to undefined areas have no effect. The RWEL bit
is reset by the completion of a write to the CCR, so the
sequence must be repeated to again initiate another change to
the CCR contents. If the sequence is not completed for any
reason (by sending an incorrect number of bits or sending a
start instead of a stop, for example), the RWEL bit is not reset
and the device remains in an active mode. Writing all zeros to
the status register resets both the WEL and RWEL bits. A read
operation occurring between any of the previous operations
will not interrupt the register write operation.
Alarm Operation
Since the alarm works as a comparison between the alarm
registers and the RTC registers, it is ideal for notifying a host
processor of a particular time event, which triggers some
action as a result. The host can be notified by either a
hardware interrupt (the IRQ/FOUT pin) or by polling the Status
Register (SR) Alarm bits. These two volatile bits (AL1for Alarm
1 and AL0 for Alarm 0), indicate if an alarm has happened. The
bits are set on an alarm condition regardless of whether the
IRQ/FOUT interrupt is enabled. The AL1 and AL0 bits in the
status register are reset by the falling edge of the eighth clock
of status register read.
There are two alarm operation modes: Single Event and
periodic Interrupt Mode:
1. Single Event Mode is enabled by setting the AL0E or AL1E
bit to “1”, the IM bit to “0”, and disabling the frequency
output. This mode permits a one-time match between the
alarm registers and the RTC registers. Once this match
occurs, the AL0 or AL1 bit is set to “1” and the IRQ/FOUT
output will be pulled low and will remain low until the AL0 or
AL1 bit is read, which will automatically resets it. Both Alarm
registers can be set at the same time to trigger alarms. The
IRQ/FOUT output will be set by either alarm, and will need
to be cleared to enable triggering by a subsequent alarm.
Polling the SR will reveal which alarm has been set.
Page 12 of 24
ISL12026, ISL12026A
2. Interrupt Mode (or “Pulsed Interrupt Mode” or PIM) is
enabled by setting the AL0E or AL1E bit to “1” the IM bit to
“1”, and disabling the frequency output. If both AL0E and
AL1E bits are set to "1", then both AL0E and AL1E PIM
alarms will function. The IRQ/FOUT output will now be
pulsed each time each of the alarms occurs. This means
that once the interrupt mode alarm is set, it will continue to
alarm for each occurring match of the alarm and present
time. This mode is convenient for hourly or daily hardware
interrupts in microcontroller applications such as security
cameras or utility meter reading. Interrupt Mode CANNOT
be used for general periodic alarms, however, since a
specific time period cannot be programmed for interrupt,
only matches to a specific time of day. The interrupt mode
is only stopped by disabling the IM bit or the Alarm Enable
bits.
Writing to the Alarm Registers
The Alarm Registers are non-volatile but require special attention
to insure a proper non-volatile write takes place. Specifically, byte
writes to individual registers are good for all but registers 0006h
and 0000Eh, which are the DWA0 and DWA1 registers,
respectively. Those registers will require a special page write for
non-volatile storage. The recommended page write sequences
are as follows:
1. 16-byte page writes: The best way to write or update the
Alarm Registers is to perform a 16-byte write beginning at
address 0001h (MNA0) and wrapping around and ending at
address 0000h (SCA0). This will insure that non-volatile
storage takes place. This means that the code must be
designed so that the Alarm0 data is written starting with
Minutes register, and then all the Alarm1 data, with the last
byte being the Alarm0 Seconds (the page ends at the
Alarm1 Y2k register and then wraps around to address
0000h).
Alternatively, the 16-byte page write could start with
address 0009h, wrap around and finish with address
0008h. Note that any page write ending at address 0007h
or 000Fh (the highest byte in each Alarm) will not trigger a
non-volatile write, so wrapping around or overlapping to
the following Alarm's Seconds register is advised.
2. Other non-volatile writes: It is possible to do writes of less
than an entire page, but the final byte must always be
addresses 0000h through 0004h or 0008h though 000Ch to
trigger a non-volatile write. Writing to those blocks of
5 bytes sequentially, or individually, will trigger a
non-volatile write. If the DWA0 or DWA1 registers need to
be set, then enough bytes will need to be written to overlap
with the other Alarm register and trigger the non-volatile
write. For Example, if the DWA0 register is being set, then
the code can start with a multiple byte write beginning at
address 0006h, and then write 3 bytes ending with the
SCA1 register as follows:
Addr
0006h
0007h
0008h
Name
DWA0
Y2K0
SCA1
FN8231 Rev 9.00
November 30, 2010
If the Alarm1 is used, SCA1 would need to have the correct
data written.
Power Control Operation
The power control circuit accepts a VDD and a VBAT input.
Many types of batteries can be used with Intersil RTC
products. For example, 3.0V or 3.6V Lithium batteries are
appropriate, and battery sizes are available that can power an
Intersil RTC device for up to 10 years. Another option is to use
a SuperCap for applications where VDD is interrupted for up to
a month. See “Application Section” on page 19 for more
information.
There are two options for setting the change-over conditions
from VDD to Battery backup mode. The BSW bit in the PWR
register controls this operation:
•
Option 1 - Standard Mode (ISL12026A Default)
•
Option 2 - Legacy Mode (ISL12026 Default)
Note that the I2C bus may or may not be operational during
battery backup. That function is controlled by the SBIB bit. That
operation is covered after the power control section.
OPTION 1- STANDARD POWER CONTROL MODE
(ISL12026A DEFAULT)
In the Standard mode, the supply will switch over to the battery
when VDD drops below VTRIP or VBAT, whichever is lower. In
this mode, accidental operation from the battery is prevented
since the battery backup input will only be used when the VDD
supply is shut off.
To select Option 1, BSW bit in the Power Register must be set
to “BSW = 0”. A description of power switchover follows.
Standard Mode Power Switchover
• Normal Operating Mode (VDD) to Battery Backup Mode
(VBAT)
To transition from the VDD to VBAT mode, both of the following
conditions must be met:
- Condition 1:
VDD < VBAT - VBATHYS
where VBATHYS 50mV
- Condition 2:
VDD < VTRIP
where VTRIP 2.2V
• Battery Backup Mode (VBAT) to Normal Mode (VDD)
The ISL12026 device will switch from the VBAT to VDD mode
when one of the following conditions occurs:
- Condition 1:
VDD > VBAT + VBATHYS
where VBATHYS 50mV
- Condition 2:
VDD > VTRIP + VTRIPHYS
where VTRIPHYS 30mV
Page 13 of 24
ISL12026, ISL12026A
There are two discrete situations that are possible when using
Standard Mode: VBAT < VTRIP and VBAT > VTRIP. These two
power control situations are illustrated in Figures 9 and 10.
The Legacy Mode power control conditions are illustrated in
Figure 11.
VDD
VOLTAGE
BATTERY BACKUP
MODE
VDD
ON
VBAT
In
Off
VTRIP
2.2V
VBAT
1.8V
FIGURE 11. BATTERY SWITCHOVER IN LEGACY MODE
VBAT + VBATHYS
VBAT - VBATHYS
FIGURE 9. BATTERY SWITCHOVER WHEN VBAT < VTRIP
Serial Communication
The device supports the I2C protocol.
Clock and Data
Data states on the SDA line can change only during SCL LOW.
SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions (see Figure 12).
BATTERY BACKUP
MODE
VDD
VBAT
3.0V
VTRIP
2.2V
VTRIP
VTRIP + VTRIPHYS
FIGURE 10. BATTERY SWITCHOVER WHEN VBAT > VTRIP
OPTION 2 -LEGACY POWER CONTROL MODE (ISL12026
DEFAULT)
The Legacy Mode follows conditions set in X1226 products. In
this mode, switching from VDD to VBAT is simply done by
comparing the voltages and the device operates from whichever
is the higher voltage. Care should be taken when changing from
Normal to Legacy Mode. If the VBAT voltage is higher than VDD,
then the device will enter battery back up and unless the battery
is disconnected or the voltage decreases, the device will no
longer operate from VDD.
To select the Option 2, BSW bit in the Power Register must be
set to “BSW = 1”
• Normal Mode (VDD) to Battery Backup Mode (VBAT)
To transition from the VDD to VBAT mode, the following
conditions must be met:
VDD < VBAT - VBATHYS
• Battery Backup Mode (VBAT) to Normal Mode (VDD)
The device will switch from the VBAT to VDD mode when the
following condition occurs:
Start Condition
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until this
condition has been met (see Figure 13).
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is HIGH.
The stop condition is also used to place the device into the
Standby power mode after a read sequence. A stop condition
can only be issued after the transmitting device has released
the bus (see Figure 13).
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either master
or slave, will release the bus after transmitting 8 bits. During
the ninth clock cycle, the receiver will pull the SDA line LOW to
acknowledge that it received the 8 bits of data (see Figure 14).
The device will respond with an acknowledge after recognition
of a start condition and if the correct Device Identifier and
Select bits are contained in the Slave Address Byte. If a write
operation is selected, the device will respond with an
acknowledge after the receipt of each subsequent 8-bit word.
The device will not acknowledge if the slave address byte is
incorrect.
VDD > VBAT +VBATHYS
FN8231 Rev 9.00
November 30, 2010
Page 14 of 24
ISL12026, ISL12026A
SCL
SDA
DATA STABLE
DATA CHANGE
DATA STABLE
FIGURE 12. VALID DATA CHANGES ON THE SDA BUS
SCL
SDA
START
STOP
FIGURE 13. VALID START AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 14. ACKNOWLEDGE RESPONSE FROM RECEIVER
In the read mode, the device will transmit 8 bits of data, release
the SDA line, then monitor the line for an acknowledge. If an
acknowledge is detected and no stop condition is generated by
the master, the device will continue to transmit data. The
device will terminate further data transmissions if an
acknowledge is not detected. The master must then issue a
stop condition to return the device to Standby mode and place
the device into a known state.
Device Addressing
Following a start condition, the master must output a Slave
Address Byte. The first 4 bits of the Slave Address Byte specify
access to either the EEPROM array or to the CCR. Slave bits
‘1010’ access the EEPROM array. Slave bits ‘1101’ access the
CCR.
Bit 3 through Bit 1 of the slave byte specifies the device select
bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the operation to
be performed. When this R/W bit is a one, then a read
operation is selected. A zero selects a write operation
(see Figure 15).
After loading the entire Slave Address Byte from the SDA bus,
the ISL12026 compares the device identifier and device select
bits with ‘1010111’ or ‘1101111’. Upon a correct compare, the
device outputs an acknowledge on the SDA line.
When shipped from the factory, EEPROM array is
UNDEFINED, and should be programmed by the customer to a
known state.
FN8231 Rev 9.00
November 30, 2010
Page 15 of 24
ISL12026, ISL12026A
DEVICE IDENTIFIER
ARRAY
1
1
CCR
SLAVE ADDRESS BYTE
BYTE 0
0
1
1
0
0
1
1
1
1
R/W
0
0
0
0
0
0
0
A8
WORD ADDRESS 1
BYTE 1
A7
A6
A5
A4
A3
A2
A1
A0
WORD ADDRESS 0
BYTE 2
D7
D6
D5
D4
D3
D2
D1
D0
DATA BYTE
BYTE 3
FIGURE 15. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES (16 BYTE PAGES)
SIGNALS FROM
THE MASTER
SDA BUS
SIGNALS FROM
THE SLAVE
S
T
A
R
T
WORD
ADDRESS 1
SLAVE
ADDRESS
1
WORD
ADDRESS 0
S
T
O
P
DATA
0000000
1 110
A
C
K
A
C
K
A
C
K
A
C
K
FIGURE 16. BYTE WRITE SEQUENCE
Following the Slave Byte is a two byte word address. The word
address is either supplied by the master device or obtained
from an internal counter. On power up the internal address
counter is set to address 0h, so a current address read of the
EEPROM array starts at address 0. When required, as part of
a random read, the master must supply the 2 Word Address
Bytes as shown in Figure 15.
In a random read operation, the slave byte in the “dummy
write” portion must match the slave byte in the “read” section.
That is if the random read is from the array the slave byte must
be 1010111x in both instances. Similarly, for a random read of
the Clock/Control Registers, the slave byte must be 1101111x
in both places.
Write Operations
Byte Write
For a write operation, the device requires the Slave Address
Byte and the Word Address Bytes. This gives the master
access to any one of the words in the array or CCR. (Note:
Prior to writing to the CCR, the master must write a 02h, then
06h to the status register in two preceding operations to enable
the write operation. See “Writing to the Clock/Control
Registers” on page 12). Upon receipt of each address byte, the
ISL12026 responds with an acknowledge. After receiving both
FN8231 Rev 9.00
November 30, 2010
address bytes the ISL12026 awaits the 8 bits of data. After
receiving the 8 data bits, the ISL12026 again responds with an
acknowledge. The master then terminates the transfer by
generating a stop condition. The ISL12026 then begins an
internal write cycle of the data to the non-volatile memory.
During the internal write cycle, the device inputs are disabled,
so the device will not respond to any requests from the master.
The SDA output is at high impedance (see Figure 16).
A write to a protected block of memory is ignored, but will still
receive an acknowledge. At the end of the write command, the
ISL12026 will not initiate an internal write cycle, and will
continue to ACK commands.
Byte writes to all of the non-volatile registers are allowed,
except the DWAn registers which require multiple byte writes
or page writes to trigger non-volatile writes. See “Device
Operation” on page 12 for more information.
Page Write
The ISL12026 has a page write operation. It is initiated in the
same manner as the byte write operation; but instead of
terminating the write cycle after the first data byte is
transferred, the master can transmit up to 15 more bytes to the
memory array and up to 7 more bytes to the clock/control
registers. The RTC registers require a page write (8 bytes),
individual register writes are not allowed. (Note: Prior to writing
Page 16 of 24
ISL12026, ISL12026A
to the CCR, the master must write a 02h, then 06h to the status
register in two preceding operations to enable the write
operation. See “Writing to the Clock/Control Registers” on
page 12).
After the receipt of each byte, the ISL12026 responds with an
acknowledge, and the address is internally incremented by
one. The address pointer remains at the last address byte
written. When the counter reaches the end of the page, it “rolls
over” and goes back to the first address on the same page.
This means that the master can write 16 bytes to a memory
array page or 8 bytes to a CCR section starting at any location
on that page. For example, if the master begins writing at
location 10 of the memory and loads 15 bytes, then the first 6
bytes are written to addresses 10 through 15, and the last 6
bytes are written to columns 0 through 5. Afterwards, the
address counter would point to location 6 on the page that was
just written. If the master supplies more than the maximum
SIGNALS FROM
THE MASTER
Stops and Write Modes
Stop conditions that terminate write operations must be sent by
the master after sending at least 1 full data byte and it’s
associated ACK signal. If a stop is issued in the middle of a
data byte, or before 1 full data byte + ACK is sent, then the
ISL12026 resets itself without performing the write. The
contents of the array are not affected.
1 N 16 FOR EEPROM ARRAY
1 N 8 FOR CCR
S
T
A
R
T
SDA BUS
bytes in a page, then the previously loaded data is over-written
by the new data, one byte at a time. Refer to Figure 18. The
master terminates the Data Byte loading by issuing a stop
condition, which causes the ISL12026 to begin the non-volatile
write cycle. As with the byte write operation, all inputs are
disabled until completion of the internal write cycle. Refer to
Figure 17 for the address, acknowledge, and data transfer
sequence.
WORD
ADDRESS 1
SLAVE
ADDRESS
1
DATA
(1)
S
T
O
P
DATA
(n)
0 0 0 00 0 0
1 1 1 0
A
C
K
SIGNALS FROM
THE SLAVE
WORD
ADDRESS 0
A
C
K
A
C
K
A
C
K
FIGURE 17. PAGE WRITE SEQUENCE
6 BYTES
6 BYTES
ADDRESS = 5
ADDRESS
ADDRESS
ADDRESS POINTER ENDS
AT ADDR = 5
10
15
FIGURE 18. WRITING 12 BYTES TO A 16-BYTE MEMORY PAGE STARTING AT ADDRESS 10
FN8231 Rev 9.00
November 30, 2010
Page 17 of 24
ISL12026, ISL12026A
Acknowledge Polling
Disabling of the inputs during non-volatile write cycles can be
used to take advantage of the 12ms (typ) write cycle time.
Once the stop condition is issued to indicate the end of the
master’s byte load operation, the ISL12026 initiates the
internal non-volatile write cycle. Acknowledge polling can
begin immediately. To do this, the master issues a start
condition followed by the Memory Array Slave Address Byte for
a write or read operation (AEh or AFh). If the ISL12026 is still
busy with the non-volatile write cycle then no ACK will be
returned. When the ISL12026 has completed the write
operation, an ACK is returned and the host can proceed with
the read or write operation. Refer to the flow chart in Figure 20.
Note: Do not use the CCR Slave byte (DEh or DFh) for
Acknowledge Polling.
Read Operations
There are three basic read operations: Current Address Read,
Random Read and Sequential Read.
Current Address Read
Internally the ISL12026 contains an address counter that
maintains the address of the last word read incremented by
one. Therefore, if the last read was to address n, the next read
operation would access data from address n + 1. On power-up,
the 16-bit address is initialized to 00h. In this way, a current
address read immediately after the power on reset can
download the entire contents of memory starting at the first
location. Upon receipt of the Slave Address Byte with the R/W
bit set to one, the ISL12026 issues an acknowledge, then
transmits 8 data bits. The master terminates the read operation
by not responding with an acknowledge during the ninth clock
and issuing a stop condition. Refer to Figure 19 for the
address, acknowledge, and data transfer sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read operation,
the master must either issue a stop condition during the ninth
cycle or hold SDA HIGH during the ninth clock cycle and then
issue a stop condition.
Random Read
Random read operations allow the master to access any
location in the ISL12026. Prior to issuing the Slave Address
Byte with the R/W bit set to zero, the master must first perform
a “dummy” write operation.
The master issues the start condition and the slave address
byte, receives an acknowledge, then issues the word address
bytes. After acknowledging receipt of each word address byte,
the master immediately issues another start condition and the
slave address byte with the R/W bit set to one. This is followed
by an acknowledge from the device and then by the 8-bit data
word. The master terminates the read operation by not
responding with an acknowledge and then issuing a stop
condition. Refer to Figure 21 for the address, acknowledge and
data transfer sequence.
FN8231 Rev 9.00
November 30, 2010
In a similar operation called “Set Current Address,” the device
sets the address if a stop is issued instead of the second start
shown in Figure 21. The ISL12026 then goes into standby
mode after the stop and all bus activity will be ignored until a
start is detected. This operation loads the new address into the
address counter. The next Current Address Read operation will
read from the newly loaded address. This operation could be
useful if the master knows the next address it needs to read,
but is not ready for the data.
SIGNALS FROM
THE MASTER
SDA BUS
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
1
1 1 1 1
A
C
K
SIGNALS FROM
THE SLAVE
DATA
FIGURE 19. CURRENT ADDRESS READ SEQUENCE
BYTE LOAD
COMPLETED BY
ISSUING STOP.
ENTER ACK POLLING
ISSUE START
ISSUE MEMORY ARRAY SLAVE
ADDRESS BYTE
AFH (READ) OR AEH (WRITE)
ISSUE STOP
NO
ACK
RETURNED?
YES
NON-VOLATILE WRITE
CYCLE COMPLETE. CONTINUE
COMMAND SEQUENCE?
NO
ISSUE STOP
YES
CONTINUE
NORMAL READ OR
WRITE COMMAND
SEQUENCE
PROCEED
FIGURE 20. ACKNOWLEDGE POLLING SEQUENCE
Page 18 of 24
ISL12026, ISL12026A
SIGNALS FROM
THE MASTER
SDA BUS
S
T
A
R
T
SLAVE
ADDRESS
1
1 1 11
A
C
K
A
C
K
A
C
K
S
T
O
P
SLAVE
ADDRESS
1
00 00000
A
C
K
SIGNALS FROM
THE SLAVE
WORD
ADDRESS 0
WORD
ADDRESS 1
1 1 1 0
S
T
A
R
T
DATA
FIGURE 21. RANDOM ADDRESS READ SEQUENCE
SIGNALS FROM
THE MASTER
SDA BUS
SIGNALS FROM
THE SLAVE
SLAVE
ADDRESS
A
C
K
A
C
K
S
T
O
P
A
C
K
1
A
C
K
DATA
(1)
DATA
(2)
DATA
(n-1)
DATA
(n)
(n is any integer greater than 1)
FIGURE 22. SEQUENTIAL READ SEQUENCE
Sequential Read
Sequential reads can be initiated as either a current address
read or random address read. The first data byte is transmitted
as with the other modes; however, the master now responds
with an acknowledge, indicating it requires additional data. The
device continues to output data for each acknowledge received.
The master terminates the read operation by not responding
with an acknowledge and then issuing a stop condition.
The data output is sequential, with the data from address n
followed by the data from address n + 1. The address counter
for read operations increments through all page and column
addresses, allowing the entire memory contents to be serially
read during one operation. At the end of the address space,
the counter “rolls over” to the start of the address space, and
the ISL12026 continues to output data for each acknowledge
received. Refer to Figure 22 for the acknowledge and data
transfer sequence.
Application Section
The Intersil RTC family uses an oscillator circuit with on-chip
crystal compensation network, including adjustable
load-capacitance. The only external component required is the
crystal. The compensation network is optimized for operation
with certain crystal parameters which are common in many of
the surface mount or tuning-fork crystals available today. Table
7 summarizes these parameters.
TABLE 7. CRYSTAL PARAMETERS REQUIRED FOR INTERSIL
RTCs
PARAMETER
MIN
Frequency
TYP
32.768
Frequency
Tolerance
Turnover
Temperature
20
Operating Temp
Range
-40
Crystal Oscillator and Temperature Compensation
Parallel Load
Capacitance
Intersil has now integrated the oscillator compensation circuity
on-chip, to eliminate the need for external components and
adjust for crystal drift over temperature and enable very high
accuracy time keeping (110ppm
occurs at the temperature extremes of -40°C and +85°C. It is
possible to address this variable drift by adjusting the load
capacitance of the crystal, which will result in predictable
change to the crystal frequency. The Intersil RTC family allows
this adjustment over temperature since the devices include onchip load capacitor trimming. This control is handled by the
Analog Trimming Register, or ATR, which has 6-bits of control.
The load capacitance range covered by the ATR circuit is
approximately 3.25pF to 18.75pF, in 0.25pF increments. Note
that actual capacitance would also include about 2pF of
package related capacitance. In-circuit tests with commercially
available crystals demonstrate that this range of capacitance
allows frequency control from +80ppm to -34ppm, using a
12.5pF load crystal.
In addition to the analog compensation afforded by the
adjustable load capacitance, a digital compensation feature is
available for the Intersil RTC family. There are 3-bits known as
the Digital Trimming Register or DTR, and they operate by
adding or skipping pulses in the clock signal. The range
provided is ±30ppm in increments of 10ppm. The default
setting is 0ppm. The DTR control can be used for coarse
adjustments of frequency drift over-temperature or for crystal
initial accuracy correction.
A final application for the ATR control is in-circuit calibration for
high accuracy applications, along with a temperature sensor
chip. Once the RTC circuit is powered up with battery backup,
the IRQ/FOUT output is set at 32.768kHz and frequency drift is
measured. The ATR control is then adjusted to a setting which
minimizes drift. Once adjusted at a particular temperature, it is
possible to adjust at other discrete temperatures for minimal
overall drift, and store the resulting settings in the EEPROM.
Extremely low overall temperature drift is possible with this
method. The Intersil evaluation board contains the circuitry
necessary to implement this control.
The crystal input at X1 has a very high impedance and will pick
up high frequency signals from other circuits on the board.
Since the X2 pin is tied to the other side of the crystal, it is also
a sensitive node. These signals can couple into the oscillator
circuit and produce double clocking or mis-clocking, seriously
affecting the accuracy of the RTC. Care needs to be taken in
layout of the RTC circuit to avoid noise pickup. In Figure 23 is a
suggested layout for the ISL12026 or ISL12027 devices in 8 Ld
SO package.
U1
R5
X1
47k
FIGURE 23. SUGGESTED LAYOUT FOR INTERSIL RTC IN SO-8
The X1 and X2 connections to the crystal are to be kept as
short as possible. A thick ground trace around the crystal is
advised to minimize noise intrusion, but ground near the X1
and X2 pins should be avoided as it will add to the load
capacitance at those pins. Keep in mind these guidelines for
other PCB layers in the vicinity of the RTC device. A small
decoupling capacitor at the VDD pin of the chip is mandatory,
with a solid connection to ground.
The ISL12026 product has a special consideration. The
IRQ/FOUT- pin on the 8 Ld SOIC package is located next to the
X2 pin. When this pin is used as a frequency output (IRQ/
FOUT) and is set to 32.768kHz, noise can couple to the X1 or
X2 pins and cause double-clocking. The layout in Figure 23
minimizes this by running the IRQ/FOUT output away from the
X1 and X2 pins. Also, reducing the switching current at this pin
by careful selection of the pull-up resistor value will reduce
noise. Intersil suggests a minimum value of 5.1k for
32.768kHz, and higher values (up to 20k) for lower frequency
IRQ/FOUT outputs.
For other RTC products, the same rules previously stated
should be observed, but slightly adjusted since the
packages and pinouts are different.
Oscillator Measurements
When a proper crystal is selected and the layout guidelines
above are observed, the oscillator should start-up in most
FN8231 Rev 9.00
November 30, 2010
Page 20 of 24
ISL12026, ISL12026A
circuits in less than one second. Some circuits may take
slightly longer, but start-up should definitely occur in less than
5 seconds. When testing RTC circuits, the most common
impulse is to apply a scope probe to the circuit at the X2 pin
(oscillator output) and observe the waveform. DO NOT DO
THIS! Although in some cases you may see a usable
waveform, due to the parasitics (usually 10pF to ground)
applied with the scope probe, there will be no useful
information in that waveform other than the fact that the circuit
is oscillating. The X2 output is sensitive to capacitive
impedance so the voltage levels and the frequency will be
affected by the parasitic elements in the scope probe. Applying
a scope probe can possibly cause a faulty oscillator to start up,
hiding other issues (although in the Intersil RTCs, the internal
circuitry assures start-up when using the proper crystal and
layout).
The best way to analyze the RTC circuit is to power it up and
read the real time clock as time advances, or if the chip has the
IRQ/FOUT output, look at the output of that pin on an
oscilloscope (after enabling it with the control register, and
using a pull-up resistor for an open-drain output). Alternatively,
the ISL12026 device has an IRQ/FOUT output, which can be
checked by setting an alarm for each minute. Using the pulse
interrupt mode setting, the once-per-minute interrupt functions
as an indication of proper oscillation.
Backup Battery Operation
Many types of batteries can be used with the Intersil RTC
products. 3.0V or 3.6V Lithium batteries are appropriate, and
sizes are available that can power a Intersil RTC device for up
to 10 years. Another option is to use a SuperCap for
applications where VDD may disappear intermittently for short
periods of time. Depending on the value of SuperCap used,
backup time can last from a few days to two weeks (with >1F).
A simple silicon or Schottky barrier diode can be used in series
with VDD to charge the SuperCap, which is connected to the
VBAT pin. Try to use Schottky diodes with very low leakages,
