OBSOLETE PRODUCT
NO RECOMMENDED REPLACEMENT
contact our Technical Support Center at
1-888-INTERSIL or www.intersil.com/tsc
DATASHEET
ISL12027, ISL12027A
FN8232
Rev 9.00
September 23, 2015
Real Time Clock/Calendar with EEPROM
The ISL12027 device is a low power real time clock with
timing and crystal compensation, clock/calender, power-fail
indicator, two periodic or polled alarms, intelligent battery
backup switching, CPU Supervisor and integrated 512x8-bit
EEPROM, in 16 Byte per page format.
Features
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
• Two Non-Volatile Alarms
- Settable on the Second, Minute, Hour, Day of the Week,
Day, or Month
- Repeat Mode (Periodic Interrupts)
The ISL12027 and ISL12027A Power Control Settings are
different. The ISL12027 uses the Legacy Mode Setting, and
the ISL12027A uses the Standard Mode Setting.
Applications that have VBAT > VDD will require only the
ISL12027A. Please refer to“Power Control Operation” on
page 15 for more details. Also, please refer to “I2C
Communications During Battery Backup and LVR Operation”
on page 24 for important details.
Pinouts
VDD
X1
X2
8
SCL
2
7
SDA
3
6
GND
4
5
RESET
1
X2
1
2
• On-Chip Oscillator Compensation
- Internal Feedback Resistor and Compensation
Capacitors
- 64 Position Digitally Controlled Trim Capacitor
- 6 Digital Frequency Adjustment Settings to ±30ppm
• 512x8-Bits of EEPROM
- 16-Byte Page Write Mode (32 total pages)
- 8 Modes of BlockLock™ Protection
- Single Byte Write Capability
• I2C-bus™ Interface
- 400kHz Data Transfer Rate
• 800nA Battery Supply Current
• Package Options
- 8 Ld SOIC and 8 Ld TSSOP Packages
ISL12027, ISL12027A
(8 LD SOIC)
TOP VIEW
X1
• Automatic Backup to Battery or SuperCap
• High Reliability
- Data Retention: 50 years
- Endurance: >2,000,000 Cycles Per Byte
ISL12027, ISL12027A
(8 LD TSSOP)
TOP VIEW
VBAT
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes and Seconds
- Day of the Week, Day, Month and Year
• Pb-Free (RoHS Compliant)
Applications
8
VDD
• Utility Meters
7
VBAT
• HVAC Equipment
• Audio/Video Components
• Modems
RESET
3
6
SCL
GND
4
5
SDA
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
FN8232 Rev 9.00
September 23, 2015
Page 1 of 29
ISL12027, ISL12027A
Pin Descriptions
PIN NUMBER
SOIC
TSSOP
SYMBOL
BRIEF DESCRIPTION
1
3
X1
The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external
32.768kHz quartz crystal. X1 can also be driven directly from a 32.768kHz source.
2
4
X2
The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external
32.768kHz quartz crystal.
3
5
RESET
RESET. This is a reset signal output. This signal notifies a host processor that the “watchdog” time period
has expired or that the voltage has dropped below a fixed VTRIP threshold. It is an open drain active LOW
output. Recommended value for the pull-up resistor is 5k. If unused, connect to ground.
4
6
GND
Ground.
5
7
SDA
Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an
open drain output and may be wire OR’ed with other open drain or open collector outputs.
6
8
SCL
The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on
this pin is always active (not gated).
7
1
VBAT
This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event
that the VDD supply fails. This pin should be tied to ground if not used.
8
2
VDD
Power Supply.
Ordering Information
PART
NUMBER
(Notes 1, 2, 3)
PART
MARKING
VBAT TRIP POINT
(V)
BSW BIT DEFAULT
SETTING
VRESET
VOLTAGE
(V)
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL12027IB27Z
12027 IB27Z
VDD < VBAT
BSW = 1
2.63
-40 to +85
8 Ld SOIC
M8.15
ISL12027IB27AZ
12027 IB27AZ
VDD < VBAT
BSW = 1
2.92
-40 to +85
8 Ld SOIC
M8.15
ISL12027IB30AZ
12027 IB30AZ
VDD < VBAT
BSW = 1
3.09
-40 to +85
8 Ld SOIC
M8.15
ISL12027IBZ
12027 IBZ
VDD < VBAT
BSW = 1
4.38
-40 to +85
8 Ld SOIC
M8.15
ISL12027IBAZ
12027 IBAZ
VDD < VBAT
BSW = 1
4.64
-40 to +85
8 Ld SOIC
M8.15
ISL12027IV27Z
2027 I27Z
VDD < VBAT
BSW = 1
2.63
-40 to +85
8 Ld TSSOP
M8.173
ISL12027IV27AZ
2027 27AZ
VDD < VBAT
BSW = 1
2.92
-40 to +85
8 Ld TSSOP
M8.173
ISL12027IV30AZ
2027 30AZ
VDD < VBAT
BSW = 1
3.09
-40 to +85
8 Ld TSSOP
M8.173
2027 IVZ
ISL12027IVZ (No
longer available or
supported)
VDD < VBAT
BSW = 1
4.38
-40 to +85
8 Ld TSSOP
M8.173
ISL12027IVAZ (No 2027 IVAZ
longer available or
supported)
VDD < VBAT
BSW = 1
4.64
-40 to +85
8 Ld TSSOP
M8.173
12027A IB27Z
ISL12027AIB27Z
(No longer available
or supported)
VDD < VBAT
BSW = 0
2.63
-40 to +85
8 Ld SOIC
M8.15
2027A I27Z
ISL12027AIV27Z
(No longer available
or supported)
VDD < VBAT
BSW =0
2.63
-40 to +85
8 Ld TSSOP
M8.173
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL12027, ISL12027A. For more information on MSL please see
techbrief TB363.
FN8232 Rev 9.00
September 23, 2015
Page 2 of 29
ISL12027, ISL12027A
Block Diagram
OSC COMPENSATION
X1
OSCILLATOR
X2
SCL
SDA
CONTROL
SERIAL
INTERFACE DECODE
LOGIC
DECODER
CONTROL/
REGISTERS
(EEPROM)
TIMER
FREQUENCY 1Hz CALENDAR
DIVIDER
LOGIC
STATUS
REGISTERS
(SRAM)
8
RESET
FN8232 Rev 9.00
September 23, 2015
WATCHDOG
TIMER
LOW VOLTAGE
RESET
TIME
KEEPING
REGISTERS
(SRAM)
BATTERY
SWITCH
CIRCUITRY
VDD
VBAT
COMPARE
ALARM
MASK
32.768kHZ
ALARM REGS
(EEPROM)
4k
EEPROM
ARRAY
Page 3 of 29
ISL12027, ISL12027A
Absolute Maximum Ratings
Thermal Information
Voltage on VDD, VBAT, SCL, SDA, and RESET pins
(respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on X1 and X2 pins
(respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V
Latchup (Note 4) . . . . . . . . . . . . . . . . . . . Class II, Level B @ +85°C
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175V
Thermal Resistance (Typical)
JA (°C/W)
JC (°C/W)
8 Ld SOIC Package (Notes 5, 6) . . . . .
115
50
8 Ld TSSOP Package (Notes 5, 6) . . .
140
40
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: Using a max positive pulse of 8.35V on all pins except X1 and
X2, Using a max positive pulse of 2.75V on X1 and X2, and using a max negative pulse of -1V for all pins.
5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. For JC, the “case temp” location is taken at the package top center.
DC Electrical Specifications
SYMBOL
Unless otherwise noted, VDD = +2.7V to +5.5V, TA = -40°C to +85°C, Typical values are at TA = +25°C and
VDD = 3.3V. Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
CONDITIONS
MIN
(Note 16)
TYP
MAX
(Note 16)
UNIT
VDD
Main Power Supply
2.7
5.5
V
VBAT
Backup Power Supply
1.8
5.5
V
Electrical Specifications
IDD2
IDD3
IBAT
Boldface limits apply over the operating temperature range, -40°C to +85°C.
MAX
(Note 16)
UNIT
NOTES
VDD = 2.7V
500
µA
7, 8, 9
VDD = 5.5V
800
µA
VDD = 2.7V
2.5
mA
VDD = 5.5V
3.5
mA
Supply Current for Main
Timekeeping (Low Power Mode)
VDD = VSDA = VSCL = 2.7V
10
µA
VDD = VSDA = VSCL = 5.5V
20
µA
Battery Supply Current
VBAT = 1.8V,
VDD = VSDA = VSCL= VRESET = 0V
800
1000
nA
VBAT = 3.0V,
VDD = VSDA = VSCL= VRESET = 0V
850
1200
nA
100
nA
2.6
V
11
SYMBOL
IDD1
NOTES
PARAMETER
Supply Current with
I2C
Active
Supply Current for Non-Volatile
Programming
IBATLKG
Battery Input Leakage
VTRIP
VBAT Mode Threshold
CONDITIONS
VDD = 5.5V, VBAT = 1.8V
MIN
(Note 16)
TYP
-100
1.8
2.2
7, 8, 9
9
7, 10, 11
VTRIPHYS VTRIP Hysteresis
30
mV
11, 14
VBATHYS
VBAT Hysteresis
50
mV
11, 14
VDD SR-
VDD Negative Slew rate
10
V/ms
12
VDD = 5.5V
IOL = 3mA
0.4
V
VDD = 2.7V
IOL = 1mA
0.4
V
400
nA
RESET OUTPUT
VOL
ILO
Output Low Voltage
Output Leakage Current
FN8232 Rev 9.00
September 23, 2015
VDD = 5.5V
VOUT = 5.5V
100
Page 4 of 29
ISL12027, ISL12027A
Watchdog Timer/Low Voltage Reset Parameters
SYMBOL
tRPD
PARAMETER
CONDITIONS
MIN
(Note 16)
TYP
(Note 5)
VDD Detect to RESET LOW
MA
(Note 16)
500
UNITS
NOTES
ns
13
tPURST
Power-up Reset Time-Out Delay
100
VRVALID
Minimum VDD for Valid RESET
Output
1.0
VRESET
ISL12027-4.5A Reset Voltage Level
4.59
4.64
4.69
V
ISL12027 Reset Voltage Level
4.33
4.38
4.43
V
ISL12027-3 Reset Voltage Level
3.04
3.09
3.14
V
ISL12027-2.7A Reset Voltage Level
2.87
2.92
2.97
V
ISL12027-2.7 Reset Voltage Level
2.58
2.63
2.68
V
1.70
1.75
1.801
s
725
750
775
ms
225
250
275
ms
225
250
275
ms
tWDO
Watchdog Timer Period
tRST
Watchdog Timer Reset Time-Out
Delay
tRSP
I2C Interface Minimum Restart Time
32.768kHz crystal between X1
and X2
32.768kHz crystal between X1
and X2
250
400
ms
V
1.2
µs
>2,000,000
Cycles
50
Years
EEPROM SPECIFICATIONS
EEPROM Endurance
EEPROM Retention
Temperature 75°C
Serial Interface (I2C) Specifications
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIL
SDA, and SCL Input Buffer LOW
Voltage
SBIB = 1 (Under VDD mode)
-0.3
0.3xVDD
V
VIH
SDA, and SCL Input Buffer HIGH
Voltage
SBIB = 1 (Under VDD mode)
0.7xVDD
VDD + 0.3
V
SBIB = 1 (Under VDD mode)
0.05xVDD
Hysteresis SDA and SCL Input Buffer
Hysteresis
VOL
SDA Output Buffer LOW Voltage
IOL = 4mA
ILI
Input Leakage Current on SCL
VIN = 5.5V
ILO
I/O Leakage Current on SDA
VIN = 5.5V
NOTES
V
0
0.4
V
0.1
10
µA
0.1
10
µA
400
kHz
TIMING CHARACTERISTICS
fSCL
SCL Frequency
tIN
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec
is suppressed.
50
ns
tAA
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of VDD,
until SDA exits the 30% to 70% of VDD
window.
900
ns
tBUF
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VDD during a
STOP condition, to SDA crossing 70%
of VDD during the following START
condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VDD crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VDD crossing.
600
ns
FN8232 Rev 9.00
September 23, 2015
Page 5 of 29
ISL12027, ISL12027A
Serial Interface (I2C) Specifications (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
tSU:STA
START Condition Set-up Time
SCL rising edge to SDA falling edge.
Both crossing 70% of VDD.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30%
of VDD to SCL falling edge crossing
70% of VDD.
600
ns
tSU:DAT
Input Data Set-up Time
From SDA exiting the 30% to 70% of
VDD window, to SCL rising edge
crossing 30% of VDD.
100
ns
tHD:DAT
Input Data Hold Time
From SCL falling edge crossing 70% of
VDD to SDA entering the 30% to 70%
of VDD window.
0
ns
tSU:STO
STOP Condition Set-up Time
From SCL rising edge crossing 70% of
VDD, to SDA rising edge crossing 30%
of VDD.
600
ns
tHD:STO
STOP Condition Hold Time for
Read, or Volatile Only Write
From SDA rising edge to SCL falling
edge. Both crossing 70% of VDD.
600
ns
Output Data Hold Time
From SCL falling edge crossing 30% of
VDD, until SDA enters the 30% to 70%
of VDD window.
0
ns
tR
SDA and SCL Rise Time
From 30% to 70% of VDD
20 +
0.1xCb
250
ns
tF
SDA and SCL Fall Time
From 70% to 30% of VDD
20 +
0.1xCb
250
ns
10
pF
20
ms
14
tDH
Cpin
SDA, and SCL Pin Capacitance
tWC
Non-Volatile Write Cycle Time
12
tR
SDA and SCL Rise Time
From 30% to 70% of VDD
20 +
0.1xCb
250
ns
15
tF
SDA and SCL Fall Time
From 70% to 30% of VDD
20 +
0.1xCb
250
ns
15
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
400
pF
15
SDA and SCL Bus Pull-up Resistor Maximum is determined by tR and tF.
Off-chip
For Cb = 400pF, max is about
2k~2.5k.
For Cb = 40pF, max is about
15k~20k
1
k
15
RPU
NOTES:
7. RESET Inactive (no reset).
8. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz.
9. VRESET = 2.63V (VDD must be greater than VRESET), VBAT = 0V.
10. Bit BSW = 0 (Standard Mode), ATR = 00h, VBAT ≥1.8V.
11. Specified at +25°C.
12. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
13. Parameter is not 100% tested.
14. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid STOP condition at the end of Write
sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.
15. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
16. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
FN8232 Rev 9.00
September 23, 2015
Page 6 of 29
ISL12027, ISL12027A
Timing Diagrams
tF
SCL
tHIGH
tLOW
tHD:STO
tR
tSU:DAT
tSU:STA
tHD:DAT
tHD:STA
SDA
(INPUT TIMING)
tSU:STO
tAA
tDH
tBUF
SDA
(OUTPUT TIMING)
FIGURE 1. BUS TIMING
SCL
8TH BIT OF LAST BYTE
SDA
ACK
tWC
STOP
CONDITION
START
CONDITION
FIGURE 2. WRITE CYCLE TIMING
tRSP
tRSP>tWDO
tRSP>tWDO
tRSP20ppm frequency
deviation translates into an accuracy of >1 minute per month.
These parameters are available from the crystal manufacturer.
Intersil’s RTC family provides on-chip crystal compensation
networks to adjust load-capacitance to tune oscillator
frequency from -34ppm to +80ppm when using a 12.5pF load
crystal. For more detailed information see “Application Section”
on page 22.
FN8232 Rev 9.00
September 23, 2015
CCR Access
The CCR is divided into 5 sections. These are:
1. Alarm 0 (8 bytes; non-volatile)
2. Alarm 1 (8 bytes; non-volatile)
3. Control (5 bytes; non-volatile)
4. Real Time Clock (8 bytes; volatile)
5. Status (1 byte; volatile)
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one section
of the CCR per operation. Access to another section requires a
new operation. A read or write can begin at any address in the
CCR.
It is not necessary to set the RWEL bit prior to writing the
status register. Section 5 (status register) supports a single
byte read or write only. Continued reads or writes from this
section terminates the operation.
The state of the CCR can be read by performing a random
read at any address in the CCR at any time. This returns the
contents of that register location. Additional registers are read
by performing a sequential read. The read instruction latches
all Clock registers into a buffer, so an update of the clock does
not change the time being read. A sequential read of the CCR
will not result in the output of data from the memory array. At
the end of a read, the master supplies a stop condition to end
the operation and free the bus. After a read of the CCR, the
address remains at the previous address +1 so the user can
execute a current address read of the CCR and continue
reading the next Register.
Real Time Clock Registers (Volatile)
SC, MN, HR, DT, MO, YR: Clock/Calendar Registers
These registers depict BCD representations of the time. As
such, SC (Seconds) and MN (Minutes) range from 00 to 59,
HR (Hour) is 1 to 12 with an AM or PM indicator (H21 bit) or 0
Page 10 of 29
ISL12027, ISL12027A
to 23 (with MIL = 1), DT (Date) is 1 to 31, MO (Month) is 1 to
12, YR (Year) is 0 to 99.
DW: Day of the Week Register
This register provides a Day of the Week status and uses three
bits DY2 to DY0 to represent the seven days of the week. The
counter advances in the cycle 0-1-2-3-4-5-6-0-1-2-… The
assignment of a numerical value to a specific day of the week
is arbitrary and may be decided by the system software
designer. The default value is defined as ‘0’.
Y2K: Year 2000 Register
Can have value 19 or 20. As of the date of the introduction of
this device, there would be no real use for the value 19 in a
true real time clock, however.
24 Hour Time
If the MIL bit of the HR register is 1, the RTC uses a 24-hour
format. If the MIL bit is 0, the RTC uses a 12-hour format and
H21 bit functions as an AM/PM indicator with a ‘1’,
representing PM. The clock defaults to standard time with H21
= 0.
Leap Years
Leap years add the day February 29 and are defined as those
years that are divisible by 4.
Status Register (SR) (Volatile)
The Status Register is located in the CCR memory map at
address 003Fh. This is a volatile register only and is used to
control the WEL and RWEL write enable latches, read power
status and two alarm bits. This register is separate from both
the array and the Clock/Control Registers (CCR).
TABLE 1. STATUS REGISTER (SR)
ADDR
7
6
003Fh
BAT
AL1
Default
0
0
5
4
AL0 OSCF
0
0
3
2
1
0
0
RWEL
WEL
RTCF
0
0
0
1
BAT: Battery Supply
This bit set to “1” indicates that the device is operating from
VBAT, not VDD. It is a read-only bit and is set/reset by hardware
(ISL12027 internally). Once the device begins operating from
VDD, the device sets this bit to “0”.
OSCF: Oscillator Fail Indicator
This bit is set to “1” if the oscillator is not operating, or is
operating but has clock jitter which does not affect the
accuracy of RTC counting. The bit is set to “0” if the oscillator is
functioning and does not have clock jitter. This bit is read only,
and is set/reset by hardware.
RWEL: Register Write Enable Latch
This bit is a volatile latch that powers up in the LOW (disabled)
state. The RWEL bit must be set to “1” prior to any writes to the
Clock/Control Registers. Writes to RWEL bit do not cause a
non-volatile write cycle, so the device is ready for the next
operation immediately after the stop condition. A write to the
CCR requires both the RWEL and WEL bits to be set in a
specific sequence.
WEL: Write Enable Latch
The WEL bit controls the access to the CCR during a write
operation. This bit is a volatile latch that powers up in the LOW
(disabled) state. While the WEL bit is LOW, writes to the CCR
address will be ignored, although acknowledgment is still
issued. The WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the Status Register. Once set, WEL
remains set until either reset to 0 (by writing a “0” to the WEL
bit and zeroes to the other bits of the Status Register) or until
the part powers up again. Writes to WEL bit do not cause a
non-volatile write cycle, so the device is ready for the next
operation immediately after the stop condition.
RTCF: Real Time Clock Fail Bit
This bit is set to a “1” after a total power failure. This is a read
only bit that is set by hardware (ISL12027 internally) when the
device powers up after having lost all power to the device (both
VDD and VBAT go to 0V). The bit is set regardless of whether
VDD or VBAT is applied first. The loss of only one of the
supplies does not set the RTCF bit to “1”. On power up after a
total power failure, all registers are set to their default states
and the clock will not increment until at least one byte is written
to the clock register. The first valid write to the RTC section
after a complete power failure resets the RTCF bit to “0”
(writing one byte is sufficient).
Unused Bits:
Bit 3 in the SR is not used, but must be zero. The Data Byte
output during a SR read will contain a zero in this bit location.
AL1, AL0: Alarm Bits
These bits announce if either alarm 0 or alarm 1 match the real
time clock. If there is a match, the respective bit is set to ‘1’.
The falling edge of the last data bit in a SR Read operation
resets the flags. Note: Only the AL bits that are set when an SR
read starts will be reset. An alarm bit that is set by an alarm
occurring during an SR read operation will remain set after the
read operation is complete.
FN8232 Rev 9.00
September 23, 2015
Page 11 of 29
ISL12027, ISL12027A
REG
NAME
7
6
Status
SR
BAT
AL1
AL0
RTC
(SRAM)
Y2K
0
0
Y2K21
ADDR.
TYPE
003F
0037
5
4
3
2
1
0
OSCF
0
RWEL
WEL
RTCF
Y2K20
Y2K13
0
0
Y2K10
RANG
E
19/20
ISL12027A
DEFAULT
BIT
ISL12027
DEFAULT
TABLE 2. CLOCK/CONTROL MEMORY MAP
01h
01h
20h
20h
DW
0
0
0
0
0
DY2
DY1
DY0
0-6
00h
00h
0035
YR
Y23
Y22
Y21
Y20
Y13
Y12
Y11
Y10
0-99
00h
00h
0034
MO
0
0
0
G20
G13
G12
G11
G10
1-12
00h
00h
0033
DT
0
0
D21
D20
D13
D12
D11
D10
1-31
01h
01h
0032
HR
MIL
0
H21
H20
H13
H12
H11
H10
0-23
00h
00h
0031
MN
0
M22
M21
M20
M13
M12
M11
M10
0-59
00h
00h
0-59
0036
0030
0014
0013
0012
Control
(EEPROM
)
SC
0
S22
S21
S20
S13
S12
S11
S10
PWR
SBIB
BSW
0
0
0
VTS2
VTS1
VTS0
00h
00h
4Xh
0Xh
DTR
0
0
0
0
0
DTR2
DTR1
DTR0
00h
00h
ATR
0
0
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
00h
00h
0011
INT
IM
AL1E
AL0E
0
0
0
0
0
00h
00h
0010
BL
BP2
BP1
BP0
WD1
WD0
0
0
0
18h
18h
Y2K1
0
0
0
0
A1Y2K10
19/20
20h
20h
DWA1
EDW1
0
DY2
DY1
DY0
0-6
00h
00h
000F
000E
000D
Alarm1
(EEPROM
)
000C
YRA1
MOA1
A1Y2K21 A1Y2K20 A1Y2K13
0
0
0
Unused - Default = RTC Year value (No EEPROM) - Future expansion
EMO1
0
0
A1G20
A1G13
A1G12
A1G11
A1G10
1-12
00h
00h
000B
DTA1
EDT1
0
A1D21
A1D20
A1D13
A1D12
A1D11
A1D10
1-31
00h
00h
000A
HRA1
EHR1
0
A1H21
A1H20
A1H13
A1H12
A1H11
A1H10
0-23
00h
00h
0009
MNA1
EMN1
A1M22
A1M21
A1M20
A1M13
A1M12
A1M11
A1M10
0-59
00h
00h
0008
SCA1
ESC1
A1S22
A1S21
A1S20
A1S13
A1S12
A1S11
A1S10
0-59
00h
00h
Y2K0
0
0
0
0
A0Y2K10
19/20
20h
20h
DWA0
EDW0
0
DY2
DY1
DY0
0-6
00h
00h
0007
0006
0005
0004
Alarm0
(EEPROM
)
YRA0
MOA0
A0Y2K21 A0Y2K20 A0Y2K13
0
0
0
Unused - Default = RTC Year value (No EEPROM) - Future expansion
EMO0
0
0
A0G20
A0G13
A0G12
A0G11
A0G10
1-12
00h
00h
0003
DTA0
EDT0
0
A0D21
A0D20
A0D13
A0D12
A0D11
A0D10
1-31
00h
00h
0002
HRA0
EHR0
0
A0H21
A0H20
A0H13
A0H12
A0H11
A0H10
0-23
00h
00h
0001
MNA0
EMN0
A0M22
A0M21
A0M20
A0M13
A0M12
A0M11
A0M10
0-59
00h
00h
0000
SCA0
ESC0
A0S22
A0S21
A0S20
A0S13
A0S12
A0S11
A0S10
0-59
00h
00h
NOTE: (Shaded cells indicate that NO other value is to be written to that bit. X indicates the bits are set according to the product variation, see device
“Ordering Information” on page 2).
FN8232 Rev 9.00
September 23, 2015
Page 12 of 29
ISL12027, ISL12027A
Alarm Registers (Non-Volatile)
Alarm0 and Alarm1
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make the
comparison. Note that there is no alarm byte for year.
Six analog trimming bits, ATR0 to ATR5, are provided in order
to adjust the on-chip load capacitance value for frequency
compensation of the RTC. Each bit has a different weight for
capacitance adjustment. For example, using a Citizen CFS206 crystal with different ATR bit combinations provides an
estimated ppm adjustment range from -34ppm to +80ppm to
the nominal frequency compensation.
The alarm function works as a comparison between the alarm
registers and the RTC registers. As the RTC advances, the
alarm will be triggered once a match occurs between the alarm
registers and the RTC registers. Any one alarm register,
multiple registers, or all registers can be enabled for a match.
See “Device Operation” on page 14 and “Application Section”
on page 22 for more information.
X1
CX1
CRYSTAL
OSCILLATOR
X2
CX2
Control Registers (Non-Volatile)
The Control Bits and Registers described in the following
section are non-volatile.
BL Register
BP2, BP1, BP0 - Block Protect Bits
The Block Protect Bits, BP2, BP1 and BP0, determine which
blocks of the array are write protected. A write to a protected
block of memory is ignored. The block protect bits will prevent
write operations to one of eight segments of the array. The
partitions are described in Table 3.
FIGURE 12. DIAGRAM OF ATR
The effective on-chip series load capacitance, CLOAD, ranges
from 4.5pF to 20.25pF with a mid-scale value of 12.5pF
(default). CLOAD is changed via two digitally controlled
capacitors, CX1 and CX2, connected from the X1 and X2 pins
to ground (see Figure 12). The value of CX1 and CX2 is given
Equation 1:
C X = 16 b5 + 8 b4 + 4 b3 + 2 b2 + 1 b1 + 0.5 b0 + 9 pF
(EQ. 1)
The effective series load capacitance is the combination of CX1
and CX2:
BP2
BP1
BP0
TABLE 3.
PROTECTED ADDRESSES
ISL12027
0
0
0
None (Default)
None
0
0
1
180h – 1FFh
Upper 1/4
0
1
0
100h – 1FFh
Upper 1/2
0
1
1
000h – 1FFh
Full Array
1
0
0
000h – 03Fh
First 4 Pages
1
0
1
000h – 07Fh
First 8 Pages
1
1
0
000h – 0FFh
First 16 Pages
1
1
1
000h – 1FFh
Full Array
ARRAY LOCK
Oscillator Compensation Registers
There are two trimming options.
• ATR. Analog Trimming Register
1
1
1
---------- + -----------
C
C
C LOAD = ----------------------------------X1
(EQ. 2)
X2
16 b5 + 8 b4 + 4 b3 + 2 b2 + 1 b1 + 0.5 b0 + 9
C LOAD = ----------------------------------------------------------------------------------------------------------------------------- pF
2
For example, CLOAD(ATR = 00000) = 12.5pF,
CLOAD(ATR = 100000) = 4.5pF, and
CLOAD(ATR = 011111) = 20.25pF. The entire range for the
series combination of load capacitance goes from 4.5pF to
20.25pF in 0.25pF steps. Note that these are typical values.
DTR Register - DTR2, DTR1, DTR0: Digital Trimming
Register
The digital trimming Bits DTR2, DTR1 and DTR0 adjust the
number of counts per second and average the ppm error to
achieve better accuracy.
• DTR. Digital Trimming Register
DTR2 is a sign bit. DTR2 = 0 means frequency compensation
is >0. DTR2 = 1 means frequency compensation is
